CN104064448B - The manufacture method of SiGe source /drain region - Google Patents
The manufacture method of SiGe source /drain region Download PDFInfo
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- CN104064448B CN104064448B CN201410339142.0A CN201410339142A CN104064448B CN 104064448 B CN104064448 B CN 104064448B CN 201410339142 A CN201410339142 A CN 201410339142A CN 104064448 B CN104064448 B CN 104064448B
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- 229910000577 Silicon-germanium Inorganic materials 0.000 title claims abstract description 55
- 238000000034 method Methods 0.000 title claims abstract description 49
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 24
- 239000002184 metal Substances 0.000 claims abstract description 22
- 229910052751 metal Inorganic materials 0.000 claims abstract description 22
- 238000000137 annealing Methods 0.000 claims abstract description 21
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 13
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 13
- 239000010703 silicon Substances 0.000 claims abstract description 13
- 239000000758 substrate Substances 0.000 claims abstract description 13
- 230000008569 process Effects 0.000 claims abstract description 11
- 238000002425 crystallisation Methods 0.000 claims abstract description 8
- 230000008025 crystallization Effects 0.000 claims abstract description 8
- 238000000151 deposition Methods 0.000 claims description 10
- QTBSBXVTEAMEQO-UHFFFAOYSA-N Acetic acid Chemical compound CC(O)=O QTBSBXVTEAMEQO-UHFFFAOYSA-N 0.000 claims description 9
- 239000003153 chemical reaction reagent Substances 0.000 claims description 7
- 238000004151 rapid thermal annealing Methods 0.000 claims description 6
- 238000001039 wet etching Methods 0.000 claims description 6
- 238000005229 chemical vapour deposition Methods 0.000 claims description 5
- 238000005224 laser annealing Methods 0.000 claims description 5
- 230000008021 deposition Effects 0.000 claims description 4
- 238000001755 magnetron sputter deposition Methods 0.000 claims description 4
- 150000007524 organic acids Chemical class 0.000 claims description 4
- 238000004544 sputter deposition Methods 0.000 claims description 4
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical group O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 claims description 3
- 229910052681 coesite Inorganic materials 0.000 claims description 3
- 229910052906 cristobalite Inorganic materials 0.000 claims description 3
- 229910017604 nitric acid Inorganic materials 0.000 claims description 3
- 239000000377 silicon dioxide Substances 0.000 claims description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 3
- 229910052682 stishovite Inorganic materials 0.000 claims description 3
- 229910052905 tridymite Inorganic materials 0.000 claims description 3
- NINIDFKCEFEMDL-UHFFFAOYSA-N Sulfur Chemical compound [S] NINIDFKCEFEMDL-UHFFFAOYSA-N 0.000 claims 1
- 239000005864 Sulphur Substances 0.000 claims 1
- 239000002253 acid Substances 0.000 claims 1
- 239000010408 film Substances 0.000 description 58
- 238000005516 engineering process Methods 0.000 description 11
- 239000010410 layer Substances 0.000 description 6
- QAOWNCQODCNURD-UHFFFAOYSA-N Sulfuric acid Chemical compound OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 3
- 229910052732 germanium Inorganic materials 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- 238000007740 vapor deposition Methods 0.000 description 2
- LKJPSUCKSLORMF-UHFFFAOYSA-N Monolinuron Chemical compound CON(C)C(=O)NC1=CC=C(Cl)C=C1 LKJPSUCKSLORMF-UHFFFAOYSA-N 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 230000006835 compression Effects 0.000 description 1
- 238000007906 compression Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 229910021419 crystalline silicon Inorganic materials 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 238000000407 epitaxy Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 230000001939 inductive effect Effects 0.000 description 1
- 235000005985 organic acids Nutrition 0.000 description 1
- 239000011241 protective layer Substances 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02524—Group 14 semiconducting materials
- H01L21/02532—Silicon, silicon germanium, germanium
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02656—Special treatments
- H01L21/02664—Aftertreatments
- H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
- H01L21/02672—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth using crystallisation enhancing elements
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The invention discloses a kind of manufacture method of SiGe source /drain region, it includes providing the N-type chip silicon substrate for being formed with grid, and etches the groove for forming source/drain region；The deposited metal film on chip；Ge films are deposited on metallic film；Annealing process is carried out to chip, by metal-induced crystallization, makes the Ge atoms permeatings in Ge films to the interface between metallic film and silicon substrate and is combined with Si, SiGe film is formed；The metallic film on surface and Ge films are removed, the PMOS source drain region with SiGe is formed.The present invention can effectively reduce the temperature of generation SiGe film, and improve the quality of SiGe film, so that boost device yield and device performance.
Description
Technical field
The present invention relates to semiconductor integrated circuit manufacturing process technology field, more particularly to a kind of system of SiGe source /drain region
Make method.
Background technology
With the development of semiconductor integrated circuit, MOSFET (mos field effect transistor) sizes subtract
It is small, continuously improve speed, performance, density and the functional unit cost of integrated circuit.Into after the 90nm technique epoch, with
IC-components size is greatly reduced, the junction depth of source/drain (elevatedsource/drain) it is more and more shallow, it is necessary to
Subsequent silicidation is used as to thicken source/drain using selective epitaxial technology (selective epi SiGe, abridge SEG)
(silicide) sacrifice layer (sacrificial layer) of reaction, so as to reduce series resistance.
And for 65/45nm technical matters, a kind of method of lifting PMOS transistor performance is：Etch PMOS source/drain electrode
Source drain recesses (i.e. source/drain region U or Sigma shape, " U " or " Σ " shape) are formed, then (S/D) is recessed in source/drain region
Epitaxial sige layer introduces the compression (compressive stress) to raceway groove inside groove, and this stress causes semiconductor die
Body lattice is distorted the simple stress (uniaxial stress) in (stretching is compressed), generation channel region, and then influences
The charge transport properties of band arrangement and semiconductor, by controlling size and the distribution of the stress in resulting devices, improve empty
The mobility (mobility) in cave (hole), so as to improve the performance of device.
Embedded germanium silicon source leakage technology (embedded SiGe, abridge eSiGe) be it is a kind of be used for improving PMOS performances should
Become silicon technology.It is to increase PMOS hole mobility by producing uniaxial compressive stress in channels, so as to improve transistor
Current driving ability, be 45nm and following technology for the core technology in high-performance technique.
The main method using selective epitaxial SiGe is thin in PMOS source and drain areas (PSD) directly epitaxy Si Ge at present
Film.Fig. 1 and Fig. 2 show the manufacture method of the prior art, and it includes：The N-type substrate 201 for being formed with grid 205, institute are provided
State grid 205 to protect with sacrifice layer 204, the groove 203 of source and drain will be formed on the substrate 201 by etching；With outside SEG methods
Prolong SiGe film 206, form the PMOS source drain region with SiGe.
Shortcoming using above-mentioned existing SEG methods formation SiGe source /drain region mainly has two aspects：(1) with technology node
Taper into, Ge content requirement more and more highers, SiGe critical thickness more and more thinner, the SiGe film for causing SEG methods to deposit
Middle defect is sharply increased, stress reduction, is unfavorable for device performance raising；(2) growth temperature of SEG methods it is general 600 DEG C with
On, the heat budget of small size cmos device is brought challenges.Therefore, it is badly in need of that a kind of SiGe film growth temperature is relatively low, film sinks
The product preferable process of quality manufactures SiGe source /drain region to substitute existing SEG methods.
The content of the invention
It is an object of the invention to make up above-mentioned the deficiencies in the prior art there is provided a kind of manufacture method of SiGe source /drain region,
The temperature of generation SiGe film can effectively be reduced, it is possible to the quality of SiGe film is improved, so that boost device yield and device
Part performance.
To achieve the above object, the present invention provides a kind of manufacture method of SiGe source /drain region, and it comprises the following steps：
Step S01 is there is provided the N-type chip silicon substrate for being formed with grid, and the grid has sacrifice layer protection, and in silicon lining
The groove of source/drain region will be formed by being etched on bottom；
Step S02, the deposited metal film on chip；
Step S03, deposits Ge films on metallic film；
Step S04, carries out annealing process to chip, by metal-induced crystallization, arrives the Ge atoms permeatings in Ge films
Interface between metallic film and silicon substrate is simultaneously combined with Si, forms SiGe film；
Step S05, the metallic film on surface and Ge films are removed, expose grid, formation has by wet etching
SiGe PMOS source drain region.
Further, in step S04 annealing process be rapid thermal annealing (RTA) or laser annealing, the rapid thermal annealing
Temperature is 300-550 DEG C, annealing time is 10-90 minutes, and the temperature of the laser annealing is 330-550 DEG C, annealing time is 3-
20 minutes.
Further, metallic film use can form the metal of metal-induced crystallization in step S02.
Further, the metallic film uses Al or Ni.
Further, the metallic film is deposited by the way of physical sputtering or chemical vapor deposition, and depositing temperature is 20-
300℃。
Further, step S03 is thin using atomic vapor deposition, magnetron sputtering or chemical vapor deposition manner deposition Ge
Film, depositing temperature is 20-300 DEG C.
Further, the Ge film thicknesses are not less than thickness of metal film.
Further, the Ge film thicknesses are 1-3 times of thickness of metal film.
Further, the thickness of the Ge films isThe thickness of the metallic film is
Further, the reagent that wet etching is selected in step S05 is to SiN, SiO2It is less than with SiGe etch rate
Further, one or more of the reagent in nitric acid, sulfuric acid, acetic acid or organic acid.
The manufacture method for the SiGe source /drain region that the present invention is provided, utilizes metal-induced crystallization principle (Metal Induced
Crystallization), by metallic film inducing action, during process annealing, the Ge atoms permeatings in Ge films are made
SiGe crystal grain is combined to form to the interface between metallic film and silicon substrate, and with Si, continuous single crystalline Si Ge is ultimately generated thin
Film, so that the effectively temperature of reduction generation SiGe film, and improve the quality of SiGe film, so that boost device yield and device
Part performance, and technique is simply controllable, it is with low cost.
Brief description of the drawings
For that can become apparent from understanding purpose, feature and advantage of the present invention, below with reference to preferable reality of the accompanying drawing to the present invention
Example is applied to be described in detail, wherein：
Fig. 1 and Fig. 2 are the schematic diagrames of SiGe source /drain region manufacture method in the prior art；
Fig. 3 is the schematic flow sheet of the manufacture method of first embodiment of the invention SiGe source /drain region；
Fig. 4 a to Fig. 4 e are the cross-sectional device views of each step of manufacture method of first embodiment of the invention SiGe source /drain region.
Embodiment
First embodiment
Refer in Fig. 3, Fig. 4 a to Fig. 4 e, the present embodiment, the manufacture method of SiGe source /drain region is to be based on 40nm technologies
In generation, it comprises the following steps：
Step S01, as shown in fig. 4 a there is provided the N-type chip silicon substrate 301 for being formed with grid 305, has on the grid 305
There are SiN sacrifice layers 304 to protect, on the silicon substrate 301, etch and will be formed between grid 305 and shallow trench isolation 302
The groove 303 of source/drain region；
Step S02, as shown in Figure 4 b, by physical sputtering technology under normal temperature, the deposited metal Al films 306 on chip,
Thickness is
Step S03, as illustrated in fig. 4 c, by magnetron sputtering technique under normal temperature, deposits Ge films 307 on metallic film,
Thickness is
Step S04, as shown in figure 4d, carries out annealing process to chip, in annealing heating environment, is lured by metal Al
Lead, make the Ge atoms permeatings in Ge films to the interface between metallic film and silicon substrate and combined with Si atoms, form SiGe
Film 308, its thickness is
Step S05, the metallic film on surface and Ge films as shown in fig 4e, removed by wet etching, expose grid
305, form the PMOS source drain region with SiGe.
Wherein, annealing process uses rapid thermal anneal process in the step S04 of the present embodiment, and its temperature is 400 DEG C, annealing
Time is 30min, in other embodiments, annealing process can also use laser annealing, annealing temperature can 300-550 DEG C it
Between, the annealing time of rapid thermal annealing can be between 10-90 minutes, and the annealing time of laser annealing can be in 3-20 minutes
Between.The metallic film of the present embodiment selects Al, in other embodiments, can form metal-induced crystallization from other
Metal, such as Ni.In the present embodiment, the technique of deposited metal film is physical sputtering, in other embodiments, can be using chemistry
The techniques such as vapour deposition carry out deposited metal film, and depositing temperature can be between 20-300 DEG C.In the present embodiment, Ge films are deposited
Technique be magnetron sputtering, in other embodiments, can be deposited using techniques such as atomic vapor deposition or chemical vapor depositions
Ge films, depositing temperature can be at 20-300 DEG C.
In actual manufacturing process, the SiGe thickness of formation is identical with Al film thicknesses, and SiGe generations can consume one
Quantitative Ge films, therefore in order to ensure the continuity of monocrystalline SiGe film growth in PSD regions, it is to be ensured that the thickness of Ge films
More than the thickness of Al films.It is preferred that Ge film thicknesses is between 1-3 times of Al film thicknesses, more preferably, Ge film thicknesses areAl film thicknesses are
On the other hand, the Ge contents in SiGe film can be adjusted by the change of annealing conditions.Because with annealing temperature
Degree rise, diffusion velocity of the Si atoms in Al films is faster than Ge atom, and the Ge contents in SiGe film can be reduced.
In the present embodiment, wet-etching technology is removed Al and Ge films from nitric acid and the mix reagent of acetic acid, but not
SiO in the protective layer SiN and shallow trench isolation on meeting damage gate surface2.In other embodiments, the reagent can also be it
He can remove metallic film and Ge films, but to SiN, SiO2It is less than with SiGe etch rateReagent, such as
Sulfuric acid, some organic acids etc..
Claims (11)
1. a kind of manufacture method of SiGe source /drain region, it is characterised in that it comprises the following steps：
Step S01 is there is provided the N-type chip silicon substrate for being formed with grid, and the grid has sacrifice layer protection, and in the N-type chip
The groove of source/drain region will be formed by being etched on silicon substrate；
Step S02, the deposited metal film on chip；
Step S03, deposits Ge films on metallic film；
Step S04, annealing process is carried out to chip, by metal-induced crystallization, makes Ge atoms permeatings in Ge films to metal
Interface between film and silicon substrate is simultaneously combined with Si, forms SiGe film；
Step S05, the metallic film on surface and Ge films are removed, expose grid, formed by wet etching with SiGe
PMOS source drain region.
2. the manufacture method of SiGe source /drain region according to claim 1, it is characterised in that：Annealing process is in step S04
Rapid thermal annealing or laser annealing, the temperature of the rapid thermal annealing is 300-550 DEG C, annealing time is 10-90 minutes, the laser
The temperature of annealing is 330-550 DEG C, annealing time is 3-20 minutes.
3. the manufacture method of SiGe source /drain region according to claim 2, it is characterised in that：Metallic film is adopted in step S02
With the metal of metal-induced crystallization can be formed.
4. the manufacture method of SiGe source /drain region according to claim 3, it is characterised in that：The metallic film using Al or
Ni。
5. the manufacture method of SiGe source /drain region according to claim 4, it is characterised in that：The metallic film uses physics
The mode of sputtering or chemical vapor deposition is deposited, and depositing temperature is 20-300 DEG C.
6. the manufacture method of SiGe source /drain region according to claim 2, it is characterised in that：Step S03 uses atom gas phase
Deposition, magnetron sputtering or chemical vapor deposition manner deposition Ge films, depositing temperature is 20-300 DEG C.
7. the manufacture method of SiGe source /drain region according to claim 6, it is characterised in that：The Ge film thicknesses are metal
1-3 times of film thickness.
8. the manufacture method of SiGe source /drain region according to claim 7, it is characterised in that：The thickness of the Ge films isThe thickness of the metallic film is
9. the manufacture method of the SiGe source /drain region according to any one of claim 1 to 8, it is characterised in that：In step S05
The reagent that wet etching is selected is to SiN, SiO2It is less than with SiGe etch rate
10. the manufacture method of SiGe source /drain region according to claim 9, it is characterised in that：The reagent is selected from nitric acid, sulphur
One or more in acid or organic acid.
11. the manufacture method of SiGe source /drain region according to claim 10, it is characterised in that：The organic acid is acetic acid.
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| CN201410339142.0A CN104064448B (en) | 2014-07-16 | 2014-07-16 | The manufacture method of SiGe source /drain region |
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| US10707298B2 (en) | 2018-09-05 | 2020-07-07 | Micron Technology, Inc. | Methods of forming semiconductor structures |
| US11018229B2 (en) * | 2018-09-05 | 2021-05-25 | Micron Technology, Inc. | Methods of forming semiconductor structures |
| US10790145B2 (en) | 2018-09-05 | 2020-09-29 | Micron Technology, Inc. | Methods of forming crystallized materials from amorphous materials |
Citations (3)
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|---|---|---|---|---|
| US7297618B1 (en) * | 2006-07-28 | 2007-11-20 | International Business Machines Corporation | Fully silicided gate electrodes and method of making the same |
| CN102208348A (en) * | 2010-03-29 | 2011-10-05 | 瑞萨电子株式会社 | Method of manufacturing semiconductor device |
| CN102468225A (en) * | 2010-11-18 | 2012-05-23 | 中芯国际集成电路制造(上海)有限公司 | Fuse structure and manufacturing method thereof |
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| US7504301B2 (en) * | 2006-09-28 | 2009-03-17 | Advanced Micro Devices, Inc. | Stressed field effect transistor and methods for its fabrication |
| JP2009016483A (en) * | 2007-07-03 | 2009-01-22 | Toshiba Corp | Semiconductor device and method for manufacturing semiconductor device |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7297618B1 (en) * | 2006-07-28 | 2007-11-20 | International Business Machines Corporation | Fully silicided gate electrodes and method of making the same |
| CN102208348A (en) * | 2010-03-29 | 2011-10-05 | 瑞萨电子株式会社 | Method of manufacturing semiconductor device |
| CN102468225A (en) * | 2010-11-18 | 2012-05-23 | 中芯国际集成电路制造(上海)有限公司 | Fuse structure and manufacturing method thereof |
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