CN104052508A - High speed serial data receiver architecture with dual error comparators - Google Patents
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Abstract
All embodiments of the invention generally relate to a high speed serial data receiver architecture with dual error comparators. Specifically, a receiver path includes first, second, third, and fourth comparator modules. The first comparator module is configured to generate, based on a signal received via the receiver path, a first digital output signal indicative of a sum of first data in the received signal and a first error. The second comparator module is configured to generate, based on the signal received via the receiver path, a second digital output signal indicative of a sum of second data in the received signal and a second error. The third comparator module is configured to generate, based on the signal received via the receiver path, a third digital output signal indicative of the first data in the received signal. The fourth comparator module is configured to generate, based on the signal received via the receiver path, a fourth digital output signal indicative of the second data in the received signal.
Description
the cross reference of related application
The application require on March 12nd, 2013 submit the 61/777th, No. 741 U.S. Provisional Applications and on March 10th, 2014 submit the 14/202nd, the rights and interests of No. 041 U.S.'s application for a patent for invention.The application be involved in submit on August 8th, 2013 the 13/962nd, No. 900 U.S. Patent applications.Whole disclosures of above-mentioned application of quoting are incorporated into this with way of reference.
Technical field
The present invention relates to the comparator in the receiver path of communication interface.
Background technology
Background technology provided herein is described for presenting in general manner the object of background of the present disclosure.All many-sides of current nominated inventor's work (to the degree of the work of partly describing in this background technology) and this description that possibly cannot otherwise be weighed as prior art when submitting to, are not neither admitted for the prior art for present disclosure clearly implicitly yet.
Signal path between transmitter and receiver (for example receiver path of serial data interface) comprises communication channel.For example, serial data interface can be high speed data interface.The data that send via communication channel may be changed by the decay of noise, interference and/or frequency dependence and dispersion.The decay of frequency dependence can be incorporated into distortion in the signal of transmission.For example, distortion can comprise intersymbol interference (ISI) and shake.Distortion can cause error as in the signal being received by receiver.
Can use difference signaling to realize communication channel.Difference signaling can reduce the impact of the interference (such as common-mode noise) of some form.Can in communication channel, use equalizer such as continuous time linear equalizer (CTLE) with partly compensate for channel decay.CTLE may be implemented as has differential amplifier fixing or programmable frequency dependence degeneration (degeneration) feature.For example, can realize programmable frequency dependence and degenerate, this allows to adjust one or more resistance and/or the capacitance in differential amplifier.Resistance and capacitance can also limit " rolling a little ", and it refers to differential amplifier and will at it, start to promote the minimum frequency of the output signal of differential amplifier.
Fig. 1 illustrates receiver path 100 (for example Gbps serial receiver), and it comprises communication channel 104, equalizer 108, error comparator module 112 and data comparator module 116.Error comparator module 112 comprises sampler 120, summer 124, decision-feedback estimation (DFE) module 128 and amplitude limiter (slicer) 132.Equalizer 108 can be for example switching regulator continuous time linear equalizer (CTLE) or the switching regulator CTLE with integrated sampler.
Equalizer 108 receives input signal 136 and generating output signal 140 via communication channel 104.Each signal in input signal 136 and output signal 140 can comprise Difference signal pair.108 pairs of input signals of equalizer 136 are carried out equalization with generating output signal 140.For example, equalizer 108 can comprise differential amplifier.
The input signal 136 receiving from communication channel 104 can comprise decay (for example frequency-dependent attenuation).For example, the frequency-dependent attenuation being caused by kelvin effect and dielectric loss (it is that two kinds of decay in communication channel 104 may be originated) is proportional with square root and the frequency of frequency respectively.Any decay in equalizer 108 compensated input signals 136 is with generating output signal 140.
120 pairs of output signals 140 of sampler sample to generate sampled signal 144.Summer 124 receives the output 148 of sampled signal 144 and DFE module 128.For example, summer 124 can be added the one or more signals corresponding to output 148 and sampled signal 144 or deduct one or more signals from sampled signal 144.Amplitude limiter 132 receives the output 152 of summer 124 and determines the digital value corresponding to input signal 136.It is for example the numeral output 156 of numeral high (for example " 1 ") or numeral low (for example " 0 ") that amplitude limiter 132 generates.Numeral output 156 can be exported corresponding to digital error.In some implementations, amplitude limiter 132 can be determined corresponding to the multiple bit digital value of input signal 136 and generate corresponding multiple bit digital output 156.In some implementations, can omit summer 124 and DFE module 128, and equalizer 108 replaces and is connected directly to amplitude limiter 132.
Similarly, data comparator module 116 comprises sampler 160, summer 164, DFE module 168 and amplitude limiter 172.160 pairs of output signals 140 of sampler sample to generate sampled signal 176.Summer 164 receives the output 180 of sampled signal 176 and DFE module 168.Amplitude limiter 172 receives the output 184 of summer 164 and determines the digital value corresponding to input signal 136.Amplitude limiter 172 generating digital outputs 188.Numeral output 188 can be exported corresponding to numerical data.In some embodiments, amplitude limiter 172 can be determined corresponding to the multiple bit digital value of input signal 136 and generate corresponding multiple bit digital output 188.
Numeral adaptation module 192 receives numeral output 156 and 188 from error comparator module 112 and data comparator module 116 respectively.Numeral adaptation module 192 generates corresponding feedback signal 196-1 and 196-2 (being referred to as feedback signal 196) based on numeral output 156 and 188, and generating digital output signal 200.Feedback signal 196 is provided to error comparator module 112 and data comparator module 116.
Feedback signal 196 comprises digital analog converter (DAC) value and polarity.The feedback signal 196-1 that is provided to error comparator module 112 can also comprise error input.DFE module 128 generates output 148 based on feedback signal 196-1.For example, DFE module 128 can comprise one or more DAC, and feedback signal 196-1 is corresponding to the optimal value of the numeral input of DAC.In this way, digital adaptation module 192 is adaptive or train DFE module 128, until optimal value is determined.Similarly, DFE module 168 generates output 180 based on feedback signal 196-2.
Clock such as data clock 204 is provided to each module in error comparator module 112 and data comparator module 116.For example, the data clock 204 that is provided to error comparator module 112 and data comparator module 116 can be same clock.
Fig. 2 illustrates receiver path 220, comprises communication channel 224, equalizer 228, error comparator module 232, odd data comparator module 236 and even data comparator module 240.Each module in error comparator module 232, odd data comparator module 236 and even data comparator module 240 receives the output 244 of equalizer 228 and correspondingly provides corresponding numeral output 248,252 and 256 to digital adaptation module 260.Numeral adaptation module 260 provides corresponding feedback signal 264-1,264-2 and 264-3 (being referred to as feedback signal 264) based on numeral output 248,252 and 256, and generating digital output 268.
Receiver path 220 can be corresponding to for example ultrahigh speed receiver path.In ultrahigh speed receiver path, each module in error comparator module 232, odd data comparator module 236 and even data comparator module 240 can for example, be carried out clock timing according to data rate half (data are received half of speed used by receiver path 220).Therefore, each module in error comparator module 232, odd data comparator module 236 and even data comparator module 240 receives half rate clock.For example, odd data comparator module 236 receives odd data clock 272, and even data comparator module receives even data clock 276.It is poor that odd data clock 272 and even data clock 276 have the nominal phase of 180 degree.As shown, error comparator module 232 receives odd data clock 272, but error comparator module 232 can be configured to receive the arbitrary clock in odd data clock 272 or even data clock 276.
Summary of the invention
Receiver path comprises first comparator module, and the signal that the first comparator module is configured to based on receiving via receiver path generates the first digital output signal.The first data and the first error sum associated with the first comparator module in the signal that the first digital output signal indication receives.The signal that the second comparator module is configured to based on receiving via receiver path generates the second digital output signal.The second data and the second error sum associated with the second comparator module in the signal that the second digital output signal indication receives.The signal that the 3rd comparator module is configured to based on receiving via receiver path generates the 3rd digital output signal.The first data in the signal that the 3rd digital output signal indication receives.The signal that the 4th comparator module is configured to based on receiving via receiver path generates the 4th digital output signal.The second data in the signal that the 4th digital output signal indication receives.
In further feature, the first error is corresponding to strange error, and the second error is corresponding to even error, and the first data are corresponding to odd data, and the second data are corresponding to even data.The first comparator module and the 3rd comparator module receive the first clock signal, and the second comparator module and the 4th comparator module reception second clock signal.The first clock signal is strange clock signal, and ii) second clock signal is even clock signal.The first clock signal and second clock signal have the phase difference of about 180 degree.
In further feature, the first sampler is configured to provide the first sample to the first comparator module and the 3rd comparator module of the signal of reception.The first sample is corresponding to the first data in the signal receiving.The second sampler is configured to provide the second sample to the second comparator module and the 4th comparator module of the signal of reception.The second sample is corresponding to the second data in the signal receiving.
For operating the method for receiver path, comprise that the signal based on receiving via receiver path generates first digital output signal, the first data and the first error sum associated with the first digital output signal in the signal that wherein the first digital output signal indication receives; Signal based on receiving via receiver path generates the second digital output signal, the second data and the second error sum associated with digital output signal in the signal that wherein the second digital output signal indication receives; Signal based on receiving via receiver path generates the 3rd digital output signal, the first data in the signal that wherein the 3rd digital output signal indication receives; And the signal based on receiving via receiver path generates the 4th digital output signal, the second data in the signal that wherein the 4th digital output signal indication receives.
In further feature, the first error is corresponding to strange error, and the second error is corresponding to even error, and the first data are corresponding to odd data, and the second data are corresponding to even data.Generate the first digital output signal and comprise and receive the first clock signal with generation the 3rd digital output signal, and generation the second digital output signal comprises reception second clock signal with generation the 4th digital output signal.The first clock signal is strange clock signal, and second clock signal is even clock signal.The first clock signal and second clock signal have the phase difference of about 180 degree.
In further feature, generate digital output of the first digital output signal and generation the 3rd and comprise the first sample that generates the signal receiving.The first sample is corresponding to the first data in the signal receiving.Generate the second digital output signal and generate the 4th digital output signal and comprise the second sample that generates the signal receiving.The second sample is corresponding to the second data in the signal receiving.
The in addition applicable aspect of present disclosure will become apparent according to embodiment, claim and accompanying drawing.Embodiment and particular example are only intended to the object of explanation, and are not intended to limit the scope of the disclosure.
Accompanying drawing explanation
Fig. 1 is the functional block diagram of receiver path.
Fig. 2 is the functional block diagram that comprises the receiver path of odd data comparator module and even data comparator module.
Fig. 3 is the functional block diagram that comprises the receiver path of strange error comparator module and even error comparator module.
Fig. 4 is the functional block diagram that comprises the receiver path in shared parity circuitry path.
The method of Fig. 5 illustrated operation receiver path.
In the accompanying drawings, can reuse Reference numeral to identify similar and/or identical element.
Embodiment
Receive respectively in the odd data comparator module of odd data clock and even data clock and the receiver path of even data comparator module having, odd data clock and even data clock may not aimed at completely.Therefore,, if use one of odd data clock and even data clock to carry out clock timing to the error comparator module in receiver path, between error comparator module and data comparator module, may there is mismatch.According to the receiver path of the principle of present disclosure, comprise strange error comparator module and even error comparator module.Strange error comparator module receives odd data clock, and even error comparator module receives even data clock.
Fig. 3 illustrates receiver path 300, comprises communication channel 304, equalizer 308, strange error comparator module 312, even error comparator module 316, odd data comparator module 320 and even data comparator module 324.Each module in strange error comparator module 312, even error comparator module 316, odd data comparator module 320 and even data comparator module 324 receives the output 328 of equalizer 308 and correspondingly provides corresponding numeral output 332,336,340 and 344 to digital adaptation module 348.Numeral adaptation module 348 provides corresponding feedback signal 352-1,352-2,352-3 and 352-4 (being referred to as feedback signal 352) based on numeral output 332,336,340 and 344, and generating digital output 356.
Correspondingly, between each module in digital adaptation module 348 and strange error comparator module 312, even error comparator module 316, odd data comparator module 320 and even data comparator module 324, form corresponding self-adaption loop.For example, numeral output 332 and feedback signal 352-1 are formed on the first self-adaption loop between strange error comparator module 312 and digital adaptation module 348.Numeral output 336 and feedback signal 352-2 are formed on the second self-adaption loop between even error comparator module 316 and digital adaptation module 348.Numeral output 340 and feedback signal 352-3 are formed on the 3rd self-adaption loop between odd data comparator module 320 and digital adaptation module 348.Numeral output 344 and feedback signal 352-4 are formed on the four selfs adaptation loop between even data comparator module 324 and digital adaptation module 348.
Receiver path 300 can be corresponding to for example ultrahigh speed receiver path.Correspondingly, each module in strange error comparator module 312, even error comparator module 316, odd data comparator module 320 and even data comparator module 324 can for example, be carried out clock timing according to data rate half (data are received half of speed used by receiver path 300).Each module in strange error comparator module 312, even error comparator module 316, odd data comparator module 320 and even data comparator module 324 receives half rate clock.For example, odd data comparator module 320 receives odd data clock 360, and even data comparator module 324 receives even data clock 364.It is poor that odd data clock 360 and even data clock 364 have the nominal phase of 180 degree.
Further, strange error comparator module 312 also receives odd data clock 360.On the contrary, even error comparator module 316 receives even data clock 364.In this way, error comparator module 312 and 316 and data comparator module 320 and 324 between mismatch error be minimized, this is because strange error comparator module 312 and odd data comparator module 320 receive same clock 360, and even error comparator module 316 and the same clock 364 of even data comparator module 324 reception.
Fig. 4 illustrates receiver path 400, comprises communication channel 404, equalizer 408, strange error comparator module 412, odd data comparator module 416, even error comparator module 420 and even data comparator module 424.Each module in strange error comparator module 412, odd data comparator module 416, even error comparator module 420 and even data comparator module 424 comprises corresponding summer 428 and amplitude limiter 432, and provides corresponding numeral output 436,440,444 and 448 to digital adaptation module 452.Numeral adaptation module 452 provides corresponding feedback signal 456-1,456-2,456-3 and 456-4 (being referred to as feedback signal 456) to strange error comparator module 412, odd data comparator module 416, even error comparator module 420 based on numeral output 436,440,444 and 448, and generating digital output 460.
Each module in strange error comparator module 412, odd data comparator module 416, even error comparator module 420 and even data comparator module 424 can for example, be carried out clock timing according to data rate half (data are received half of speed used by receiver path 400).Each module in strange error comparator module 412, odd data comparator module 416, even error comparator module 420 and even data comparator module 424 receives half rate clock.For example, strange error comparator module 412 and odd data comparator module 416 receive odd data clock 464.Even error comparator module 420 and even data comparator module 424 receive even data clock 468.It is poor that odd data clock 464 and even data clock 468 have the nominal phase of 180 degree.
Strange error comparator module 412 and odd data comparator module 416 share sampler 472, summer 476 and DFE module 480.For example, some in the DFE module of strange error comparator module 412 and odd data comparator module 416 or all DAC can be moved to DFE module 480.Although as shown, strange error comparator module 412 and odd data comparator module 416 still comprise DFE module 484, if related DAC be moved to shared DFE module 480, can remove DFE module 484.Sampler 472 uses odd data clock 464 to carry out clock timing.
On the contrary, even error comparator module 420 and even data comparator module 424 share sampler 488, summer 492 and DFE module 496.For example, some in the DFE module of even error comparator module 420 and even data comparator module 424 or all DAC can be moved to DFE module 496.Although as shown, even error comparator module 420 and even data comparator module 424 still comprise DFE module 500, if related DAC be moved to shared DFE module 496, can remove DFE module 500.Sampler 488 uses odd data clock 468 to carry out clock timing.
Numeral adaptation module 452 provides respectively additional feedback signal 504-1 and 504-2 (being referred to as feedback signal 504) to DFE module 480 and 496.Yet if remove as mentioned above DFE module 484 and 500, digital adaptation module 452 can only provide feedback signal 504 and feedback signal 456 is not provided.Further, can provide from same clock and data recovery loop or can from independently or part independently clock and data recovery loop odd data clock 464 and even data clock 468 are provided.
Correspondingly, due to the DAC of strange error comparator module 412 and odd data comparator module 416 shared sampler 472, summer 476 and DFE modules 480, so the mismatch error between strange error comparator module 412 and odd data comparator module 416 is further reduced.Similarly, due to the DAC of even error comparator module 420 and even data comparator module 424 shared sampler 488, summer 492 and DFE modules 496, so the mismatch error between even error comparator module 420 and even data comparator module 424 is further reduced.
Fig. 5 illustrates the method 520 that operation comprises the receiver path of strange error comparator module and even error comparator module.Method 520 starts from 524.528,520 pairs of signal samplings that receive via communication channel of method.532, sampled signal is provided to each module in strange error comparator module, odd data comparator module, even error comparator module and even data comparator module.536, strange error comparator module, odd data comparator module, even error comparator module and even data comparator module provide corresponding digital output signal based on sampled signal and corresponding feedback signal.540, the digital adaptation of method 520 use generates corresponding feedback signal and is provided to strange error comparator module, odd data comparator module, even error comparator module and even data comparator module.544, method 520 provides digital output signal.The method ends at 548.
More than describing is only illustrative in essence, and is not intended to limit present disclosure, its application or use.The broad teachings of present disclosure can realize with various forms.Therefore,, although present disclosure comprises particular example, because other is modified in research accompanying drawing, specification and following claim, will become apparent afterwards, so the true scope of present disclosure should so not limited.As used herein, phrase " at least one in A, B, C " is appreciated that the logic (A or B or C) that means to use non-exclusive logic OR.Should be understood that, the one or more steps in method can not change by different order (or side by side) execution the principle of present disclosure.
(comprise giving a definition) in this application, term " module " can use term " circuit " to replace.Term " module " can refer to a part for the following or comprise the following: application-specific integrated circuit (ASIC) (ASIC), numeral, simulation or hybrid analog-digital simulation/digital discrete circuit; Numeral, simulation or hybrid analog-digital simulation/digital integrated circuit; Combinational logic circuit; Field programmable gate array (FPGA); (share, special use or group) processor of run time version; (share, special use or group) memory of the code that storage is carried out by processor; Other applicable hardware component of described function is provided; Or above some or the combination of all in every, for example, with the form of SOC (system on a chip).
As above used, term " code " can comprise software, firmware and/or microcode, and can refer to program, routine, function, class and/or object.Term " shared processing device " comprises the single processor of carrying out from the some or all of codes of a plurality of modules.Term " group processor " comprises with Attached Processor and combines to carry out the processor from the some or all of codes of one or more modules.Term " shared storage " comprises that storage is from the single memory of the some or all of codes of a plurality of modules.Term " group memory " comprises with annex memory and combines to store the memory from the some or all of codes of one or more modules.Term " memory " is the subset of term " computer-readable medium ".As used herein, term " computer-readable medium " does not comprise the transient state signal of telecommunication or the electromagnetic signal of propagating by medium (such as on carrier wave); Therefore it is tangible with non-transient that term " computer-readable medium " can be considered to.Non-limiting example non-transient, tangible computer-readable medium comprises nonvolatile memory (such as flash memory), volatile memory (such as static RAM and dynamic random access memory), magnetic storage (such as tape or hard disk) and optical storage.
The apparatus and method of describing in this application can partly or completely be realized by the performed one or more computer programs of one or more processors.Computer program is included in the executable instruction of processor of storing at least one non-transient, tangible computer-readable medium.Computer program can also comprise and/or depend on the data of storage.
Claims (20)
1. a receiver path, comprising:
The first comparator module, the signal being configured to based on receiving via described receiver path generates the first digital output signal, the first data and the first error sum associated with described the first comparator module in the described signal that wherein said the first digital output signal indication receives;
The second comparator module, the described signal being configured to based on receiving via described receiver path generates the second digital output signal, the second data and the second error sum associated with described the second comparator module in the described signal that wherein said the second digital output signal indication receives;
The 3rd comparator module, the described signal being configured to based on receiving via described receiver path generates the 3rd digital output signal, described the first data in the described signal that wherein said the 3rd digital output signal indication receives; And
The 4th comparator module, the described signal being configured to based on receiving via described receiver path generates the 4th digital output signal, described the second data in the described signal that wherein said the 4th digital output signal indication receives.
2. receiver path according to claim 1, wherein said the first error is corresponding to strange error, and described the second error is corresponding to even error, and described the first data are corresponding to odd data, and described the second data are corresponding to even data.
3. receiver path according to claim 1, i wherein) described the first comparator module and described the 3rd comparator module receive the first clock signal, and ii) described the second comparator module and described the 4th comparator module receive second clock signal.
4. receiver path according to claim 3, wherein i) described the first clock signal is strange clock signal, and ii) described second clock signal is even clock signal.
5. receiver path according to claim 3, wherein said the first clock signal and described second clock signal have the phase differences of about 180 degree.
6. receiver path according to claim 3, further comprises:
The first sampler, is configured to provide first sample of described signal of reception to described the first comparator module and described the 3rd comparator module, and wherein said the first sample is corresponding to described the first data in the described signal receiving; And
The second sampler, is configured to provide second sample of described signal of reception to described the second comparator module and described the 4th comparator module, and wherein said the second sample is corresponding to described the second data in the described signal receiving.
7. receiver path according to claim 6, wherein i) described the first sampler receives described the first clock signal, and ii) described the second sampler receives described second clock signal.
8. receiver path according to claim 6, further comprises:
The first decision-feedback estimation module, is configured to i) revise described the first sample, and ii) provide described first sample of modification to described the first comparator module and described the 3rd comparator module; And
The second decision-feedback estimation module, is configured to i) revise described the second sample, and ii) provide described second sample of modification to described the second comparator module and described the 4th comparator module.
9. receiver path according to claim 8, i wherein) described the first decision-feedback estimation module is configured to revise described the first sample based on the first feedback signal, and ii) described the second decision-feedback estimation module is configured to revise described the second sample based on the second feedback signal.
10. receiver path according to claim 9, further comprises digital adaptation module, and described digital adaptation module is configured to:
Based on described the first digital output signal and described the 3rd digital output signal, generate described the first feedback signal; And
Based on described the second digital output signal and described the 3rd digital output signal, generate described the second feedback signal.
11. 1 kinds for operating the method for receiver path, and described method comprises:
Signal based on receiving via described receiver path, generates the first digital output signal, the first data and the first error sum associated with described the first digital output signal in the described signal that wherein said the first digital output signal indication receives;
Described signal based on receiving via described receiver path, generates the second digital output signal, the second data and the second error sum associated with described digital output signal in the described signal that wherein said the second digital output signal indication receives;
Described signal based on receiving via described receiver path, generates the 3rd digital output signal, described the first data in the described signal that wherein said the 3rd digital output signal indication receives; And
Described signal based on receiving via described receiver path, generates the 4th digital output signal, described the second data in the described signal that wherein said the 4th digital output signal indication receives.
12. methods according to claim 11, wherein said the first error is corresponding to strange error, and described the second error is corresponding to even error, and described the first data are corresponding to odd data, and described the second data are corresponding to even data.
13. methods according to claim 11, wherein generate described the first digital output signal and generate described the 3rd digital output signal and comprise and receive the first clock signal, and wherein generate described the second digital output signal and generate described the 4th digital output signal and comprise and receive second clock signal.
14. method according to claim 13, wherein i) described the first clock signal is strange clock signal, and ii) described second clock signal is even clock signal.
15. methods according to claim 13, wherein said the first clock signal and described second clock signal have the phase difference of about 180 degree.
16. methods according to claim 13, wherein:
Generate described the first digital output signal and generate the first sample that described the 3rd numeral output comprises the described signal that generation receives, wherein said the first sample is corresponding to described the first data in the described signal receiving; And
Generate described the second digital output signal and generate the second sample that described the 4th digital output signal comprises the described signal that generates reception, wherein said the second sample is corresponding to described the second data in the described signal receiving.
17. method according to claim 16, wherein i) generate described the first sample comprise receive described the first clock signal and ii) generate described the second sample and comprise and receive described second clock signal.
18. methods according to claim 16, further comprise:
Revise described the first sample; And
Revise described the second sample.
19. methods according to claim 18, wherein revise described the first sample and comprise based on the first feedback signal and revise described the first sample, and wherein revise described the second sample and comprise based on the second feedback signal and revise described the second sample.
20. methods according to claim 19, further comprise:
Based on described the first digital output signal and described the 3rd digital output signal, generate described the first feedback signal; And
Based on described the second digital output signal and described the 3rd digital output signal, generate described the second feedback signal.
Applications Claiming Priority (4)
| Application Number | Priority Date | Filing Date | Title |
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| US201361777741P | 2013-03-12 | 2013-03-12 | |
| US61/777,741 | 2013-03-12 | ||
| US14/202,041 US9367385B2 (en) | 2013-03-12 | 2014-03-10 | High speed serial data receiver architecture with dual error comparators |
| US14/202,041 | 2014-03-10 |
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| US20020172103A1 (en) * | 2001-05-17 | 2002-11-21 | Fujitsu Limited | Information access device, information access method, and information storage medium access system |
| US20090224806A1 (en) * | 2008-03-05 | 2009-09-10 | Sun Microsystems, Inc. | Analog baud rate clock and data recovery |
| US20090232196A1 (en) * | 2008-03-14 | 2009-09-17 | Nec Coropration | Apparatus and method for decision feedback equalization |
| CN101794295A (en) * | 2010-01-06 | 2010-08-04 | 哈尔滨工程大学 | Regular expression-oriented multi-mode matching hardware engine and generating method |
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020172103A1 (en) * | 2001-05-17 | 2002-11-21 | Fujitsu Limited | Information access device, information access method, and information storage medium access system |
| US20090224806A1 (en) * | 2008-03-05 | 2009-09-10 | Sun Microsystems, Inc. | Analog baud rate clock and data recovery |
| US20090232196A1 (en) * | 2008-03-14 | 2009-09-17 | Nec Coropration | Apparatus and method for decision feedback equalization |
| CN101794295A (en) * | 2010-01-06 | 2010-08-04 | 哈尔滨工程大学 | Regular expression-oriented multi-mode matching hardware engine and generating method |
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