CN104051489A - Low Profile Image Sensor - Google Patents
Low Profile Image Sensor Download PDFInfo
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- CN104051489A CN104051489A CN201410160097.2A CN201410160097A CN104051489A CN 104051489 A CN104051489 A CN 104051489A CN 201410160097 A CN201410160097 A CN 201410160097A CN 104051489 A CN104051489 A CN 104051489A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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Abstract
The invention relates to a lower profile image sensor. A sensor package comprises a host substrate with opposing first and second surfaces, an aperture extending therethrough, circuit layers, and first contact pads. A second substrate at least partially in the aperture has opposing first and second surfaces, a plurality of photo detectors, second contact pads at the second substrate first surface and electrically coupled to the photo detectors, and trenches formed into the second substrate first surface, conductive traces extending from the second contact pads and into the trenches. A third substrate has a first surface mounted to the first surface of the second substrate. The third substrate includes a cavity formed into its first surface and positioned over the photo detectors. Electrical connectors connect the first contact pads and conductive traces. A lens module is mounted to the host substrate for focusing light through the third substrate and onto the photo detectors.
Description
related application
The application requires the rights and interests of the U.S. Provisional Application number 61/778267 of submitting on March 12nd, 2013, and is attached to by reference herein.
Technical field
The present invention relates to a kind of encapsulation of microelectronic component, and relate more specifically to a kind of encapsulation of optical semiconductor device.
Background technology
The trend of semiconductor device is less integrated circuit (IC) device (also referred to as chip) being encapsulated in less encapsulation (it protects chip, provides from sheet signaling connectedness simultaneously).An example is imageing sensor, and it is to have comprised the IC device that incident light is transformed into the photodetector of the signal of telecommunication (it has accurately reflected incident light intensity and color information with good spatial resolution).
There is different actuating forces behind in the research and development in the wafer-class encapsulation solution for imageing sensor.For example, the form factor (density, increasing in order to realize highest-capacity/volume ratio) reducing has overcome spatial limitation and can realize less camera module solution.The electric property increasing can utilize shorter interconnection length to realize, and this has improved electric property and has therefore improved device speed, and this has reduced chip power-consumption strongly.
Current, chip on board (COB-wherein bare chip is directly installed on printed circuit board (PCB)) and housing box (Shellcase) wafer level chip size package (wherein wafer is laminated between two glass flakes) are main encapsulation and the packaging technologies (for example, for mobile device camera, optical mouse etc.) for building image sensor module.But, in the time using the imageing sensor of higher pixel, due to the assembling restriction for 8 inches and 12 inches image sensor wafers of encapsulation, size restrictions (for the more requirement of low profile device), production problems and capital investment in early stage, COB and housing box WLCSP assembling become more and more difficult.In addition, the WLP encapsulation of standard is the encapsulation of fan-in formula, and wherein chip area equals package area, has therefore limited the number that I/O connects.
Need improved encapsulation and encapsulation technology, its provide be cost effectively and use the low profile encapsulation solution of simplified structure.
Summary of the invention
A kind of image sensor package, comprises main substrate assembly and the sensor chip that is mounted to main substrate assembly.Main substrate assembly comprises multiple the first contact pads that have first substrate on the first and second relative surfaces, the perforate that runs through the first substrate between the first and second surfaces, one or more circuit layer and be electrically coupled to one or more circuit layers.Sensor chip is arranged in perforate at least in part, and comprise second substrate with the first and second relative surfaces, be formed on the second substrate or among multiple photodetectors, be formed on multiple second contact pads that are electrically coupled to photodetector at the first surface place of the second substrate, be formed into the one or more grooves in the first surface of the second substrate, each from the second contact pad one is extended and extends to the multiple conductive traces in one or more grooves, and there is the 3rd substrate of the first surface that is mounted to the second substrate first surface, wherein the 3rd substrate comprises the cavity on photodetector that is positioned in the first surface that is formed into the 3rd substrate.Each of electric connector is electrically connected with in multiple conductive traces one one in the first contact pad.Lens module is mounted to main substrate assembly, and wherein lens module comprises and arranging for focused light through the 3rd substrate and focus on the one or more lens on photodetector.
In another aspect, a kind of image sensor package comprises main substrate assembly and the sensor chip that is mounted to main substrate assembly.Main substrate assembly comprises first substrate with the first and second relative surfaces, runs through the perforate of the first substrate between the first and second surfaces, one or more circuit layers, and be electrically coupled to multiple first contact pads of one or more circuit layers.Sensor chip is arranged in perforate at least in part, and comprise second substrate with the first and second relative surfaces, be formed on the second substrate or among multiple photodetectors, be formed on multiple second contact pads that are electrically coupled to photodetector at the second surface place of the second substrate, be formed in the first surface of the second substrate and expose one or more grooves of the second contact pad, and there is the 3rd substrate of the first surface that is mounted to the second substrate first surface, wherein the 3rd substrate comprises the cavity on photodetector that is positioned in the first surface that is formed into the 3rd substrate.The 4th substrate comprises the first and second relative surfaces, and wherein the first surface of the 4th substrate is mounted to the second surface of the second substrate, and wherein the 4th substrate comprises the one or more grooves in the first surface that is formed into the 4th substrate.Each from the second contact pad one of multiple conductive trace extend and extend in one or more grooves of the 4th substrate.Each of electric connector is electrically connected with in multiple conductive traces one one in the first contact pad.Lens module is mounted to main substrate assembly, and wherein lens module comprises and arranging for focused light through the 3rd substrate and focus on the one or more lens on photodetector.
By looking back specification, claims and accompanying drawing, it is clear that the other objects and features of the invention will become.
Brief description of the drawings
Figure 1A to Fig. 1 L shows the cross-sectional side view that forms the step in image sensor module in order.
Fig. 2 A to Fig. 2 H is the cross-sectional side view that shows in order the step in the alternate embodiment that forms image sensor module.
Fig. 3 A to Fig. 3 C is the cross-sectional side view that shows in order the step in the second alternate embodiment that forms image sensor module.
Fig. 4 shows the cross-sectional side view of the 3rd alternate embodiment of image sensor module.
Embodiment
The present invention is low profile, chip-scale sensor assembly (for example, for camera), it combines the imageing sensor of wafer-class encapsulation, the main substrate with imaging window and optics/camera lens module, and these parts are by extremely main substrate of direct-assembling.
Figure 1A to Fig. 1 M illustrates the formation of the imageing sensor of encapsulation.This formation has started from comprising the wafer 10 (silicon substrate) of multiple imageing sensors 12 formed thereon, as illustrated in Figure 1A.Each imageing sensor 12 comprises multiple photodetectors 14, supports circuit 16 and contact pad 18.Photodetector 14 is configured to survey and measure incident light.Contact pad 18 is electrically connected to photodetector 14 and/or their support circuit 16 for providing from sheet signaling.Each photodetector 14 is voltage signal by transform light energy.Can comprise that extra circuit is to amplify voltage, and/or be converted into numerical data.Color filter and/or lenticule 20 can be installed on photodetector 14.Preferably, be formed on the top surface of substrate 10 such as the passivation layer 22 of silicon dioxide (silica) or silicon nitride.Passivation layer 22 is formed and makes it is at least transparent for transducer by the light wavelength that is used to survey.The transducer of the type is well known in the art, and does not further describe at this.
By the effective coverage (comprising those regions of photodetector 14 and filter/lens 20) that is mounted to the protectiveness of upper surface of substrate 10 and optically transparent substrate 24 and seals each transducer 12.Multiple cavitys 26 be formed in the basal surface of substrate 24 and aim at the effective coverage of each transducer 12.Each cavity 26 is enough large with the whole effective coverage of in covering sensor 12, but the contact pad 18 of covering sensor not.By epoxy resin, polymer, resin or any other one or more suitable joint adhesive and method, protectiveness substrate 24 is bonded in effective side of substrate 10.The synthetic that optically transparent substrate 24 can be polymer, glass, glass and polymer or any other one or more optically transparent materials.Preferably, substrate is glass.The preferred non-limiting example of substrate 24 can have the thickness of 50 to 1000 μ m, and the preferred heights of void space can be 5 to 500 μ m.Can carry out thinning silicon substrate 10 by the combination of mechanical lapping, chemico-mechanical polishing (CMP), wet etching, atmosphere downstream plasma (ADP), dry chemical etch (DCE) and/or aforementioned technique or any other one or more suitable silicon thinning methods.50 to 300 μ m by the preferred thickness of the silicon substrate 10 of thinning.The structure obtaining is illustrated in Figure 1B.
Can remove with the combination of laser cutting device, mechanical sawing, aforementioned technique and/or any other suitable one or more glass cutting methods the part of the protectiveness substrate 24 between the effective coverage of transducer 12.Laser cutting is preferred method.This technique has separated the part (its final coverlet is cut into independent tube core) that forms the substrate 24 of cavity 26, has therefore realized protectiveness cavity list and has cut.The structure obtaining is illustrated in Fig. 1 C.Preferably, each protectiveness substrate 24 has formed with the sealing of substrate 10 to protect the part (, having sealed cavity 26) of the substrate 10 on photodetector 14 and lenticule/filter 20.
On structure, deposit one deck photoresist 28.Photoresist deposition process can be spraying or any other one or more suitable deposition processs.Expose and etching photoresist 28 by suitable photoetching process well known in the art, wherein in the region of the substrate 10 between transducer 12, remove photoresist, therefore exposed passivation layer.Remove the passivation layer 22 (for example passing through plasma etching) being exposed, therefore exposed substrate 10.If passivation is silicon dioxide or silicon nitride, etchant can be CF4, SF6 or any other suitable etchant.Carrying out subsequently silicon is etched with groove 30 is formed into being exposed in part of substrate 10.Silicon etching can be the anisotropic dry etching that uses CF4, SF6 or any other suitable etchant.In the scope of the preferred depth of groove 30 in 25 to 150 μ m, depend on the final thickness of substrate 10.The structure obtaining is illustrated in Fig. 1 D.
Use acetone or any other one or more chemistry well known in the art or plasma (for example O2 plasma) photoresist stripping means to peel off photoresist 28.Passivation layer 32 (for example silicon dioxide) is deposited on structure, preferably has the thickness that is equal to or greater than 0.5 μ m.Can carry out silica deposit by physical vapour deposition (PVD) (PVD) or any other one or more suitable deposition processs.On structure, deposit one deck photoresist 34 (for example, by spraying or any other one or more suitable deposition processs).Expose and etching photoresist 34 by suitable photoetching process well known in the art, removed photoresist 34 from the part on protectiveness substrate 24 and contact pad 18 thus, in those regions, exposed the part of passivation layer 32.Carry out the part (on protectiveness substrate 24 and on contact pad 18) that is exposed that etching removes passivation layer 32.The result obtaining is illustrated in Fig. 1 E.
Peel off photoresist 34 (for example using oxygen plasma technique or acetone chemical peeling or any other photoresist stripping means well known in the art).Structurally depositing conducting layer 36.Conductive layer 36 can be copper, aluminium, conducting polymer or any other one or more suitable electric conducting materials, and can deposit by physical vapour deposition (PVD) PVD, chemical vapour deposition (CVD), plating or any other one or more suitable deposition processs.Preferably, conductive layer 36 is aluminium and deposits by PVD.On structure, deposit one deck photoresist 38, and it is exposed and be etched with the photoresist 38 that removes on protectiveness substrate 24 and the core at groove 30 bottom places by suitable photoetching process well known in the art.The structure obtaining is illustrated in Fig. 1 F.
Carry out the part that is exposed that wet method or dry etching remove conductive layer 36, left the multiple discrete traces that form the conductive layer 36 of lead-in wire, each extension of the sidewall along groove 30 from contact pad 18 that goes between, and extend the bottom that arrives groove 30.Etchant for wet etching can be phosphoric acid (H3PO4), acetic acid, nitric acid (HNO3) or any other one or more suitable etchants.Etchant for dry etching can be Cl2, CCl4, SiCl4, BCl3 or any other one or more suitable etchants.Wet etching is the method for optimizing forming for going between.Remove subsequently photoresist 38, obtain the structure shown in Fig. 1 G.Can for example, to the optional plating technic of 36 execution (Ni/Pd/Au) that goes between.It should be noted, alternatively, photoresist 38 can be left on the sidewall of protectiveness substrate 24 alternatively, and conductive layer 36 can be retained on the sidewall of protectiveness substrate 24 there, and it also can serve as light shield layer in the case.
On structure, deposit optional sealant layer 40.Sealant layer 40 can be combination or any other one or more suitable dielectric materials of polyimides, pottery, polymer, polymer synthetic, Parylene, silicon dioxide, epoxy resin, silicones, porcelain, nitride, glass, ionic crystals, resin, previous materials.Sealant layer 40 is preferably 0.5 to 20 μ m on thickness, and preferred material is liquid photoetching polymer, allly can pass through in this way spray deposited solder mask.Imageable light (photoimagable) sealant layer 40 is developed and optionally remove from the contact portion 36a of protectiveness substrate 24 and lead-in wire 36.If necessary, encapsulant 40 can be retained on the sidewall of protectiveness substrate 24 alternatively to serve as light shield layer.The structure obtaining is illustrated in Fig. 1 H.
Can on contact portion 36a, form interconnection 42.Alternatively, interconnection 42 can be formed on main substrate or by other members that contact with contact portion 36a.Interconnection 42 can be BGA, column cap projection, plating projection, adhesive projection, polymer projection, copper post, microtrabeculae or any other one or more suitable interconnecting methods.Preferably, utilize the adhesive projection being formed by one or more electric conducting materials and one or more cohesive materials to form interconnection 42.One or more electric conducting materials can be combination or any other one or more suitable electric conducting materials of silver, copper, aluminium, gold, graphite, previous materials.One or more adhesive materials can be combination or any other one or more suitable adhesive materials of varnish, resin, previous materials.Preferably, carry out depositing electrically conductive adhesive on contact portion 36a by pneumatic distribution rifle or any other one or more suitable distribution methods, and by heating, UV or any other one or more suitable curings, it is cured subsequently, forms thus projection 42.When mounted, the extra play of electroconductive binder can be assigned on projection 42 or be dispensed in the contact pad of main substrate.The structure obtaining is illustrated in Fig. 1 I.
Along the line that spreads all over groove, substrate 10 is singly cut into multiple tube cores subsequently, obtains the structure of Fig. 1 J.Can utilize mechanical bit chopper and slicer, laser cutting or any other suitable technique to complete wafer scale section/mono-the cutting of parts.The encapsulated sensor tube core of singly cutting can be mounted to main substrate 44 via interconnection 42 subsequently, and this main substrate 44 has contact pad 46, circuit layer 48 and perforate 50, and sensor die is given prominence to through this perforate 50, as shown in Fig. 1 K.Main substrate 44 can be the substrate of organic flexible PCB, silicon (rigidity), glass, pottery or any other type applicatory.The thickness of main substrate 44 preferably enough little the so that upper surface of winner's substrate 44 below the upper surface of substrate 10.Can be deposited on the conductive adhesive layer in the contact pad 46 of main substrate by using by silk screen printing, and promote to install by curing process subsequently.
Lens module 52 can be installed on transducer 12, as illustrated in Fig. 1 L.Exemplary lens module 52 can comprise the shell 54 that is engaged to main substrate 44, and its housing has supported one or more lens on transducer 12.Groove 30 can be groove annular, open sides, and its basal surface is continuous annular shoulder thus, and perforate 50 can be imitateed the shape of groove 30 in the case.Alternatively, can have multiple grooves 30 discrete, open sides, each trench bottom surfaces has formed discrete shoulder thus, and perforate 50 will have the shape that adapts to this arrangements of grooves in the case.
Fig. 2 A to Fig. 2 H illustrates the formation of the alternate embodiment of package image transducer.This formation starts from same structure as illustrated in Figure 1A, except contact pad 18 be positioned at the apparent surface of light substrate incident thereon 10 upper.This configuration can comprise the sensor component (BSI) of backside illumination, and wherein photodetector 14 is formed adjacently with the apparent surface of substrate, enters the light of substrate 10 because contact pad 18 or photodetector are configured to survey via this surface.Substrate 10 is mounted to support substrates 60 with suitable adhesive 62, as illustrated in Fig. 2 A.By protectiveness substrate 24 and by carrying out seal sensor about Figure 1B and Fig. 1 C in the support substrates 60 of identical technology institute thinning described above, to obtain the structure shown in Fig. 2 B.
As about Fig. 1 D described above process substrate so that groove 64 is formed in substrate 10, except groove 64 runs through substrate 10 with exposed adhesive 62 and has partly exposed contact pad 18 always, as illustrated in Fig. 2 C.Subsequently for example by remove the adhesive 62 being exposed with plasma etching process.Remove subsequently photoresist 28.On structure, applying photoresist 66, is photoetching etching afterwards, to remove the photoresist 66 (and exposing substrate 60) on the substrate 60 at groove 64 bottom places.Carry out subsequently the part that is exposed that silicon etching carrys out etch substrate 60, so that groove 64 is extended in substrate 60, as illustrated in Fig. 2 D.
Remove photoresist 66, and as about Fig. 1 E described above in groove 64, form passivation layer 32, as shown in Fig. 2 E.Remove photoresist 34, and as about Fig. 1 F and Fig. 1 G formation conductive trace/lead-in wire 36 described above, it extends downwardly into groove 64 from contact pad 18, as shown in Fig. 2 F.For this embodiment, trace/lead-in wire extends along the lower wall of the groove 64 being limited by substrate 60, and does not extend along the upper side wall of the groove 64 being limited by substrate 10.
As about Fig. 1 H and Fig. 1 I formation sealant described above 40 and interconnection 42, as shown in Fig. 2 G.Singly cut subsequently substrate 10, be mounted to main substrate 44, and as about described above itself and lens module 52 are assembled of Fig. 1 J to Fig. 1 L, as shown in Fig. 2 H.
Fig. 3 A to Fig. 3 C illustrates the formation of the second alternate embodiment of package image transducer.This formation starts from the structure (before singly cutting) of Fig. 2 G.Mutually adhere to back-to-back two this structures, as illustrated in Fig. 3 A, preferably use adhesive.Subsequently back-to-back substrate 60 is singly cut into modules 70, each has upper sensor 12a and the lower sensor 12b of back-to-back orientation, as shown in Figure 3 B.Upper sensor 12a is mounted to main substrate 44, and as about described above itself and lens module 52 are assembled of Fig. 1 J to Fig. 1 L, as shown in Fig. 3 C.Lower sensor 12b is electrically connected to the contact pad 46 of main substrate by wire-bonded 72.Wire-bonded 72 can be connected to interconnection 42 or be connected directly to the contact pad 18 of lower sensor 12b.
As can be applied to similarly the embodiment of Figure 1A to Fig. 1 L about the similar technique of Fig. 3 A to Fig. 3 C back-to-back transducer of formation described above, as illustrated in Fig. 4.
It being understood that and the invention is not restricted to one or more embodiment described above and that this paper is illustrated, but contain any and all distortion in the scope that falls into claims.For example, reference of the present invention is not intended to limit the scope of any claim or claim term herein, but alternatively only with reference to one or more features that can be covered by one or more claims.Material, technique and multiple example are only schematically as described above, and should not be considered restriction claim.In addition as accessory rights requires and specification it is evident that, be not that all method steps all need to be carried out according to illustrated or claimed accurate order, but according to allowing any order that correctly forms imageing sensor to carry out.Finally, the individual layer of material can be formed the multilayer of this or similar material, and vice versa.
It should be noted, as used herein, term " ... on " and " ... on " all comprise with comprising " and directly exist ... on " (not arranging intermediate materials, element or interval between the two) and " be connected on ... on " (having arranged intermediate materials, element or interval between the two).Similarly, term " with ... adjacent " comprise " with ... direct neighbor " (do not arrange intermediate materials between the two, element or interval) and " with ... indirect neighbor " (arrange intermediate materials between the two, element or interval), " being mounted to ... " comprises " being directly mounted to ... " (does not arrange intermediate materials between the two, element or interval) and " being indirectly mounted to ... " (arranged intermediate materials between the two, element or interval), and " electric coupling " comprises " being directly electrically coupled to ... " (not having intermediate materials or element that element is electrically connected between the two) and " Indirect Electro is coupled to ... " (having intermediate materials or element that element is electrically connected between the two).For example, " on substrate " forming element can comprise directly forming element on substrate, wherein there is no intermediate materials/element between the two, and is connected on forming element on substrate, wherein has one or more intermediate materials/elements between the two.
Claims (14)
1. an image sensor package, comprising:
Main substrate assembly, it comprises:
The first substrate, it has the first and second relative surfaces,
Perforate, it runs through described the first substrate between described the first and second surfaces,
One or more circuit layers,
Multiple the first contact pads, it is electrically coupled to described one or more circuit layer;
Sensor chip, it is mounted to described main substrate assembly and is arranged at least in part in described perforate, and wherein said sensor chip comprises:
The second substrate, it has the first and second relative surfaces,
Multiple photodetectors, its be formed on described the second substrate or among,
Multiple the second contact pads, the first surface place that it is formed on described the second substrate, is electrically coupled to described photodetector;
One or more grooves, it is formed in the first surface of described the second substrate,
Multiple conductive traces, each from described the second contact pad one is extended and extends in described one or more groove, and
The 3rd substrate, it has the first surface that is mounted to described the second substrate first surface, and wherein said the 3rd substrate comprises the cavity on described photodetector that is positioned in the first surface that is formed into described the 3rd substrate;
Electric connector, each is electrically connected with in described multiple conductive traces one one in described the first contact pad; And
Lens module, it is mounted to described main substrate assembly, and wherein said lens module comprises to be arranged for focused light through described the 3rd substrate and focus on the one or more lens on described photodetector.
2. image sensor package according to claim 1, wherein, described electric connector is conductive projection, its each by one in described the first contact pad one of being electrically connected in described multiple conductive trace.
3. image sensor package according to claim 1, wherein, described one or more grooves are grooves of single open sides, it comprises the basal surface that is shaped as annular shoulder.
4. image sensor package according to claim 1, wherein, described one or more grooves are grooves of multiple open sides, it comprises the basal surface that is shaped as discrete shoulder.
5. image sensor package according to claim 1, further comprises:
The second sensor chip, it comprises:
The 4th substrate, it has the first and second relative surfaces,
Multiple the second photodetectors, its be formed on described the 4th substrate or among,
Multiple the 3rd contact pads, the first surface place that it is formed on described the 4th substrate, is electrically coupled to described the second photodetector,
One or more grooves, it is formed in the first surface of described the 4th substrate,
The 5th substrate, it has the first surface that is mounted to described the 4th substrate first surface, and wherein said the 5th substrate comprises the cavity on described the second photodetector that is positioned in the first surface that is formed into described the 5th substrate, and
Multiple the second conductive traces, each from described the 3rd contact pad one is extended and extends in one or more grooves of described the 4th substrate;
Wherein, described the first substrate further comprises the 4th contact pad that is coupled to described one or more circuit layers;
The second electric connector, each is electrically connected with in described multiple the second conductive traces one one in described the 4th contact pad; And
The second lens module, it is mounted to described main substrate assembly, and wherein said the second lens module comprises to be arranged for focused light through described the 5th substrate and focus on the one or more lens on described the second photodetector;
Wherein, the second surface of described the 4th substrate is mounted to the second surface of described the second substrate.
6. image sensor package according to claim 5, wherein, described the second electric connector is wire-bonded.
7. image sensor package according to claim 5, wherein, the described second and the 4th each in substrate is Semiconductor substrate.
8. an image sensor package, comprising:
Main substrate assembly, it comprises:
The first substrate, it has the first and second relative surfaces,
Perforate, it runs through described the first substrate between described the first and second surfaces,
One or more circuit layers,
Multiple the first contact pads, it is electrically coupled to described one or more circuit layer;
Sensor chip, it is mounted to described main substrate assembly and is arranged at least in part in described perforate, and wherein said sensor chip comprises:
The second substrate, it has the first and second relative surfaces,
Multiple photodetectors, its be formed on described the second substrate or among,
Multiple the second contact pads, the second surface place that it is formed on described the second substrate, is electrically coupled to described photodetector,
One or more grooves, it is formed in the first surface of described the second substrate and exposes described the second contact pad, and
The 3rd substrate, it has the first surface that is mounted to described the second substrate first surface, and wherein said the 3rd substrate comprises the cavity on described photodetector that is positioned in the first surface that is formed into described the 3rd substrate;
The 4th substrate, it has the first and second relative surfaces, the first surface of wherein said the 4th substrate is mounted to the second surface of described the second substrate, and wherein said the 4th substrate comprises the one or more grooves in the first surface that is formed into described the 4th substrate;
Multiple conductive traces, each from described the second contact pad one is extended and extends in one or more grooves of described the 4th substrate;
Electric connector, each is electrically connected with in described multiple conductive traces one one in described the first contact pad; And
Lens module, it is mounted to described main substrate assembly, and wherein said lens module comprises to be arranged for focused light through described the 3rd substrate and focus on the one or more lens on described photodetector.
9. image sensor package according to claim 8, wherein, described electric connector is conductive projection, its each by one in described the first contact pad one of being electrically connected in described multiple conductive trace.
10. image sensor package according to claim 8, wherein, one or more grooves of described the 4th substrate are the grooves of single open sides, it comprises the basal surface that is shaped as annular shoulder.
11. image sensor package according to claim 8, wherein, one or more grooves of described the 4th substrate are the grooves of multiple open sides, it comprises the basal surface that is shaped as discrete shoulder.
12. image sensor package according to claim 8, further comprise:
The second sensor chip, it comprises:
The 5th substrate, it has the first and second relative surfaces,
Multiple the second photodetectors, its be formed on described the 5th substrate or among,
Multiple the 3rd contact pads, the second surface place that it is formed on described the 5th substrate, is electrically coupled to described the second photodetector,
One or more grooves, it is formed in the first surface of described the 5th substrate and exposes described the 3rd contact pad, and
The 6th substrate, it has the first surface that is mounted to described the 5th substrate first surface, and wherein said the 6th substrate comprises the cavity on described the second photodetector that is positioned in the first surface that is formed on described the 6th substrate;
The 7th substrate, it has the first and second relative surfaces, the first surface of wherein said the 7th substrate is mounted to the second surface of described the 5th substrate, and wherein said the 7th substrate comprises the one or more grooves in the first surface that is formed into described the 7th substrate;
Multiple the second conductive traces, each from described the 3rd contact pad one is extended and extends in one or more grooves of described the 7th substrate;
Wherein, described the first substrate further comprises the 4th contact pad that is coupled to described one or more circuit layers;
The second electric connector, each is electrically connected with in described multiple the second conductive traces one one in described the 4th contact pad; And
The second lens module, it is mounted to described main substrate assembly, and wherein said the second lens module comprises to be arranged for focused light through described the 6th substrate and focus on the one or more lens on described the second photodetector;
Wherein, the second surface of described the 4th substrate is mounted to the second surface of described the 7th substrate.
13. image sensor package according to claim 12, wherein, described the second electric connector is wire-bonded.
14. image sensor package according to claim 12, wherein, each in described second, the 4th, the 5th and the 7th substrate is Semiconductor substrate.
Applications Claiming Priority (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US201361778267P | 2013-03-12 | 2013-03-12 | |
| US61/778267 | 2013-03-12 | ||
| US14/200,146 US9190443B2 (en) | 2013-03-12 | 2014-03-07 | Low profile image sensor |
| US14/200146 | 2014-03-07 |
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| CN101221963A (en) * | 2007-01-08 | 2008-07-16 | 采钰科技股份有限公司 | Electronic assembly for image sensor device and fabrication method thereof |
| US20080191335A1 (en) * | 2007-02-08 | 2008-08-14 | Advanced Chip Engineering Technology Inc. | Cmos image sensor chip scale package with die receiving opening and method of the same |
| CN102820274A (en) * | 2011-06-09 | 2012-12-12 | 奥普蒂兹公司 | 3D Integrated Microelectronic Assembly With Stress Reducing Interconnects And Method Of Making Same |
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