CN104051421B - Semiconductor chip structure in conjunction with substrate through-hole and metal coupling and its manufacturing method thereof - Google Patents
Semiconductor chip structure in conjunction with substrate through-hole and metal coupling and its manufacturing method thereof Download PDFInfo
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- CN104051421B CN104051421B CN201310079415.8A CN201310079415A CN104051421B CN 104051421 B CN104051421 B CN 104051421B CN 201310079415 A CN201310079415 A CN 201310079415A CN 104051421 B CN104051421 B CN 104051421B
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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Abstract
The invention discloses the semiconductor chip structure of a kind of combination substrate through-hole and metal coupling and its manufacturing method thereof, wherein aforementioned structure are by including a substrate, at least one substrate through-hole, at least one metal layer on back, at least one the first metal layer, at least semiconductor electronic component and at least one metal coupling；Wherein this first metal layer and this semiconductor electronic component are formed at the front of this substrate；This metal coupling, is formed on this first metal layer；This substrate through-hole runs through this substrate；This metal layer on back is formed at the back side of this substrate, the back side covering this substrate through-hole and at least covering this substrate of part, and contacts in the top of this substrate through-hole with this first metal layer at least part of.With the structure of the present invention, it is favorably improved the link density of semiconductor element, significantly can reduce wafer size, and speed signaling rate, and power consumption can be reduced simultaneously, and be provided that heterogeneous integration again.
Description
Technical field
The present invention is about the semiconductor chip structure of a kind of combination substrate through-hole and metal coupling and its manufacturing method thereof；With
The structure of the present invention, can make the stacking of crystal covering type chip, be favorably improved the link density of semiconductor element, reduce chip chi
Transmission speed that is very little and speeding signal.
Background technology
In the middle of the processing procedure of semiconductor element, for reducing the area of semiconductor wafer, and then develop crystal covering type wafer stacking
Technology.This wafer stacking technology would generally use the copper post of metal coupling, comes between the upper lower wafer as flip stacking
Contact, and to turn on and to transmit signal by the copper post of metal coupling.1A figure is that the tool copper pillar bumps of a prior art are partly led
The cross-sectional view of body chip, wherein structure include a substrate 101, a metal level 103, a metal coupling 105 successively
And semiconductor electronic component 113；Wherein this semiconductor electronic component 113 is formed at the front of this substrate 101；And wherein should
Metal level 103 is formed at the front of this substrate 101, and contacts with this semiconductor electronic component 113；And this metal coupling 105 shape
Become on this metal level 103.1B figure is the crystal covering type wafer stacking of the tool copper pillar bumps semiconductor wafer of a prior art
Cross-sectional view, the embodiment shown in its primary structure and 1A figure is roughly the same, only, this metal coupling 105 it
On, stack a upper chip 135；And wherein this metal coupling 105 is connected with this upper chip 135, by this metal coupling
105, the signal of this semiconductor electronic component 113 on this substrate 101 can be made to be connected with this upper chip 135；Again in this base
Under plate 101, another setting one module group substrates 133, on this module group substrates 133, set a joint routing 137 again, connect by this
Close routing 137 to connect the signal of this semiconductor electronic component 113 to this module group substrates 133.
Though design so can reach the effect of 3D crystal covering type wafer stacking, however, the limit in the link density of circuit
System is still very big, thus still limited to reducing wafer size, and signaling rate cannot effectively be lifted again, also therefore overall brilliant
The power consumption of piece is still higher.
Content of the invention
In view of this, in order to solve above-mentioned technical problem, a kind of present invention combination substrate through-hole of proposition is partly led with projection
Body chip architecture and its manufacturing method thereof, not only can provide heterogeneous integration, also can improve the link density of semiconductor element, reduce
Wafer size, speeds the transmission speed of signal, reduces the power consumption of chip, and reduces material cost.
The semiconductor chip structure of combination substrate through-hole and metal coupling that the present invention provides, includes a substrate, at least
One substrate through-hole, at least one metal layer on back, at least one the first metal layer, at least semiconductor electronic component and at least one gold medal
Belong to projection；
Wherein this substrate through-hole runs through this substrate；
Wherein this metal layer on back is formed at the back side of this substrate, and this metal layer on back cover this substrate through-hole and
At least cover the back side of this substrate of part；
Wherein this first metal layer, is formed at the front of this substrate, and this first metal layer of wherein at least part is in this base
The top of plate through hole is contacted with this metal layer on back；
Wherein this semiconductor electronic component, is formed at the front of this substrate, and this first metal layer of part should be partly with part
Conducting electrons element contacts；And
Wherein this metal coupling, is formed on this first metal layer.
When implementing, also a protective layer can be more set, make this protective layer in the middle of above-mentioned structure, on this substrate
Cover this substrate at least part of, this semiconductor electronic component and this first metal layer of part, and this metal coupling and extremely
This first metal layer of small part is not covered by this protective layer.
When implementing, also between this metal coupling and this first metal layer, more can arrange in the middle of above-mentioned structure
At least one reroutes road floor so that this rewiring road floor is on this protective layer and this first metal layer, and this rewiring road floor
Under this metal coupling, and the structure of wherein this rewiring road floor includes at least one dielectric layer, at least one dielectric layer through hole
And at least one second metal layer；
Wherein this dielectric layer, is formed on this protective layer and this first metal layer, and this dielectric layer covers part and is somebody's turn to do
Substrate, this protective layer and this first metal layer of part；
Wherein this dielectric layer through hole, runs through this dielectric layer；And
Wherein this second metal layer, is formed on this dielectric layer so that this second metal layer covers this dielectric layer leads to
Hole and at least cover part this dielectric layer, and this second metal layer of wherein at least part in this dielectric layer through hole bottom with
Partly this first metal layer contacts, and this metal coupling, is formed on this second metal layer.
When implementing, the material of this substrate aforesaid is GaAs（GaAs）, carborundum（SiC）, gallium nitride（GaN）Or phosphorus
Change indium（InP）.
When implementing, more plate an added metal layer on this metal coupling aforesaid, wherein constitute this added metal layer
Material be indium, stannum, indium alloy, tin alloy or indium stannum alloy.
In implement when, this substrate thickness aforesaid be more than 10 μm be less than 300 μm between.
When implementing, the material of this metal layer on back aforesaid is gold, copper, palladium（Pd）, nickel（Ni）, silver（Ag）, the conjunction of nickel
Gold, gold copper, nickel billon, Ni-Pd alloy, the alloy of Polarium, metal material or metal material.
When implementing, the material of this first metal layer aforesaid is gold, copper, gold copper, metal material or metal material
Alloy.
When implementing, the material of this metal coupling aforesaid is copper, the alloy of copper alloy, metal material or metal material.
When implementing, the material of this protective layer aforesaid is silicon nitride（SiN）.
When implementing, the material of this dielectric layer aforesaid is dielectric material polybenzoxazoles（Polybenzoxazole,
PBO）.
When implementing, the material of this second metal layer aforesaid is gold, copper, gold copper, metal material or metal material
Alloy.
The present invention also provides the manufacturing method thereof of a kind of combination substrate through-hole and the semiconductor chip structure of metal coupling, including
Following steps：
In the front of a substrate, form at least semiconductor electronic component；
In the front of this substrate, form at least one the first metal layer；
Wherein this first metal layer of this part is contacted with this semiconductor electronic component of part；In this first metal layer it
On, form at least one metal coupling；
In this substrate front side, form a protection metal coupling layer；
Wherein this protection metal coupling layer cover this substrate front side, this semiconductor electronic component, this first metal layer with
And this metal coupling；
On this protection metal coupling layer, form a peel ply；
Wherein this peel ply covers this protection metal coupling layer；
On this peel ply, adhere to a upper upper substrate；
Grind and polish the back side of this substrate；
In the back side of this substrate, at least one substrate through-hole is produced with exposure imaging and etching technique；
Wherein this substrate through-hole runs through this substrate；
Plate at least one metal layer on back in the back side of this substrate；
The back side that wherein this metal layer on back covers this substrate through-hole and at least covers this substrate of part, and wherein
At least partly this first metal layer is contacted with this metal layer on back in the top of this substrate through-hole；
In the back side of this substrate, vac sorb lives an infrabasal plate；
After heated, this upper substrate is made to peel off this peel ply；
Remove this peel ply and this protection metal coupling layer；And release vac sorb, remove this infrabasal plate.
When implementing, also can be in the middle of above-mentioned structure, before this substrate front side forms this protection metal coupling layer, first
One protective layer is set on this substrate, make this protective layer cover this substrate at least part of, this semiconductor electronic component and
Partly this first metal layer, and this metal coupling and at least partly this first metal layer do not covered by this protective layer；Then at
This substrate front side forms this protection metal coupling layer, and makes this protection metal coupling layer cover this substrate front side, this first gold medal
Belong to layer, this protective layer and this metal coupling.
When implementing, also can be in the middle of above-mentioned structure, before forming this metal coupling on this first metal layer, first
At least one rewiring road floor is set on this protective layer and this first metal layer, and the structure of wherein this rewiring road floor includes
Have：At least one dielectric layer, at least one dielectric layer through hole and at least one second metal layer；
Wherein this dielectric layer, is formed on this protective layer and this first metal layer, and this dielectric layer covers part and is somebody's turn to do
Substrate, this protective layer and this first metal layer of part；
Wherein this dielectric layer through hole, runs through this dielectric layer；And
Wherein this second metal layer, is formed on this dielectric layer so that this second metal layer covers this dielectric layer leads to
Hole and at least cover part this dielectric layer, and this second metal layer of wherein at least part in this dielectric layer through hole bottom with
Partly this first metal layer contacts；
Form this metal coupling afterwards on this second metal layer；
And make this protection metal coupling floor cover this rewiring road floor, this second metal layer, this dielectric layer, this dielectric layer
Through hole and this metal coupling.
When implementing, the material of this substrate aforesaid is GaAs（GaAs）, carborundum（SiC）, gallium nitride（GaN）Or phosphorus
Change indium（InP）.
When implementing, more plate an added metal layer on this metal coupling aforesaid, wherein constitute this added metal layer
Material be indium, stannum, indium alloy, tin alloy or indium stannum alloy.
When implementing, between this substrate thickness aforesaid is less than 300 μm more than 10 μm.
When implementing, the material of this metal layer on back aforesaid is gold, copper, palladium（Pd）, nickel（Ni）, silver（Ag）, the conjunction of nickel
Gold, gold copper, nickel billon, Ni-Pd alloy, the alloy of Polarium, metal material or metal material.
When implementing, the material of this first metal layer aforesaid is gold, copper, gold copper, metal material or metal material
Alloy.
When implementing, the material of this metal coupling aforesaid is copper, the alloy of copper alloy, metal material or metal material.
When implementing, the material of this protective layer aforesaid is silicon nitride（SiN）.
When implementing, the material of this dielectric layer aforesaid is dielectric material polybenzoxazoles（Polybenzoxazole,
PBO）.
When implementing, the material of this second metal layer aforesaid is gold, copper, gold copper, metal material or metal material
Alloy.
When implementing, aforementioned upper substrate is sapphire substrate.
When implementing, aforementioned infrabasal plate is carbide substrate.
Combination substrate through-hole and the semiconductor chip structure of projection and its manufacturing method thereof that the present invention provides, are favorably improved
The link density of semiconductor element, significantly can reduce wafer size, and speed signaling rate, and can reduce power consumption simultaneously
Amount, and it is provided that heterogeneous integration again.
Brief description
Figure 1A is the cross-sectional view of the tool copper pillar bumps semiconductor wafer of a prior art.
Figure 1B is that the cross-section structure of the crystal covering type wafer stacking of tool copper pillar bumps semiconductor wafer of a prior art is illustrated
Figure.
Fig. 2A is the cross-sectional view with the semiconductor wafer of metal coupling for the combination substrate through-hole of the present invention.
Fig. 2 B is the another cross-sectional view with the semiconductor wafer of metal coupling for the combination substrate through-hole of the present invention.
Fig. 2 C-1 is that the combination substrate through-hole of the present invention is illustrated with another cross-section structure of the semiconductor wafer of metal coupling
Figure.
Fig. 2 C-2 is that the combination substrate through-hole of the present invention is shown with again another cross-section structure of the semiconductor wafer of metal coupling
It is intended to.
Fig. 2 D-1 is that the combination substrate through-hole of the present invention is illustrated with the another cross-section structure of the semiconductor wafer of metal coupling
Figure.
Fig. 2 D-2 is that the combination substrate through-hole of the present invention is shown with again another cross-section structure of the semiconductor wafer of metal coupling
It is intended to.
Fig. 2A -0 is fabrication steps 1 cross-section structure with the semiconductor wafer of metal coupling for the combination substrate through-hole of the present invention
Schematic diagram.
Fig. 2A -1 is fabrication steps 2,3,4 section with the semiconductor wafer of metal coupling for the combination substrate through-hole of the present invention
Structural representation.
Fig. 2A -2 is fabrication steps 5 cross-section structure with the semiconductor wafer of metal coupling for the combination substrate through-hole of the present invention
Schematic diagram.
Fig. 2A -3 is fabrication steps 6 cross-section structure with the semiconductor wafer of metal coupling for the combination substrate through-hole of the present invention
Schematic diagram.
Fig. 2A -4 is fabrication steps 7 cross-section structure with the semiconductor wafer of metal coupling for the combination substrate through-hole of the present invention
Schematic diagram.
Fig. 2A -5 is fabrication steps 8 cross-section structure with the semiconductor wafer of metal coupling for the combination substrate through-hole of the present invention
Schematic diagram.
Fig. 2A -6 is fabrication steps 9 cross-section structure with the semiconductor wafer of metal coupling for the combination substrate through-hole of the present invention
Schematic diagram.
Fig. 2A -7 is the fabrication steps 10 section knot with the semiconductor wafer of metal coupling for the combination substrate through-hole of the present invention
Structure schematic diagram.
Fig. 2 B-0 is fabrication steps A of semiconductor wafer of combination substrate through-hole and the metal coupling of the present invention and step 2,
3rd, 4 cross-sectional view.
Fig. 2 C-1-0 is the combination substrate through-hole of the present invention and fabrication steps B of semiconductor wafer of metal coupling and step
2nd, 3,4 cross-sectional view.
Fig. 2 C-2-0 is the combination substrate through-hole of the present invention and fabrication steps C, D of semiconductor wafer of metal coupling and step
Rapid 2,3,4 cross-sectional view.
Fig. 2 D-1-0 is fabrication steps E, F of semiconductor wafer with metal coupling for the combination substrate through-hole of the present invention, G, H
And step 2,3,4 cross-sectional view.
Fig. 2 D-2-0 is fabrication steps E, F of semiconductor wafer of combination substrate through-hole and the metal coupling of the present invention, G,
H, I and step 2,3,4 cross-sectional view.
Fig. 2 E is the combination substrate through-hole of the present invention and cuing open of the crystal covering type wafer stacking of the semiconductor wafer of metal coupling
Face structural representation.
Fig. 2 F is the another crystal covering type wafer stacking with the semiconductor wafer of metal coupling for the combination substrate through-hole of the present invention
Cross-sectional view.
Fig. 3 shows combination substrate through-hole and the semiconductor chip structure of metal coupling and its stream of manufacturing method thereof of the present invention
Cheng Tu.
Brief description:
101st, substrate；103rd, metal level；
105th, metal coupling；111st, added metal layer；
113rd, semiconductor electronic component；133rd, module group substrates；
135th, upper chip；137th, engage routing；
201st, substrate；203rd, the first metal layer；
205th, metal coupling；207th, metal layer on back；
209th, substrate through-hole；211st, added metal layer；
213rd, semiconductor electronic component；215th, protective layer；
217th, reroute road floor；219th, dielectric layer；
221st, dielectric layer through hole；223rd, second metal layer；
225th, protect metal coupling layer；227th, peel ply；
229th, upper substrate；231st, infrabasal plate；
233rd, module group substrates；235th, upper chip；
237th, engage routing.
Specific embodiment
The invention will be further described with specific embodiment below in conjunction with the accompanying drawings, so that those skilled in the art is permissible
It is better understood from the present invention and can be practiced, but illustrated embodiment is not as a limitation of the invention.
Fig. 2A is the cross-sectional view with the semiconductor wafer of projection for the combination substrate through-hole of the present invention, including
One substrate 201, wherein this substrate 201 typically use GaAs（GaAs）, carborundum（SiC）, gallium nitride（GaN）Or indium phosphide
（InP）Constituted Deng semi-conducting material, and this substrate 201 thickness be more than 10 μm be less than 300 μm between；In this substrate 201
Front is provided with least semiconductor electronic component 213, wherein this semiconductor electronic component 213 be field effect electric crystal (FET),
Heteroj unction bipolar electric crystal (HBT), resistance, the combination of the various semiconductor electronic component such as inductively or capacitively；Again in this base
The front of plate 201 is provided with least one the first metal layer 203, and the wherein material of this first metal layer 203 is gold, copper, Jin Tonghe
The alloy of gold, metal material or metal material, the thickness of this first metal layer 203 is more than or equal to 3 μm, and this first metal layer
203 are contacted with this semiconductor electronic component 213 of part；Again on this first metal layer 203, it is provided with least one metal convex
Block 205, the wherein material of this metal coupling 205 are copper, the alloy of copper alloy, metal material or metal material；In this substrate 201
The back side at least one substrate through-hole 209 is etched with etching technique, and this substrate through-hole 209 runs through this substrate 201；Then at this base
The back side of plate 201 plates at least one metal layer on back 207, makes this metal layer on back 207 cover this substrate through-hole 209 and extremely
Cover the back side of this substrate 201 of part less, the wherein material of this metal layer on back 207 is gold, copper, palladium（Pd）, nickel（Ni）, silver
（Ag）, the alloy of nickel, gold copper, nickel billon, Ni-Pd alloy, the alloy of Polarium, metal material or metal material.
Refer to Fig. 2 B, be the cross-sectional view of another embodiment of the present invention, shown in its primary structure and Fig. 2A
Embodiment roughly the same, only, on this metal coupling 205, more plate an added metal layer 211, wherein constitute this welding
The material of metal level 211 is indium, stannum, indium alloy, tin alloy or indium stannum alloy.
Refer to Fig. 2 C-1, be the cross-sectional view of another embodiment of the present invention, its primary structure and Fig. 2A institute
The embodiment shown is roughly the same, only, on this substrate 201, more arranges a protective layer 215, make this protective layer 215 cover to
This substrate 201 of small part, this semiconductor electronic component 213 and part this first metal layer 203, and this metal coupling 205 with
And at least partly this first metal layer 203 is not covered by this protective layer 215, and the material of wherein this protective layer 215 is nitridation
Silicon（SiN）.
Refer to Fig. 2 C-2, be the cross-sectional view of another embodiment of the present invention, its primary structure and Fig. 2 C-1
Shown embodiment is roughly the same, only, on this metal coupling 205, more plates an added metal layer 211, and wherein constituting should
The material of added metal layer 211 is indium, stannum, indium alloy, tin alloy or indium stannum alloy.
Refer to Fig. 2 D-1, be the cross-sectional view of another embodiment of the present invention, its primary structure and Fig. 2 C-1
Shown embodiment is roughly the same, only, between this metal coupling 205 and this first metal layer 203, more arranges at least one
Reroute road floor 217 so that this rewiring road floor 217 is on this protective layer 215 and this first metal layer 203, and this heavy cloth
Line layer 217 is under this metal coupling 205, and the structure of wherein this rewiring road floor 217 includes：At least one dielectric layer
219th, at least one dielectric layer through hole 221 and at least one second metal layer 223, wherein this dielectric layer 219, are formed at this protective layer
215 and this first metal layer 203 on, and this dielectric layer 219 covers this substrate 201 of part, this protective layer 215 and part
This first metal layer 203, the material wherein constituting this dielectric layer 219 is dielectric material polybenzoxazoles
（Polybenzoxazole, PBO）, and the thickness of this dielectric layer 219 is between 5 μm and 30 μm；Wherein this dielectric layer leads to
Hole 221, runs through this dielectric layer 219；And wherein second metal layer 223, it is formed on this dielectric layer 219 so that this second gold medal
Belong to layer 223 to cover this dielectric layer through hole 221 and at least cover this dielectric layer 219 of part, and wherein at least part this
Two metal levels 223 in this dielectric layer through hole 221 bottom with part this first metal layer 203 contact, wherein constitute this second
The material of metal level 223 is the alloy of gold, copper, gold copper, metal material or metal material；This metal coupling 205 again, forms
On this second metal layer 223；By the design of this rewiring road floor 217, can select to be arranged on this metal coupling 205
Suitable position, and electronic signal can be via this metal layer on back 207, this first metal layer 203 and this semiconductor electronic component
213 are connected, and are transferred to this metal coupling 205 by this first metal layer 203 with this second metal layer 223 again.
Refer to Fig. 2 D-2, be the cross-sectional view of another embodiment of the present invention, its primary structure and Fig. 2 D-1
Shown embodiment is roughly the same, only, on this metal coupling 205, more plates an added metal layer 211, and wherein constituting should
The material of added metal layer 211 is indium, stannum, indium alloy, tin alloy or indium stannum alloy.
Fig. 3 shows combination substrate through-hole and the semiconductor chip structure of projection and its flow process of manufacturing method thereof of the present invention
Figure.As illustrated, taking make the semiconductor chip structure that the combination substrate through-hole as shown in aforementioned Fig. 2A is with projection as a example, its system
Cheng Fangfa comprises the following steps：
Step 1. refers to Fig. 2A -0, in the front of a substrate 201, forms at least semiconductor electronic component 213；In
The front of this substrate 201, forms at least one the first metal layer 203, and this first metal layer 203 of part and this semi-conductor electricity of part
Subcomponent 213 contacts；On this first metal layer 203, form at least one metal coupling 205；Wherein this substrate 201 is usual
It is to use GaAs（GaAs）, carborundum（SiC）, gallium nitride（GaN）Or indium phosphide（InP）Constituted Deng semi-conducting material, and
This substrate 201 thickness be more than 10 μm be less than 300 μm between；Wherein this semiconductor electronic component 213 is field effect electric crystal
(FET), the combination of heteroj unction bipolar electric crystal (HBT), resistance, the various semiconductor electronic component such as inductively or capacitively；
The material of wherein this first metal layer 203 is the alloy of gold, copper, gold copper, metal material or metal material, this first metal
The thickness of layer 203 is more than or equal to 3 μm；The material of wherein this metal coupling 205 is copper, copper alloy, metal material or metal material
The alloy of material；
Step 2. refers to Fig. 2A -1, in this substrate 201 front, forms a protection metal coupling layer 225, makes this protection
Metal coupling layer 225 covers the front of this substrate 201, this semiconductor electronic component 213, this first metal layer 203 and should
Metal coupling 205；
Step 3. refers to Fig. 2A -1, on this protection metal coupling layer 225, forms a peel ply 227, makes this stripping
Absciss layer 227 covers this protection metal coupling layer 225；
Step 4. refers to Fig. 2A -1, on this peel ply 227, adheres to a upper upper substrate 229, wherein this upper substrate
229 is sapphire substrate；
Step 5. refers to Fig. 2A -2, grinds and polish the back side of this substrate 201；
Step 6. refers to Fig. 2A -3, in the back side of this substrate 201, is produced at least with exposure imaging and etching technique
One substrate through-hole 209, makes this substrate through-hole 209 run through this substrate 201；
Step 7. refers to Fig. 2A -4, plates at least one metal layer on back 207 in the back side of this substrate 201, makes this back side
The back side that metal level 207 covers this substrate through-hole 209 and at least covers this substrate 201 of part, and wherein at least part
This first metal layer 203 is contacted with this metal layer on back 207 in the top of this substrate through-hole 209；Wherein this metal layer on back
207 material is gold, copper, palladium（Pd）, nickel（Ni）, silver（Ag）, the alloy of nickel, gold copper, nickel billon, Ni-Pd alloy, palladium
The alloy of billon, metal material or metal material；
Step 8. refers to Fig. 2A -5, and in the back side of this substrate 201, vac sorb lives an infrabasal plate 231, wherein under this
Substrate 231 is carbide substrate；
Step 9. refers to Fig. 2A -5 and Fig. 2A -6, heated after, make this upper substrate 229 peel off this peel ply 227；
Remove this peel ply 227 and this protection metal coupling layer 225；And
Step 10. refers to Fig. 2A -6 and Fig. 2A -7, discharges vac sorb, removes this infrabasal plate 231.
It is intended to make the semiconductor chip structure of the combination substrate through-hole as shown in earlier figures 2B and projection, as aforementioned Fig. 3 institute
Outside 10 steps shown, need need to increase following steps after step 1, before step 2：
Step A. refers to 2B-0 figure, more plates an added metal layer 211, wherein structure on this metal coupling 205
The material becoming this added metal layer 211 is indium, stannum, indium alloy, tin alloy or indium stannum alloy.
It is intended to make the semiconductor chip structure of the combination substrate through-hole as shown in earlier figures 2C-1 and projection, such as aforementioned Fig. 3
Outside 10 shown steps, need need to increase following steps after step 1, before step 2：
Step B. refers to Fig. 2 C-1-0, on this substrate 201, more arranges a protective layer 215, makes this protective layer 215
Cover this substrate 201 at least part of, this semiconductor electronic component 213 and this first metal layer 203 of part, and this metal is convex
Block 205 and at least partly this first metal layer 203 are not covered by this protective layer 215；The material of wherein this protective layer 215 is
Silicon nitride（SiN）；
And wherein this protection metal coupling layer 225 of step 2. cover this substrate 201 front, this first metal layer 203,
This protective layer 215 and this metal coupling 205.
It is intended to make the semiconductor chip structure of the combination substrate through-hole as shown in earlier figures 2C-2 and projection, such as aforementioned Fig. 3
Outside 10 shown steps, need need to increase following steps after step 1, before step 2：
Step C. refers to Fig. 2 C-2-0, on this substrate 201, more arranges a protective layer 215, makes this protective layer 215
Cover this substrate 201 at least part of, this semiconductor electronic component 213 and this first metal layer 203 of part, and this metal is convex
Block 205 and at least partly this first metal layer 203 are not covered by this protective layer 215；The material of wherein this protective layer 215 is
Silicon nitride（SiN）；
Step D. refers to Fig. 2 C-2-0, more plates an added metal layer 211, wherein structure on this metal coupling 205
The material becoming this added metal layer 211 is indium, stannum, indium alloy, tin alloy or indium stannum alloy.
And wherein this protection metal coupling layer 225 of step 2. cover this substrate 201 front, this first metal layer 203,
This protective layer 215 and this metal coupling 205.
It is intended to make the semiconductor chip structure of the combination substrate through-hole as shown in earlier figures 2D-1 and projection, such as aforementioned Fig. 3
Outside 10 shown steps, step 1 need be revised as following steps：
Step E. refers to Fig. 2 D-1-0, in the front of a substrate 201, forms at least semiconductor electronic component 213；
In the front of this substrate 201, form at least one the first metal layer 203, and this first metal layer 203 of part and this quasiconductor of part
Electronic component 213 contacts；
Step F. refers to Fig. 2 D-1-0, on this substrate 201, more arranges a protective layer 215, makes this protective layer 215
Cover this substrate 201 at least part of, this semiconductor electronic component 213 and this first metal layer 203 of part, and this metal is convex
Block 205 and at least partly this first metal layer 203 are not covered by this protective layer 215；The material of wherein this protective layer 215 is
Silicon nitride（SiN）；
Step G. refers to Fig. 2 D-1-0, on this protective layer 215 and this first metal layer 203, more arranges at least
One reroutes road floor 217, and the structure of wherein this rewiring road floor 217 includes：
At least one dielectric layer 219, is formed on this protective layer 215 and this first metal layer 203, and this dielectric layer 219
Cover this substrate 201 of part, this protective layer 215 and this first metal layer 203 of part；Wherein constitute this dielectric layer 219
Material is dielectric material polybenzoxazoles（Polybenzoxazole, PBO）, and the thickness of this dielectric layer 219 be between 5 μm with
Between 30 μm；
At least one dielectric layer through hole 221, runs through this dielectric layer 219；And
At least one second metal layer 223, is formed on this dielectric layer 219 so that this second metal layer 223 covers this
Dielectric layer through hole 221 and at least cover this dielectric layer 219 of part, and this second metal layer 223 of wherein at least part is in this
The bottom of dielectric layer through hole 221 is contacted with this first metal layer 203 of part；Wherein constitute the material of this second metal layer 223
Alloy for gold, copper, gold copper, metal material or metal material；
Step H. refers to Fig. 2 D-1-0, on this second metal layer 223, forms at least one metal coupling 205；
And wherein this protection metal coupling floor 225 of step 2. covers this rewiring road floor 217, this second metal layer
223rd, this dielectric layer 219, this dielectric layer through hole 221 and this metal coupling 205.
It is intended to make the semiconductor chip structure of the combination substrate through-hole as shown in earlier figures 2D-2 and projection, its step is for example front
State the structure making Fig. 2 D-1, changing the step 1 in 10 steps shown in Fig. 3 except need becomes step E, step F, step G, step
Outside rapid H, following steps need be increased after step H, before step 2：
Step I. refers to Fig. 2 D-2-0, more plates an added metal layer 211, wherein structure on this metal coupling 205
The material becoming this added metal layer 211 is indium, stannum, indium alloy, tin alloy or indium stannum alloy.
Fig. 2 E is the section knot with the crystal covering type wafer stacking of semiconductor wafer of projection for the combination substrate through-hole of the present invention
Structure schematic diagram, its primary structure is roughly the same with Fig. 2 C-1 and shown embodiment, only, welds on this metal coupling 205
Connect a upper chip 235, and wherein this metal coupling 205 is connected with this upper chip 235, and wherein this upper chip 235
Include other semiconductor electronic component；Electronic signal via this metal layer on back 207, this first metal layer 203 and can be somebody's turn to do
Semiconductor electronic component 213 is connected, and is transferred to this metal coupling 205 by this first metal layer 203 again, then through this
Electronic signal is transferred to the semiconductor electronic component that this upper chip 235 is comprised by metal coupling 205；Again in this back metal
Under layer 207, module group substrates 233 are set, on this module group substrates 233, set at least one joint routing 237, by this again
Engage routing 237 signal of this semiconductor electronic component 213 can be connected to this module group substrates 233.
Fig. 2 F is the section knot with the crystal covering type wafer stacking of semiconductor wafer of projection for the combination substrate through-hole of the present invention
Structure schematic diagram, its primary structure is roughly the same with Fig. 2 D-1 and shown embodiment, only, welds on this metal coupling 205
Connect a upper chip 235, and wherein this metal coupling 205 is connected with this upper chip 235, and wherein this upper chip 235
Include other semiconductor electronic component；By the design of this rewiring road floor 217, can select this metal coupling 205
Arrange in position, this upper chip 235 of arranging in pairs or groups pad corresponding with this metal coupling 205；And electronic signal can
It is connected via this metal layer on back 207, this first metal layer 203 and this semiconductor electronic component 213, and again by this first gold medal
Belong to layer 203 and be transferred to this metal coupling 205 with this second metal layer 223, then through this metal coupling 205 by electronic signal
Transmit the semiconductor electronic component being comprised to this upper chip 235；Again under this metal layer on back 207, a module is set
Substrate 233, on this module group substrates 233, is set at least one joint routing 237 again, can partly be led this by this joint routing 237
The signal of body electronic component 213 connects to this module group substrates 233.
In sum, the present invention pass through with the combination substrate through-hole of the present invention and the semiconductor chip structure of projection and its
Manufacturing method thereof, is favorably improved the link density of semiconductor element, significantly can reduce wafer size, and speeds signal transmission speed
Degree, and power consumption can be reduced simultaneously, and it is provided that heterogeneous integration again, the therefore present invention can reach expected purpose really, and
There is good process stability and element reliability.
Embodiment described above is only the preferred embodiment lifted for absolutely proving the present invention, the protection model of the present invention
Enclose not limited to this.Equivalent substitute or conversion that those skilled in the art are made on the basis of the present invention, all in the present invention
Protection domain within.Protection scope of the present invention is defined by claims.
Claims (24)
1. a kind of combination substrate through-hole and the semiconductor chip structure of metal coupling are it is characterised in that primary structure includes：
One substrate；
At least one substrate through-hole, runs through this substrate；
At least one metal layer on back, is formed at the back side of this substrate, and this metal layer on back covers this substrate through-hole and extremely
Cover the back side of this substrate of part less；
At least one the first metal layer, is formed at the front of this substrate, and this first metal layer of wherein at least part leads in this substrate
The top in hole is contacted with this metal layer on back；
At least semiconductor electronic component, is formed at the front of this substrate, and this first metal layer of part and this quasiconductor of part
Electronic component contacts；And
At least one metal coupling, is formed on this first metal layer；
On this substrate, a protective layer is more set, makes this protective layer cover this substrate at least part of, this semiconductor electronic unit
Part and part this first metal layer, and this metal coupling and at least partly this first metal layer do not covered by this protective layer
Lid；
Between between this metal coupling and this first metal layer, more arranging at least one rewiring road floor so that this rewiring road floor
On this protective layer and this first metal layer, and this rewiring road floor is under this metal coupling, and wherein, this rewiring road
The structure of layer includes：
At least one dielectric layer, is formed on this protective layer and this first metal layer, and this dielectric layer cover part this substrate,
This protective layer and this first metal layer of part；
At least one dielectric layer through hole, runs through this dielectric layer；And
At least one second metal layer, be formed on this dielectric layer so that this second metal layer cover this dielectric layer through hole with
And at least cover this dielectric layer of part, and this second metal layer of wherein at least part is in the bottom of this dielectric layer through hole and part
This first metal layer contacts, and this metal coupling, is formed on this second metal layer.
2. combination substrate through-hole as claimed in claim 1 and the semiconductor chip structure of metal coupling are it is characterised in that constitute
The material of this dielectric layer is polybenzoxazoles.
3. combination substrate through-hole as claimed in claim 1 and the semiconductor chip structure of metal coupling are it is characterised in that constitute
The material of this second metal layer is gold, copper or gold copper.
4. combination substrate through-hole as claimed in claim 1 and the semiconductor chip structure of metal coupling are it is characterised in that constitute
The material of this protective layer is silicon nitride.
5. combination substrate through-hole as claimed in claim 1 and the semiconductor chip structure of metal coupling are it is characterised in that constitute
The material of this substrate is GaAs, carborundum, gallium nitride or indium phosphide.
6. the semiconductor chip structure of combination substrate through-hole as claimed in claim 1 and metal coupling is it is characterised in that in this
An added metal layer is more plated, the material wherein constituting this added metal layer is indium, stannum, indium alloy, stannum close on metal coupling
Gold or indium stannum alloy.
7. the semiconductor chip structure of combination substrate through-hole as claimed in claim 1 and metal coupling is it is characterised in that this base
Plate thickness be more than 10 μm be less than 300 μm between.
8. combination substrate through-hole as claimed in claim 1 and the semiconductor chip structure of metal coupling are it is characterised in that constitute
The material of this metal layer on back is gold, copper, palladium, nickel, silver, the alloy of nickel, gold copper, nickel billon, Ni-Pd alloy or porpezite
Alloy.
9. combination substrate through-hole as claimed in claim 1 and the semiconductor chip structure of metal coupling are it is characterised in that constitute
The material of this first metal layer is gold, copper or gold copper.
10. the combination substrate through-hole as described in claim 1 and metal coupling semiconductor chip structure it is characterised in that
The material constituting this metal coupling is copper, the alloy person of copper alloy, metal material or metal material.
A kind of 11. combination substrate through-holes and the manufacturing method thereof of the semiconductor wafer of metal coupling, comprise the following steps：
In the front of a substrate, form at least semiconductor electronic component；
In the front of this substrate, form at least one the first metal layer, and this first metal layer of part and this semiconductor electronic of part
Element contacts；
On this first metal layer, form at least one metal coupling；
In this substrate front side, form a protection metal coupling layer, so that this protection metal coupling layer is covered this substrate front side, be somebody's turn to do half
Conducting electrons element, this first metal layer and this metal coupling；
On this protection metal coupling layer, form a peel ply, make this peel ply cover this protection metal coupling layer；
On this peel ply, adhere to a upper upper substrate；
Grind and polish the back side of this substrate；
In the back side of this substrate, at least one substrate through-hole is produced with exposure imaging and etching technique, so that this substrate through-hole is run through
This substrate；
Plate at least one metal layer on back in the back side of this substrate, make this metal layer on back cover this substrate through-hole and at least
Cover the back side of this substrate of part, and this first metal layer of wherein at least part is in top and this back-side gold of this substrate through-hole
Belong to layer to contact；
In the back side of this substrate, vac sorb lives an infrabasal plate；
After heated, this upper substrate is made to peel off this peel ply；
Remove this peel ply and this protection metal coupling layer；And
Release vac sorb, removes this infrabasal plate.
The manufacturing method thereof of the semiconductor wafer of 12. combination substrate through-holes as claimed in claim 11 and metal coupling, its feature
It is, further comprising the steps：
Before this substrate front side forms this protection metal coupling layer, a protective layer is set prior on this substrate, makes this protection
Layer covers this substrate at least part of, this semiconductor electronic component and this first metal layer of part, and this metal coupling and
At least partly this first metal layer is not covered by this protective layer；Form this protection metal coupling layer then at this substrate front side, and
This protection metal coupling layer is made to cover this substrate front side, this first metal layer, this protective layer and this metal coupling.
The manufacturing method thereof of the semiconductor wafer of 13. combination substrate through-holes as claimed in claim 12 and metal coupling, its feature
It is, the material constituting this protective layer is silicon nitride.
The manufacturing method thereof of the semiconductor wafer of 14. combination substrate through-holes as claimed in claim 12 and metal coupling, its feature
It is, further comprising the steps：
Before forming this metal coupling on this first metal layer, prior to arrange on this protective layer and this first metal layer to
Few one reroutes road floor, and the structure of wherein this rewiring road floor includes：
At least one dielectric layer, is formed on this protective layer and this first metal layer, and this dielectric layer cover part this substrate,
This protective layer and this first metal layer of part；
At least one dielectric layer through hole, runs through this dielectric layer；And
At least one second metal layer, be formed on this dielectric layer so that this second metal layer cover this dielectric layer through hole with
And at least cover this dielectric layer of part, and this second metal layer of wherein at least part is in the bottom of this dielectric layer through hole and part
This first metal layer contacts；
Form this metal coupling afterwards on this second metal layer；
And make this protection metal coupling floor cover this rewiring road floor, this second metal layer, this dielectric layer, this dielectric layer through hole
And this metal coupling.
The manufacturing method thereof of the semiconductor wafer of 15. combination substrate through-holes as claimed in claim 14 and metal coupling, its feature
It is, the material constituting this dielectric layer is polybenzoxazoles.
The manufacturing method thereof of the semiconductor wafer of 16. combination substrate through-holes as claimed in claim 14 and metal coupling, its feature
It is, the material constituting this second metal layer is gold, copper or gold copper.
The manufacturing method thereof of the semiconductor wafer of 17. combination substrate through-holes as claimed in claim 11 and metal coupling, its feature
It is, the material constituting this substrate is GaAs, carborundum, gallium nitride or indium phosphide.
The manufacturing method thereof of the semiconductor wafer of 18. combination substrate through-holes as claimed in claim 11 and metal coupling, its feature
It is, more plates an added metal layer on this metal coupling, the material wherein constituting this added metal layer is indium, stannum, indium
Alloy, tin alloy or indium stannum alloy.
The manufacturing method thereof of the semiconductor wafer of 19. combination substrate through-holes as claimed in claim 11 and metal coupling, its feature
Be, this substrate thickness be more than 10 μm be less than 300 μm between.
The manufacturing method thereof of the semiconductor wafer of 20. combination substrate through-holes as claimed in claim 11 and metal coupling, its feature
It is, the material constituting this metal layer on back is gold, copper, palladium, nickel, silver, the alloy of nickel, gold copper, nickel billon, nickel palladium close
Gold or Polarium.
The manufacturing method thereof of the semiconductor wafer of 21. combination substrate through-holes as claimed in claim 11 and metal coupling, its feature
It is, the material constituting this first metal layer is gold, copper or gold copper.
The manufacturing method thereof of the semiconductor wafer of 22. combination substrate through-holes as claimed in claim 11 and metal coupling, its feature
It is, the material constituting this metal coupling is copper or copper alloy.
The manufacturing method thereof of the semiconductor wafer of 23. combination substrate through-holes as claimed in claim 11 and metal coupling, its feature
It is, this upper substrate is sapphire substrate.
The manufacturing method thereof of the semiconductor wafer of 24. combination substrate through-holes as claimed in claim 11 and metal coupling, its feature
It is, this infrabasal plate is carbide substrate.
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| CN201310079415.8A CN104051421B (en) | 2013-03-13 | 2013-03-13 | Semiconductor chip structure in conjunction with substrate through-hole and metal coupling and its manufacturing method thereof |
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| CN105914135A (en) * | 2016-05-31 | 2016-08-31 | 上海华虹宏力半导体制造有限公司 | Forming method of semiconductor device |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4970574A (en) * | 1988-05-31 | 1990-11-13 | Nec Corporation | Electromigrationproof structure for multilayer wiring on a semiconductor device |
| CN1671273A (en) * | 2004-03-16 | 2005-09-21 | 株式会社藤仓 | Device with through-hole interconnection and method for manufacturing the same |
| CN102655132A (en) * | 2011-03-02 | 2012-09-05 | 矽品精密工业股份有限公司 | Semiconductor structure and method for fabricating the same |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4970574A (en) * | 1988-05-31 | 1990-11-13 | Nec Corporation | Electromigrationproof structure for multilayer wiring on a semiconductor device |
| CN1671273A (en) * | 2004-03-16 | 2005-09-21 | 株式会社藤仓 | Device with through-hole interconnection and method for manufacturing the same |
| CN102655132A (en) * | 2011-03-02 | 2012-09-05 | 矽品精密工业股份有限公司 | Semiconductor structure and method for fabricating the same |
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