CN104051323A - Semiconductor packaging structure and preparation method thereof - Google Patents
Semiconductor packaging structure and preparation method thereof Download PDFInfo
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- CN104051323A CN104051323A CN201310080595.1A CN201310080595A CN104051323A CN 104051323 A CN104051323 A CN 104051323A CN 201310080595 A CN201310080595 A CN 201310080595A CN 104051323 A CN104051323 A CN 104051323A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
- H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
- H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
- H01L2224/02165—Reinforcing structures
- H01L2224/02166—Collar structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05556—Shape in side view
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
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Abstract
The invention provides a semiconductor packaging structure and preparation method thereof. The semiconductor packaging structure comprises a metal interconnection layer arranged on a semiconductor substrate, a metal shielding layer arranged on the metal interconnection layer, and a welding plate layer arranged on the metal shielding layer; and the metal shielding layer has a multi-layer superposition structure, wherein thermal expansion coefficients of all layers in the multi-layer superposition structure are decreased from bottom to top. Because the provided semiconductor packaging structure has the good thermodynamic property, size change differences of the metal interconnection layer and all sub layers of the metal shielding layers due to thermal expansion and cold contraction as well as the fracture probability of crystallization interfaces of all layers due to the size change differences after the annealing process of the semiconductor packaging structure preparation can be effectively reduced, thereby avoiding the welding plate peeling phenomenon. Moreover, the metal shielding layer with the multi-layer superposition structure has the good mechanical characteristic, thereby reducing damages on the active zone of the semiconductor device by various stresses generated by the welding wire bonding process.
Description
Technical field
The present invention relates to semiconductor preparation field, especially relate to a kind of semiconductor package and preparation method thereof.
Background technology
Along with semiconductor fabrication constantly in progressive, transistor grid size constantly dwindle, make constantly dwindling of integrated circuit (IC) apparatus size, and the semiconductor element of enormous amount is with multilayer interconnect structure, is embedded in thick and fast in chip base, and connects by multiple layer metal interconnection layer.In existing semiconductor technology, copper becomes the line of the most frequently used metal interconnecting layer with its good electric conductivity, the Chinese patent application that concrete technology can be CN1881557A referring to publication number.
In the back-end process of preparing at semiconductor device (The back end of line, BEOL), welding lead bonding techniques is a kind of widely used assembling encapsulation technology.It is included on the interconnection line of semiconductor chip the top a wire bond pads (wire bond pads is set, be called for short pad below), described pad material is mostly aluminium, and on pad, weld a lead-in wire the semiconductor element with circuit is connected to the pin in original paper encapsulation, and realize I/O(in/out) interface connection.Wherein the size of pad and the setting of lead-in wire and layout have determined the final size of integrated circuit (IC) apparatus.Thereby in existing semiconductor device preparation, mostly adopt bonding packaging (Bond Over Active on active area, BOA) technology, at active device, electrostatic discharge circuit (Electro-Static discharge, ESD), power supply and design bonding wire pad above earth bus to guarantee to reduce the size of chip.
In the development of welding lead bonding, copper lead material, with its good mechanical performance, electric conductivity and the price more cheap with respect to Precious Metals-Gold, is widely used in integrated antenna package field to carry out the encapsulation of high-end integrated circuit.
But than gold, the hardness of copper is larger, therefore, in encapsulation process, than previous gold wire bonds technology, copper lead-in wire needs higher ultrasonic power could be connected with pad with bonding action power (bond force).But larger ultrasonic power and bonding action power (bond force) are brought more challenges to wire bond pads, for example, easily cause metal pad (for example aluminium) extruding, extrude, pad cracked and coming off, the damage of metal lead wire, even the active area below para-linkage pad metal region (Bond Over Active, BOA) causes damage.
For example, for described problem (bonding damage and pad are peeled off), conventionally there are two kinds of solutions at present, a kind of is by DOE(Design Of Experiments) method optimizes bonding parameter, extruding force pad being caused to reduce bonded copper lead-in wire, but the method has limitation, for example, after bonding force reduces, will inevitably cause bonding copper ball to come off (ball lift), and can not meet effective bonding of copper lead-in wire and pad.Another method is the mechanical strength that increases pad, for example select the damage to active area below metal with opposing of metal screen layer that the larger material of hardness makes, as increase the concentration of Cu in pad aluminum alloy materials or other alloys, secondly, increasing diffusion shielding layer between aluminum pad and metallic copper interconnection layer also can reduce in bonding packaging process pad and the stress impact power of active region below thereof as the thickness of the larger materials of hardness such as TaN, TiN.In further technical development, with the metal screen layer that comprises the sandwich construction that material that the hardness such as the multiple layer metals such as TaN, TiN, Ta or metal nitride layer are larger forms with optimizing stress slowly-releasing.
Yet find in practical operation, no matter individual layer (generally adopts TaN layer, it is stronger for the ability that prevents the diffusion of copper-aluminium) or multiple layer metal shielding layer structure, metal screen layer is for preventing copper-aluminium diffusivity be directly proportional to the thickness stopping (TaN layer now is generally approximately 700A), but blocked up TaN and interconnecting metal are connected in Wire bonding strength test, tend to occur pad peeling, greatly reduce like this yield of semiconductor die package, and cause performance hidden danger to the semiconductor chip after follow-up encapsulation.
Summary of the invention
Problem solved by the invention is, in the metal interconnecting layer of existing semiconductor packages and pad lead key closing process, easily causes semiconductor device source region impaired, after lead key closing process, be prone to that pad is peeled off and metal interconnecting layer and pad between diffusion phenomena.
For addressing the above problem, the invention provides a kind of preparation method of semiconductor package, comprising:
In Semiconductor substrate, form metal interconnecting layer;
On metal interconnecting layer, form metal screen layer, described metal screen layer is multiple-layer stacked structure, and each layer in multiple-layer stacked structure from the bottom to top thermal coefficient of expansion successively decreases;
On described metal screen layer, form pad layer.
Alternatively, described multiple-layer stacked structure is double-deck overlaying structure or three layers of overlaying structure.
Alternatively, when metal screen layer is double-deck overlaying structure, forms step and comprise:
On described metal interconnecting layer, form Ti layer;
On described Ti layer, form TaN layer.
Alternatively, when metal screen layer is three layers of overlaying structure, forms step and comprise:
On described metal interconnecting layer, form Ti layer;
On described Ti layer, form TiN layer;
On described TiN layer, form TaN layer.
Alternatively, the method for formation metal screen layer is physical vaporous deposition.
Alternatively, the thickness of described TaN layer is 100 dust to 800 dusts, is preferably 100～500 dusts.
Alternatively, before forming metal screen layer, also comprise:
Deposit passivation layer above described metal interconnecting layer;
On passivation layer, form opening and expose described metal interconnecting layer.
The present invention also provides a kind of semiconductor package, comprising:
Be positioned at the metal interconnecting layer in Semiconductor substrate; Be positioned at the metal screen layer on described metal interconnecting layer; Be positioned at the pad layer on described metal screen layer;
Alternatively, described metal screen layer is multiple-layer stacked structure, and each layer in described multiple-layer stacked structure from the bottom to top thermal coefficient of expansion successively decreases.
Alternatively, described multiple-layer stacked structure is double-deck overlaying structure or three layers of overlaying structure.
Alternatively, when described multiple-layer stacked structure is double-deck overlaying structure, described metal screen layer comprises: Ti layer and be positioned at the TaN layer on described Ti layer.
Alternatively, when described multiple-layer stacked structure is three layers of overlaying structure, described metal screen layer comprises: Ti layer, be positioned at the TiN layer on described Ti layer and be positioned at the TaN layer on described TiN layer.
Alternatively, the thickness of described TaN layer is 100～800 dusts.
Alternatively, also comprise: on described metal interconnecting layer, deposit passivation layer, described metal screen layer and pad layer are arranged in described passivation layer.
Compared with prior art, technical scheme of the present invention has the following advantages:
In the metal screen layer of multiple-layer stacked structure, the thermal coefficient of expansion of each layer successively decreases from the bottom to top, in the semiconductor package that copper is metal interconnecting layer as take, in metal screen layer, the coefficient of expansion of the bottom and the coefficient of expansion of copper are the most approaching, and remaining each layer of coefficient of expansion successively decreases according to this.In the annealing operation of preparing at semiconductor device, each layer in metal interconnecting layer and multiple-layer stacked structure from the bottom to top, the change in volume of expanding with heat and contract with cold is successively decreased according to this, thereby can effectively reduce the cracking probability that the crystalizing interface of metal interconnecting layer, each metallic shield layering occurs because of change in volume.Above-mentioned semiconductor package has improved the bond strength between metal interconnecting layer, metal screen layer and each metal screen layer greatly, avoids occurring in lead key closing process pad peeling.And, the metal screen layer of multiple-layer stacked structure has better mechanical property, it can be alleviated in welding lead bonding technology, and for the stress impact of active region, the various stress that produce when guaranteeing to encapsulate can not cause damage to the active region of semiconductor device.
In possibility, in comprising three layers of overlaying structure of Ti layer, TiN layer and TaN layer, the expansion of metal coefficient of Ti and copper is close, in the annealing operation of preparing at semiconductor device, the change in volume difference of Ti layer and copper interconnection layer is little, thereby can guarantee integrated structure good between both crystalizing interfaces, to guarantee the bond strength of copper and Ti layer.And between the coefficient of expansion of TiN between Ti and TaN.Before and after annealing process, each layer in described three layers of overlaying structure be the change in volume trend that tapers off from the bottom to top, thereby the crystalizing interface causing based on change in volume difference between reduction adjacent two layers cracking probability, and TiN and Ti and TaN all have good wettability, even thereby after expanding with heat and contract with cold, between TiN layer and Ti layer, the crystalizing interface between TiN and TaN layer all has good bond strength.Three layers of overlaying structure of the above-mentioned Ti of comprising layer, TiN layer and TaN layer have further been strengthened the shielding of metal screen layer for the diffusion of the metal ion of interconnection layer and the metal ion of pad layer, and can effectively avoid occurring in lead key closing process pad peeling.
Accompanying drawing explanation
Fig. 1 to Fig. 5 is embodiment 1 schematic diagram that the present invention prepares semiconductor package;
Fig. 6 to Fig. 8 is embodiment 2 schematic diagrames that the present invention prepares semiconductor package;
Fig. 9 to Figure 11 is embodiment 3 schematic diagrames that the present invention prepares semiconductor package.
Embodiment
As mentioned in background technology, in existing semiconductor packaging process, often by arranging as the metal screen layer of the larger materials of hardness such as TaN, TiN, Ta, Ti between copper interconnecting line and pad (being mostly aluminium matter pad), to solve the higher ultrasonic power that adopts in copper lead-in wire and pad joint technology or larger combination power (stress migration, that abbreviation SM) causes damages for metal pad, for active area, cause stress damage, and the defect such as ion diffusion between copper and pad.
Yet thicker metal screen layer has directly reduced the strength of connection of metal screen layer and metal interconnecting layer, the semiconductor package of formation is prone to pad peeling.Analyze its reason, inventor thinks, as after the pad layer at aluminium material forms, the etching injury that the leading portion etching technics (for example reactive ion etching) of preparing for repairing semiconductor device causes silicon and each dielectric layer, and in the substrate thermal anneal process carrying out, copper interconnection layer is different from the coefficient of thermal expansion and contraction of metal screen layer, (copper is soft alloy, thermal coefficient of expansion is larger, and as TaN etc. be the fragility material that hardness is larger, thermal coefficient of expansion is less), both differ greatly at the change in volume based on the meeting of expanding with heat and contract with cold, thereby after annealing process, grain boundaries at metal screen layer is prone to cracking phenomena, copper metal can spread to aluminum pad along cracking place, reduced the shield effectiveness of metal screen layer to copper metal, and then increase the probability that electron transfer (EM) occurs when semiconductor device is used.
The invention provides a kind of semiconductor package and preparation method thereof for this reason.For above-mentioned purpose of the present invention, feature and advantage can be become apparent more, below in conjunction with accompanying drawing, the specific embodiment of the present invention is described in detail.
Embodiment 1
Shown in figure 1～Fig. 5, preparation method's detailed process of a kind of semiconductor package provided by the invention comprises:
In conjunction with reference to shown in figure 1, semi-conductive substrate 10 is provided, described Semiconductor substrate 10 has completed the FEOL in semiconductor fabrication, has formed active parts, is referred to as Semiconductor substrate 10 herein.In described Semiconductor substrate 10, form copper interconnection layer 11 and copper interconnection layer 11 medium 101 around.The technical process that forms copper interconnection layer is dual damascene (Dua-Damascene) technology, does not repeat them here.
In conjunction with reference to shown in figure 2, afterwards, deposit passivation layer 12 on described copper interconnection layer 11, to cover described copper interconnection layer 11; Described in patterning, passivation layer 12, form opening 13 to expose described copper interconnection layer 11.
During this time, described passivation layer 12 comprises that adopting chemical vapor deposition (CVD) method, plasma enhanced chemical gaseous phase deposition (PECVD) method, the plasma of formation to strengthen silicon nitride (PESIN) layer, plasma strengthens one or more the combination in tetraethoxysilane (PETEOS) layer, silicon nitride (SiN) layer and tetraethoxysilane (TEOS) layer.Can adopt afterwards photoresist pattern is mask, and with passivation layer 12 described in plasma etching industrial or reactive ion etching (RIE) technique etching, forms described opening 13, exposes described copper interconnection layer 11.In this process, comprising: adopt as fluorine-containing (F) gas nitrogen N
2, helium He and oxygen O
2mist etching step, and adopt afterwards ashing or wet clean process to remove photoresist figure step, this process does not repeat them here.
In conjunction with reference to shown in figure 3, after described passivation layer 12 forms, above described passivation layer 12, adopt physical vapor deposition (PVD) method depositing Ti layer 21 and TaN layer 22 successively, form the metal screen layer of double-deck overlaying structure.Afterwards, above described TaN layer 22, deposit aluminium lamination 23, as pad layer.
In conjunction with reference to shown in figure 4, aluminium lamination 23 described in patterning, and can CF
4, CHF
3, add in addition N
2, CO
2, O
2in one or more as etching atmosphere, adopt dry etching remove described aluminium lamination 23 two side portions and expose described passivation layer 12.And then with reference to shown in figure 5, on described passivation layer 12, deposit the attached passivation layer 14 of one deck, and attached passivation layer 14 described in patterning, form opening 15 and expose described aluminium lamination 23, to form semiconductor package.Described attached passivation layer 14, its forming process and patterning process are similar to described passivation layer 12, do not repeat them here.
From shown in Fig. 3 to Fig. 5, in the semiconductor package that the present embodiment forms, described Ti layer 21 is connected with described copper interconnection layer 11, and described TaN layer 22 is connected with the aluminium lamination 23 as pad layer.Wherein, described aluminium lamination 23 thickness are 4～50,000 dusts, and the thickness of described TaN layer 22 is 100～800 dusts, as 100 dusts, 150 dusts, 200 dusts, 250 dusts, 300 dusts, 400 dusts, 500 dusts ... 800 dusts, and the thickness of described Ti layer 21 is 100～1000 dusts.
Described Ti layer 21, TaN layer 22 and aluminium lamination 23 can adopt chemical vapor deposition (CVD) method or ald (ALD) method to form equally.The concrete structure of described Ti layer 21, TaN layer 22 and aluminium lamination 23 can be determined according to the concrete structure of integrated circuit.
After forming above-mentioned semiconductor package, complete as the subsequent techniques such as annealing formation integrated circuit.Again thereby this integrated circuit is encapsulated and produces complete integrated circuit (IC) chip.When to integrated antenna package, bonded copper lead-in wire on described aluminium lamination 23, afterwards again to copper lead-in wire and aluminium lamination 23 carry out bonding strength test, and the EM of the integrated circuit forming test and SM test.Find, on the semiconductor package of preparing at the present embodiment, after solder bond copper lead-in wire, copper lead-in wire does not have pad peeling to occur in testing with the bond strength of aluminium lamination, and copper lead-in wire is completely up to standard with the bond strength of aluminium lamination.In existing semiconductor package, described TaN layer thickness generally need be greater than 500 dusts just can effectively be suppressed interconnecting metal copper and spread to pad aluminium, in the present embodiment, it is only 100 dusts that the thickness of described TaN layer 22 can be thinned to, it not only can further dwindle the volume of semiconductor package, and every reliability testing is also completely up to standard.
Analyze its reason, the coefficient of expansion of Ti and copper is close, in annealing process, Ti and the copper volume change difference based on expanding with heat and contract with cold is little, make both crystalizing interfaces not be subject to both change in volume impacts and occur obvious cracking phenomena, it is good that this crystalizing interface structure keeps, and between Ti and TaN and between Ti and copper interconnecting line, all there is good wettability, between TaN and aluminium with there is good wettability, thereby there is good bond strength between copper interconnecting line, Ti layer, TaN layer and aluminium lamination.In addition, TaN hardness is large and the coefficient of expansion is less, change in volume in annealing process procedure is less, the change in volume of TaN and copper interconnecting line differs greatly, in the present embodiment, increased Ti layer between copper interconnection layer and TaN layer after, Ti metal effectively relaxed copper interconnecting line and TaN change in volume and cause at the stress difference producing between the two, greatly reduce before and after annealing the impact for the crystalizing interface of TaN layer.
Therefore, even if being reduced to 100A, TaN layer thickness also can guarantee the shield effectiveness to the diffusion of pad aluminium to copper interconnecting line, TaN layer thickness further reduces the total stress of TaN layer and the stress difference between copper interconnection layer and pad aluminium lamination after reducing simultaneously, thereby guaranteed between TaN layer and aluminium lamination, the crystalizing interface structure between TaN layer and Ti layer and between Ti layer and copper interconnection layer is intact.Satisfactory texture based on above-mentioned three crystalizing interfaces, described metal screen layer can effectively suppress interconnecting metal copper and spread to pad aluminium.Metallic shield layering hardness from top to bottom increases progressively, and this structure also can more effectively be alleviated in lead key closing process, and the stress producing, for the impact of the element in copper interconnection layer, active area and Semiconductor substrate, suppresses SM effect.
In sum, the double-deck overlaying structure of TaN layer and Ti layer has better thermodynamic behaviour with respect to existing semiconductor package (as the single-layer metal shielding layer structure of TaN) and (comprises each layer that the thermal expansion coefficient difference of each layer causes change in volume based on expanding with heat and contract with cold and occurring, and the change in volume based on each layer cause for bond strength impact between each layer) and mechanical property, thereby guarantee each layer of thermal coefficient of expansion and Stress match, when absorbing and offsetting welding lead bonding, act on copper lead-in wire, mechanical stress on aluminum pad layer and copper interconnecting line and thermal stress, the various stress that produce while guaranteeing to encapsulate can not go between to copper, aluminum pad and copper interconnecting line cause mechanical damage.
It should be noted that; the aluminum pad layer of above-mentioned final formation can be used as wire bond pads, probe pad and test point or needs other encapsulation or the test pad structure of supporting construction below, and aluminum pad concrete structure does not limit protection scope of the present invention.
Embodiment 2
The technical scheme of the present embodiment and embodiment 1 is roughly the same, in conjunction with reference to figure 6, its difference is only: in the semiconductor package preparation process of above-described embodiment 1, after described Ti layer 21 forms, adopt PVD method above the described Ti of stating layer 21, to deposit one deck TiN layer 24.Above described TiN layer 24, deposit again afterwards described TaN layer 22, thereby form the metal screen layer of three layers of overlaying structure.
In conjunction with reference to shown in figure 7 and Fig. 8, above described TaN layer 22, forming after described aluminium lamination 23, described in patterning, aluminium lamination 23, adopt dry etch process remove described aluminium lamination 23 two side portions and expose described passivation layer 12, and on described passivation layer 12, deposit the attached passivation layer 14 of one deck, attached passivation layer 14 described in patterning, forms opening 15 and exposes described aluminium lamination 23.
Now, in the semiconductor package that this example forms, described metal screen layer has comprised Ti layer 21, TiN layer 24 and TaN layer 22 from the bottom to top successively.Wherein, described TiN layer 24 is as the excessive layer between described Ti layer 21 and TaN layer 22.Between the coefficient of expansion of TiN between Ti and TaN, in annealing process, Ti layer 21, TiN layer 24 and the TaN layer 22 change in volume trend that tapers off, the double-deck overlaying structure that comprises Ti layer 21 and TaN layer 22 than embodiment 1, change in volume difference between different layerings is less, thereby can optimize the structure of crystalizing interface between different layers.And, between TiN layer 24 and Ti layer 21, and the wettability between TiN layer 24 and TaN layer 22 is obviously better than the wettability between Ti layer 21 and TaN layer 22, thereby described TiN layer 24 can effectively strengthen the bond strength of Ti layer 21 and TaN layer 22, and suppress better interconnecting metal copper and spread to pad aluminium.In addition, the hardness of TaN layer 22, TiN layer 24 and Ti layer 21 increases progressively according to this, and this structure is more conducive to alleviate the stress that produces in lead key closing process for the impact of the element in copper interconnection layer, active area and Semiconductor substrate.
In sum, the semiconductor package that the present embodiment forms guarantees that each layer of thermal coefficient of expansion and stress match, it acts on mechanical stress and thermal stress in copper lead-in wire and aluminum pad layer in the time of can absorbing and offset welding lead bonding, the various stress that produce while guaranteeing to encapsulate can not cause mechanical damage to copper lead-in wire and pad.Metal screen layer than the double-deck overlaying structure in embodiment 1 has better thermodynamics and mechanical property.
Wherein, the thickness of the described TaN layer 22 that the present embodiment forms is 100～800 dusts, remaining shielded metal layering (TiN layer and Ti layer) thickness also between in 100～1000 dusts, and the metal screen layer of three layers of overlaying structure that form is close with the double-level-metal shielding thickness in embodiment 1.Concrete structure can be determined according to the actual needs of integrated circuit.
Embodiment 3
The technical scheme of the present embodiment and above-described embodiment 1 and embodiment 2 is roughly the same, in conjunction with reference to figure 3, Fig. 6 and Fig. 9～Figure 11, its difference is, at above-mentioned Fig. 3 or Fig. 6, deposit after pad layer 23, above described pad layer 23, again deposit one or more layers attached metal screen layer, and deposit again another layer of pad layer 33 above described one or more layers attached metal screen layer.Afterwards, similar with above-mentioned patterning pad layer 23 processes, pad layer 33 described in patterning, and through etching technics, described in etching, pad layer 33, and each attached metal screen layer of described pad layer 33 belows and be the both sides of the metal screen layer of multiple-layer stacked structure, until expose described passivation layer 12.Above described pad layer 33 and passivation layer 12, deposit the attached passivation layer 16 of one deck, and described in patterning, attached passivation layer 16 forms opening 17, to expose described pad layer 33, thereby form the semiconductor package (as shown in figure 11) that comprises two-layer pad layer 23 and 33.
Particularly, in conjunction with reference to shown in figure 9, take embodiment 2 as example.
After aluminium lamination 23 depositions in embodiment 2 (with reference to figure 6), the attached metal screen layer 31 and 32 of stack deposition according to this above described aluminium lamination 23, and another layer of aluminium lamination 33.Wherein, being positioned at undermost attached metal screen layer 31 is connected with described aluminium lamination 23.Described attached metal screen layer is chosen as Ti, TiN or TaN layer.Described attached metal screen layer 31 and 32, and aluminium lamination 33 its all can adopt the methods such as chemical vapor deposition (CVD) method, physical vapor deposition (PVD) method or ald (ALD) method to form.
Afterwards, shown in Figure 10, aluminium lamination 33 described in patterning, and can CF
4, CHF
3, add in addition N
2, CO
2, O
2in one or more as etching atmosphere, adopt dry etching to remove the two side portions of described aluminium lamination 33, described attached metal screen layer 31 and 32, aluminium lamination 23, Ti layer 21, TiN layer 24 and TaN layer 22, until expose described passivation layer 12.
In conjunction with reference to Figure 11, on described passivation layer 12 and described aluminium lamination 33, deposit the attached passivation layer 16 of one deck, and attached passivation layer 16 described in patterning, form opening 17 and expose described aluminium lamination 33, form the semiconductor package that comprises two-layer pad layer (pad layer 23 and 33).The forming process of described attached passivation layer 16 is similar to described passivation layer 12 forming processes, does not repeat them here.
It should be noted that, in the present invention, as as described in embodiment 1 and 2 as described in after pad layer forms, can adopt technique as described in example 3 above above pad layer, to form multilayer pad layer, and between each pad layer, respectively form one or more layers attached metal screen layer.Described multilayer pad layer structure can further be optimized in pad lead key closing process, for the active area protection under interconnecting metal layer and interconnecting metal layer.Solve the problem that pad layer cracks and damages in encapsulation process simultaneously, further to improve the bonding force of described pad layer and lead-in wire, make lead-in wire and pad layer in conjunction with more stable, strengthen the Performance And Reliability of the last semiconductor package forming, further improve the yield of product.The number of plies of described attached metal screen layer does not limit protection scope of the present invention.
The foregoing is only specific embodiments of the invention; object is in order to make those skilled in the art better understand spirit of the present invention; it is limited range that yet protection scope of the present invention not take the specific descriptions of this specific embodiment; any those skilled in the art is not within departing from the scope of spirit of the present invention; can make an amendment specific embodiments of the invention, and not depart from protection scope of the present invention.
Claims (13)
1. a preparation method for semiconductor package, is characterized in that,
In Semiconductor substrate, form metal interconnecting layer;
On metal interconnecting layer, form metal screen layer, described metal screen layer is multiple-layer stacked structure, and each layer in multiple-layer stacked structure from the bottom to top thermal coefficient of expansion successively decreases;
On described metal screen layer, form pad layer.
2. preparation method as claimed in claim 1, is characterized in that, described multiple-layer stacked structure is double-deck overlaying structure or three layers of overlaying structure.
3. preparation method as claimed in claim 2, is characterized in that, when metal screen layer is double-deck overlaying structure, forms step and comprises:
On described metal interconnecting layer, form Ti layer;
On described Ti layer, form TaN layer.
4. preparation method as claimed in claim 2, is characterized in that, when metal screen layer is three layers of overlaying structure, forms step and comprises:
On described metal interconnecting layer, form Ti layer;
On described Ti layer, form TiN layer;
On described TiN layer, form TaN layer.
5. preparation method as claimed in claim 1, is characterized in that, the method that forms metal screen layer is physical vaporous deposition.
6. the preparation method as described in claim 3 or 4, is characterized in that, the thickness of described TaN layer is 100 dust to 800 dusts.
7. preparation method as claimed in claim 1, is characterized in that, before forming metal screen layer, also comprises:
Deposit passivation layer above described metal interconnecting layer;
On passivation layer, form opening and expose described metal interconnecting layer.
8. a semiconductor package, comprising:
Be positioned at the metal interconnecting layer in Semiconductor substrate; Be positioned at the metal screen layer on described metal interconnecting layer; Be positioned at the pad layer on described metal screen layer;
It is characterized in that, described metal screen layer is multiple-layer stacked structure, and each layer in described multiple-layer stacked structure from the bottom to top thermal coefficient of expansion successively decreases.
9. semiconductor package as claimed in claim 8, is characterized in that, described multiple-layer stacked structure is double-deck overlaying structure or three layers of overlaying structure.
10. semiconductor package as claimed in claim 9, is characterized in that, when described multiple-layer stacked structure is double-deck overlaying structure, described metal screen layer comprises: Ti layer and be positioned at the TaN layer on described Ti layer.
11. semiconductor packages as claimed in claim 1, is characterized in that, when described multiple-layer stacked structure is three layers of overlaying structure, described metal screen layer comprises: Ti layer, be positioned at the TiN layer on described Ti layer and be positioned at the TaN layer on described TiN layer.
12. semiconductor packages as described in claim 10 or 11, is characterized in that, the thickness of described TaN layer is 100～800 dusts.
13. semiconductor packages as claimed in claim 8, is characterized in that, also comprise: on described metal interconnecting layer, deposit passivation layer, described metal screen layer and pad layer are arranged in described passivation layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310080595.1A CN104051323B (en) | 2013-03-13 | 2013-03-13 | A kind of semiconductor package and preparation method thereof |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310080595.1A CN104051323B (en) | 2013-03-13 | 2013-03-13 | A kind of semiconductor package and preparation method thereof |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105448870A (en) * | 2014-06-23 | 2016-03-30 | 中芯国际集成电路制造(上海)有限公司 | Bonding pad structure, manufacturing method therefor, and semiconductor device |
| CN106158735A (en) * | 2015-04-21 | 2016-11-23 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method of semiconductor device, semiconductor devices and electronic installation |
| CN110875242A (en) * | 2018-08-30 | 2020-03-10 | 台湾积体电路制造股份有限公司 | Semiconductor device and method of forming the same |
| CN110972418A (en) * | 2018-09-30 | 2020-04-07 | 比亚迪股份有限公司 | Electronic device case, electronic device, and composite body |
| WO2022057339A1 (en) * | 2020-09-17 | 2022-03-24 | 长鑫存储技术有限公司 | Solder pad structure, semiconductor structure, semiconductor packaging structure, and preparation method therefor |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020011669A1 (en) * | 1999-01-28 | 2002-01-31 | Noriaki Fujiki | Semiconductor device |
| CN1350703A (en) * | 1999-05-19 | 2002-05-22 | 国际商业机器公司 | Robust interconnect structure |
| CN1503344A (en) * | 2002-11-27 | 2004-06-09 | ���ǵ�����ʽ���� | Method for forming aluminium lead wire |
| CN1770423A (en) * | 2004-09-30 | 2006-05-10 | 株式会社东芝 | Method of manufacturing semiconductor device |
| US20090121354A1 (en) * | 2007-11-09 | 2009-05-14 | Hynix Semiconductor Inc. | Semiconductor Device and Method of Fabricating the Same |
-
2013
- 2013-03-13 CN CN201310080595.1A patent/CN104051323B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020011669A1 (en) * | 1999-01-28 | 2002-01-31 | Noriaki Fujiki | Semiconductor device |
| CN1350703A (en) * | 1999-05-19 | 2002-05-22 | 国际商业机器公司 | Robust interconnect structure |
| CN1503344A (en) * | 2002-11-27 | 2004-06-09 | ���ǵ�����ʽ���� | Method for forming aluminium lead wire |
| CN1770423A (en) * | 2004-09-30 | 2006-05-10 | 株式会社东芝 | Method of manufacturing semiconductor device |
| US20090121354A1 (en) * | 2007-11-09 | 2009-05-14 | Hynix Semiconductor Inc. | Semiconductor Device and Method of Fabricating the Same |
Non-Patent Citations (1)
| Title |
|---|
| 毛卫民: "《工程材料学原理》", 31 October 2009, 北京：高等教育出版社 * |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105448870A (en) * | 2014-06-23 | 2016-03-30 | 中芯国际集成电路制造(上海)有限公司 | Bonding pad structure, manufacturing method therefor, and semiconductor device |
| CN106158735A (en) * | 2015-04-21 | 2016-11-23 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method of semiconductor device, semiconductor devices and electronic installation |
| CN106158735B (en) * | 2015-04-21 | 2019-02-01 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method of semiconductor device, semiconductor devices and electronic device |
| CN110875242A (en) * | 2018-08-30 | 2020-03-10 | 台湾积体电路制造股份有限公司 | Semiconductor device and method of forming the same |
| US11682639B2 (en) | 2018-08-30 | 2023-06-20 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device and method of forming the same |
| CN110972418A (en) * | 2018-09-30 | 2020-04-07 | 比亚迪股份有限公司 | Electronic device case, electronic device, and composite body |
| WO2022057339A1 (en) * | 2020-09-17 | 2022-03-24 | 长鑫存储技术有限公司 | Solder pad structure, semiconductor structure, semiconductor packaging structure, and preparation method therefor |
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| CN104051323B (en) | 2017-12-29 |
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