CN104051002B - Primary particle inversion resistant SRAM type FPGA refreshes circuit and method for refreshing - Google Patents
Primary particle inversion resistant SRAM type FPGA refreshes circuit and method for refreshing Download PDFInfo
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- CN104051002B CN104051002B CN201410250530.1A CN201410250530A CN104051002B CN 104051002 B CN104051002 B CN 104051002B CN 201410250530 A CN201410250530 A CN 201410250530A CN 104051002 B CN104051002 B CN 104051002B
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Abstract
nullPrimary particle inversion resistant SRAM type FPGA refreshes circuit and method for refreshing，Relate to the anti-single particle upset field, space of field programmable gate array，Solve existing SRAM type FPGA refreshing circuit and method utilizes peripheral control unit realization to reload configuration order and configuration data，There is circuit complexity high，There is the problems such as unstability in controller，Use the memorizer that two panels is identical，BOOT stores complete configuration file，Configuration file contains user's functional module to be realized and FGPA realizes the refresh module that self refreshes，SCRUB stores the configuration file after editor，After FPGA has loaded first memorizer，Refresh module launches into refresh mode，By periodically reading the configuration file in SCRUB memorizer，Realize the periodic refresh under FPGA normally works.The present invention is effectively reduced power consumption and the circuit complexity that FPGA refreshes.
Description
Technical field
The present invention relates to field-programmable gate array technical field, particularly relate to two panels memorizer and realize one
Plant SRAM type FPGA primary particle inversion resistant refreshing circuit and method.
Background technology
FPGA based on SRAM (static random access memory, SRAM) is because of it
Multiformity in terms of functional configuration with repeatable, the little distinguishing feature such as short with the R&D cycle of application volume, quilt
It is widely applied to space industry, although being easier to compared to the FPGA of special IC and antifuse configuration
By the impact of single-particle (single event effect, SEE), but its prominent superiority makes it still hold
Carry on a shoulder pole the challenges such as the appearance control of aircraft under spatial environments, number biography and image procossing, and progressively develop into
A kind of trend
Owing to Energetic particle impact is relatively big, the logic state of SRAM type FPGA internal configuration memorizer
Usually overturn owing to particle clashes into, single-particle inversion i.e. occurs.If upset occurs in memory, make
Can be reset by signal；If it occur that in logic function district, spacecraft function may be caused to interrupt, no matter occur
Spacecraft may all can be had an immense impact on by which kind of.
Xilinx company first generation Virtex FPGA starts, about SRAM type FPGA fault-tolerance study not
Disconnect, Flouride-resistani acid phesphatase design and triplication redundancy (TMR) design constantly application.The application of TMR design is the most not
Can meet the long reliability of FPGA, the accumulation of internal single-particle inversion may cause the mistake of TMR,
Needing to remove all rollovers position according to certain frequency to correct FPGA, a kind of method is returning of bit stream
Reading, reload when flip bit being detected, this method needs to consume the substantial amounts of time.Another
The method of simple anti-SEU is to ignore retaking of a year or grade detecting step, only reloads whole CLB frame block and BRAM
Inline frame block, this method is called refreshing, refreshes and substantially requires less system resource, but this meaning
The time configuration logic the biggest is at " WriteMode ", and once the complete cycle refreshed needs to be set relatively
Short.Refresh all SEU on permission system reparation configuration memorizer and not interrupt system properly functioning.Generally
Method for refreshing be utilize peripheral control unit realize to configuration order and configuration data reload, the method
Circuit complexity is high, and controller there is also certain unstability, it is necessary to propose a kind of circuit complexity low,
Low in energy consumption, reliability higher anti-single particle reverse circuit.
Summary of the invention
The present invention solves that existing SRAM type FPGA refreshing circuit and method utilize peripheral control unit to realize right
Configuration order is reloaded with configuration data, there is circuit complexity high, and controller exists unstability etc.
Problem, it is provided that a kind of primary particle inversion resistant SRAM type FPGA refreshes circuit and method for refreshing.
Primary particle inversion resistant SRAM type FPGA refreshes circuit, including BOOT memorizer and SCRUB
Memorizer；Described BOOT memorizer is used for storing user function module, and it is right that SCRUB memorizer is used for storing
Configuration file in BOOT memorizer update after configuration file, described BOOT memorizer by number
The loading to FPGA is realized according to line and control line；After loading completes, FPGA internal refresh module is periodic
Controlling I/O mouth, described I/O mouth is connected with the control end of SCRUB memorizer；Control SCRUB memorizer
In configuration file be periodically loaded in FPGA.
Primary particle inversion resistant SRAM type FPGA refreshes the method for refreshing of circuit, and the method is by following steps
Realize:
Step one, use fever writes by complete configuration file programming to BOOT memorizer, simultaneously refreshed join
Put file programming to SCRUB memorizer；
Step 2, to refreshing after circuit powers on, FPGA removes internal configuration data, waits to be initiated completing；
After step 3, FPGA initialize successfully, BOOT memorizer is initially configured data, through T1 millisecond
After, BOOT memorizer has configured, and FPGA normally works, and FPGA internal refresh functions of modules starts；
Described T1 is the time that FPGA completes a complete configuration；
After step 4, T2 millisecond, FPGA enters auto refresh mode, and FPGA internal refresh module controls
Corresponding I/O mouth, periodically controls SCRUB memory operation, the refreshing in described SCRUB memorizer
Configuration file will be loaded in FPGA；Described T2 such as is at the time to be refreshed；
After step 5, T3 millisecond, Refreshing Configuration Files has loaded, and FPGA internal refresh module controls
SCRUB memorizer quits work, and completes once to refresh；Described T3 has been that a refresh configuration needs
Time；
Step 6, repeated execution of steps four and step 5, FPGA refreshes performance period.
Beneficial effects of the present invention: SRAM type FPGA circuitry of the present invention, complexity is low, power consumption
The anti-single particle upset that low, reliability is high refreshes circuit.
One, refresh function module of the present invention is integrated in inside FPGA, it is not necessary to peripheral control unit,
Only increase a piece of SCRUB memorizer, simplify conventional brush novel circuit, reduce circuit power consumption.And FPAG
The probability of overall generation single-particle inversion is extremely low, and in refresh module utilizes sheet, resource is little, almost can neglect
Slightly, it occurs the probability of single-particle inversion near 0, and circuit fault-tolerance improves；
Two, BOOT memorizer of the present invention and SCRUB memorizer share 8 position datawires,
Control line is independent.SCRUB memorizer stores the configuration updating configuration file in BOOT memorizer
File, this configuration file does not interferes with FPGA and normally works and omit retaking of a year or grade function；
Three, memorizer of the present invention be have can single programming (OTP) framework memorizer, such is deposited
Reservoir has the highest radiation-resisting performance, has the highest inheritance in aerospace craft.Configure literary composition simultaneously
Part passes through fever writes programming, and when JTAG will not be occurred to download, the problem of CRC check mistake, substantially reduces
Complexity to Refreshing Configuration Files amendment.
Four, refreshing circuit of the present invention can apply to the FPGA core of any support dynamic refresh function
On sheet.
Accompanying drawing explanation
Fig. 1 is the refreshing principle that primary particle inversion resistant SRAM type FPGA of the present invention refreshes circuit
Figure；
Fig. 2 is that primary particle inversion resistant SRAM type FPGA of the present invention refreshes SCRUB in circuit
In memorizer, configuration file updates flow chart；
Fig. 3 is the method for refreshing that primary particle inversion resistant SRAM type FPGA of the present invention refreshes circuit
Flow chart.
Detailed description of the invention
Detailed description of the invention one, combine Fig. 1 and Fig. 2 present embodiment, primary particle inversion resistant SRAM are described
Type FPGA refreshes circuit；Including BOOT memorizer and SCRUB memorizer.BOOT memorizer stores
User function module, is powered on and is completed the normal load of FPGA by data wire and control line, when having loaded
After one-tenth, FPGA refresh module can periodically control its corresponding I/O mouth, this I/O mouth and SCRUB memorizer
Control end be connected, make the configuration file in SCRUB memorizer periodically be loaded in FPGA,
The file of SCRUB memorizer storage is to the amended configuration file of configuration file in BOOT memorizer, should
File resets affecting the configuration-direct that FPGA normally works or deletes before loading, institute
It is always maintained at normally working with FPGA, if FPGA refresh module generation single-particle inversion, can pass through
Reloading mode ensures that FPGA normally works, and whole process FPGA is constantly in write state.
Refresh function module in present embodiment is integrated in FPGA therein, it is not necessary to peripheral control unit,
Only increase a piece of SCRUB memorizer, simplify conventional brush novel circuit.This refreshing circuit can apply to any
Support on the fpga chip of dynamic refresh；Described BOOT memorizer and SCRUB memorizer share one
Bar 8 position datawire, control line is independent.Wherein, BOOT memorizer stores complete configuration file, and
SCRUB memorizer stores the configuration file updating configuration file in BOOT memorizer, specifically walks
Suddenly Fig. 2 is combined；
In present embodiment, two panels memorizer and FPGA system clock all share external crystal-controlled oscillation, it is ensured that
FPGA refreshes the stability of sequential, also includes outside reloading circuit, reconfigures signal by setting low FPGA
Realize FPGA to restart.FPGA refresh module function is only the periodic Control to two I/O mouths, it is ensured that
Correct being loaded in FPGA of configuration file in SCRUB memorizer.Due to FPAG entirety generation single-particle
In the probability of upset is extremely low, and refresh module utilizes sheet, resource is little, almost can ignore, and it occurs simple grain
The probability of son upset is near 0, and circuit fault-tolerance improves.
In present embodiment two panels memorizer use have can word programming (OTP) framework memorizer, such
Memorizer configuration file pass through fever writes programming, the problem of CRC check mistake when JTAG will not be occurred to download,
Substantially reducing the complexity to Refreshing Configuration Files amendment, such memorizer has the highest Flouride-resistani acid phesphatase simultaneously
Characteristic, has the highest inheritance and reliability in aerospace craft.
Detailed description of the invention two, combining Fig. 3 present embodiment is described, present embodiment is detailed description of the invention
Primary particle inversion resistant SRAM type FPGA described in one refreshes the method for refreshing of circuit, and the method is by following
Step realizes:
One, utilize fever writes by integrated configuration file programming to BOOT memorizer, simultaneously by refresh configuration literary composition
Part programming is to SCRUB memorizer；
Two, system electrification, FPGA understands internal configuration data, waits to be initiated completing；
Three, FPGA initializes successfully, and BOOT memorizer is initially configured data, and configuration mode selects Salve
SelectMap mode；
Four, T1After Hao Miao, BOOT memory data has configured, and enables signal and is set low, chip selection signal
Being set high, this memorizer is prohibited, and internal address counter empties, and data output is in high-impedance state.FPGA
Normal work, refresh module function on；
Five, T2After Hao Miao, FPGA enters auto refresh mode, and refresh module controls corresponding I/O mouth, cycle
Property ground SCRUB memorizer Enable Pin is set high, chip selection signal sets low, and SCRUB memorizer is started working,
Refreshing Configuration Files will be loaded in FPGA；
Six, T3After Hao Miao, Refreshing Configuration Files has loaded, and FPGA refresh module is by SCRUB memorizer
Enable signal sets low, and chip selection signal sets high, and whole loading procedure FPGA normally works, and completes once to refresh；
Seven, constantly repeating the 5th step and the 6th step, FPGA realizes (T2+T3) millisecond ground periodic refresh.
If eight refresh module functions are made mistakes, FPGA can be restarted by reloading mode, rerun with
Upper step realizes FPGA and refreshes.
Wherein, T1Represent that FPGA completes the time required for a complete configuration；T2When expressions etc. are to be refreshed
Between；T3Table completes a refresh configuration required time, this time T3It is substantially equal to T1, (T2+T3) represent twice
The refresh interval time.
In present embodiment, refresh time depends on frequency and the size of configuration file position bit stream of configurable clock generator.
Refresh cycle after minimizing in reality is of substantially equal with refresh time, it is ensured that system is averagely in each upset
Gap performs at least 10 refresh operations.
Claims (10)
1. primary particle inversion resistant SRAM type FPGA refreshes a circuit, it is characterized in that, including BOOT
Memorizer and SCRUB memorizer；Described BOOT memorizer is used for storing user function module, SCRUB
Memorizer configuration file after the configuration file in BOOT memorizer is updated by storage, described
BOOT memorizer realizes the loading to FPGA by data wire and control line；After loading completes, in FPGA
Portion's refresh module periodically controls I/O mouth, and described I/O mouth is connected with the control end of SCRUB memorizer；
Control the configuration file in SCRUB memorizer to be periodically loaded in FPGA.
Primary particle inversion resistant SRAM type FPGA of one the most according to claim 1 refreshes circuit,
It is characterized in that, also include outside reloading circuit, when FPGA internal refresh module generation single-particle inversion
Time, make FPGA normally work by reloading circuit.
Primary particle inversion resistant SRAM type FPGA of one the most according to claim 1 refreshes circuit,
It is characterized in that, described BOOT memorizer and SCRUB memorizer share the data wire of eight, control line
Independent use.
Primary particle inversion resistant SRAM type FPGA of one the most according to claim 1 refreshes circuit,
It is characterized in that, described SCRUB memorizer is for storage to the configuration file in BOOT memorizer again
Configuration file after editor, the step of the configuration file updated in SCRUB memorizer is:
Step A, ISE Software Create configuration file, update the bitstream header file of generation, reset FAR
Register value, retains the configuration data of CLB frame block；
BRAM frame block configuration data in the configuration file of the bitstream header file that step B, deletion generate, again
Set FAR register value, retain BRAM inline frame blocks of data；
Step C, deletion crc register bit stream file also update configuration bit-stream tail file,
Obtain the configuration file after updating.
5. use the primary particle inversion resistant SRAM of one described in claim 1-4 any one claim
The method for refreshing refreshing circuit of type FPGA, is characterized in that, the method is realized by following steps:
Step one, use fever writes by complete configuration file programming to BOOT memorizer, simultaneously refreshed join
Put file programming to SCRUB memorizer；
Step 2, to refreshing after circuit powers on, FPGA removes internal configuration data, waits to be initiated completing；
After step 3, FPGA initialize successfully, BOOT memorizer is initially configured data, through T1 millisecond
After, BOOT memorizer has configured, and FPGA normally works, and FPGA internal refresh functions of modules starts；
Described T1 is the time that FPGA completes a complete configuration；
After step 4, T2 millisecond, FPGA enters auto refresh mode, and FPGA internal refresh module controls
Corresponding I/O mouth, periodically controls SCRUB memory operation, the refreshing in described SCRUB memorizer
Configuration file will be loaded in FPGA；Described T2 such as is at the time to be refreshed；
After step 5, T3 millisecond, Refreshing Configuration Files has loaded, and FPGA internal refresh module controls
SCRUB memorizer quits work, and completes once to refresh；Described T3 has been that a refresh configuration needs
Time；
Step 6, repeated execution of steps four and step 5, FPGA refreshes performance period.
The refreshing circuit of a kind of primary particle inversion resistant SRAM type FPGA the most according to claim 5
Method for refreshing, it is characterised in that in step 3, described BOOT memorizer has configured, by BOOT
The enable signal of memorizer sets low, and chip selection signal sets high, and BOOT memorizer quits work.
The refreshing circuit of a kind of primary particle inversion resistant SRAM type FPGA the most according to claim 5
Method for refreshing, it is characterised in that in step 4, described FPGA internal refresh module periodically will
SCRUB memorizer Enable Pin sets high, and chip selection signal sets low, and SCRUB memorizer is started working.
The refreshing circuit of a kind of primary particle inversion resistant SRAM type FPGA the most according to claim 5
Method for refreshing, it is characterised in that in step 5, Refreshing Configuration Files has loaded, FPGA internal refresh
The enable signal of SCRUB memorizer is set low by module, and chip selection signal sets high, and SCRUB memorizer stops adding
Carrying work, in loading procedure, FPAG normally works, and completes once to refresh.
The refreshing circuit of a kind of primary particle inversion resistant SRAM type FPGA the most according to claim 5
Method for refreshing, it is characterised in that when FPGA internal refresh functions of modules is made mistakes, then heavily added by outside
Carry circuit and restart FPGA, it is achieved the refreshing to FPGA.
The refreshing electricity of a kind of primary particle inversion resistant SRAM type FPGA the most according to claim 5
The method for refreshing on road, it is characterised in that described BOOT memorizer, SCRUB memorizer and FPGA time
Clock shares external crystal-controlled oscillation, it is achieved FPGA refreshes the stability of sequential.
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| CN104637530B (en) * | 2014-04-17 | 2017-10-24 | 清华大学 | A kind of redundancy structure random access storage device |
| CN110209547B (en) * | 2019-05-05 | 2023-06-16 | 北京空间飞行器总体设计部 | SRAM type FPGA single event upset reinforcement timing refresh frequency determination method and system |
| CN111143107B (en) * | 2019-11-13 | 2022-06-17 | 广东高云半导体科技股份有限公司 | FPGA single event reversal verification circuit and method |
| CN111785310A (en) * | 2020-08-04 | 2020-10-16 | 中国科学院近代物理研究所 | FPGA (field programmable Gate array) reinforcement system and method for resisting single event upset |
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| CN201549234U (en) * | 2009-07-23 | 2010-08-11 | 西安空间无线电技术研究所 | SRAM-based FPGA configuring and refreshing integrated device |
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| US6838331B2 (en) * | 2002-04-09 | 2005-01-04 | Micron Technology, Inc. | Method and system for dynamically operating memory in a power-saving error correction mode |
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| CN201549234U (en) * | 2009-07-23 | 2010-08-11 | 西安空间无线电技术研究所 | SRAM-based FPGA configuring and refreshing integrated device |
| CN103325411A (en) * | 2013-06-20 | 2013-09-25 | 上海航天测控通信研究所 | Single event upset resisting reinforcing system and method used for FPGA (Field Programmable Gate Array) |
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