CN104038184A - QETFF circuit unit based on CMOS technology - Google Patents
QETFF circuit unit based on CMOS technology Download PDFInfo
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- CN104038184A CN104038184A CN201310284373.1A CN201310284373A CN104038184A CN 104038184 A CN104038184 A CN 104038184A CN 201310284373 A CN201310284373 A CN 201310284373A CN 104038184 A CN104038184 A CN 104038184A
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- circuit
- qetff
- triggered flip
- edge triggered
- umux
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Abstract
The invention discloses a QETFF circuit unit based on a CMOS technology. The circuit unit is mainly composed of a uMUX circuit module. The uMUX circuit module comprises a first NMOS tube, a second NMOS tube, a third NMOS tube, a fourth NMOS tube, a fifth NMOS tube, a sixth NMOS tube, a first PMOS tube, a second PMOS tube, a third PMOS tube, a fourth PMOS tube, a fifth PMOS tube and a sixth PMOS tube. The QETFF circuit unit has the following advantages: under the condition that functions are correct, compared to a conventional circuit, eight MOS tubes are saved, and the circuit complexity is reduced; and an analysis comparison shows that the critical path of a QETFF circuit is shortened by a half compared to that of the conventional circuit, the length of each data output path in the circuit is uniform, and the problem of varying length of each data output path in the conventional circuit is prevented.
Description
Technical field the present invention relates to a kind of CMOS based on ternary clock being made up of data selector tetra-edge triggered flip flop QETFF (Quad-Edge-Triggered Flip-Flop).
Background technology is because ternary clock has four saltus steps (edge) in one-period, many one times of twice saltus step than traditional two-value clock in one-period, so the four edge triggered flip flop QETFF (Quad-Edge-Triggered Flip-Flop) based on ternary clock have the feature [1] of low-power consumption.From prior art, four edge triggered flip flops that document [1] proposes are that first is to all triggers of sensitivity of four of ternary clock saltus steps.This trigger utilizes the one-out-three data selector (MUX) in document [2,3,4] to realize all functions of sensitivity of four of ternary clock saltus steps.From the cmos circuit figure of one-out-three MUX, can find out, this one-out-three MUX has three to be denoted as 0,1 and 2 data input pin, selects control end and a data output end for one.In passage path three of this MUX from input to output, there are two to be to be formed by a transmission gate, have one to be to be formed by the transmission gate of two series connection.Therefore, its critical path (the longest path) is 2 transmission gates.Because the length of these three passage path differs, can cause the inhomogeneity of the data outgoing route length of four edge triggered flip flops, this can have influence on the stability problem of four edge triggered flip flop performances.Further, four edge triggered flip flop circuit structures in document [1] are carried out can finding after serious analysis, the data input pin 0 and 2 of three one-out-three MUX is always connected in parallel, and makes like this one in these two data input pins to become a redundant input end.Therefore, also exist the problem of redundant data input in this four edge triggered flip flop, this can increase the unnecessary complexity of circuit and cause the problem of electronic devices and components waste.
List of references:
[1] Lang Yanfeng, Shen Jizhong. low-power consumption four edge triggered flip flop designs [J]. Circuits and Systems journal, 2012,17 (6): 37-41.
[2]Wu，X.，Prosser，F.：Design?ofternary?CMOS?circuits?based?on?transmission?function?theory，International?Journal?of?Electronics，1988，65，(5)，pp.891-905
[3]Prosser，F.，Wu，X.，Chen，X.CMOS?Ternary?Flip-Flops?&?Their?Applications.IEE?Proceedings?on?Computer&Digital?Techniques1988；135(5)：266-272.
[4] Hu Junfeng, Shen Jizhong, Yao Maoqun etc. Design of low power multivalued double-edge-triggered flip-flop [J]. journal of Zhejiang university (engineering version), 2005,39 (11): 1699-1702.
Summary of the invention is for the stability of above-mentioned four edge triggered flip flop QETFF and the problem of redundant data input, task of the present invention is exactly to keep under the constant prerequisite of four edge triggered flip flop functions, make the data outgoing route homogeneous of four edge triggered flip flops, performance parameter is stable, reduces the complexity of circuit and the metal-oxide-semiconductor use amount of saving circuit.
The technical scheme that the present invention takes is: first design a kind of novel simple data selector uMUX that is applicable to four edge triggered flip flops; Then design four novel edge triggered flip flop QETFF with it.
Described novel simple data selector uMUX should comprise following technical characterictic:
A, it has one to select control signal TCLK, is that a value is 0,1 and 2 ternary (digital) signal;
B, this new types of data selector uMUX have two data input pin D
0/2and D
1, and a data output end Y;
C, in the time that three values select control signal TCLK to get 0 or 2, this new types of data selector uMUX gated data input D
0/2and close D
1; In the time that three values select control signal TCLK to get 1, gated data input D
1and close D
0/2;
D, for realizing C, need select the level 0 of control signal TCLK be converted to 2 three values, and in the time that three values select control signal TCLK to be 2, maintenance 2 be constant, and in the time that three values selection control signal TCLK are 1, need be converted to 01; So just can 2 and 0 remove to control the gating of two data input pins and close with what obtain after conversion.
E, according to the transmission voltage switching theorem in the functional requirement of D and document [2,3], can create the alternative data selector uMUX that selects control signal TCLK based on three values.
In the circuit structure of four edge triggered flip flops in document [1], available newly-designed alternative data selector uMUX removes to replace original one-out-three data selector MUX, so just obtains the new four edge triggered flip flop QETFF of the invention.New four edge triggered flip flop QETFF have eliminated redundant data input, have reduced the complexity of circuit.Newly-designed four edge triggered flip flop QETFF have saved the use amount of 8 metal-oxide-semiconductors than four edge triggered flip flops in document [1].And because two passage path corresponding to two data input pins of new data selector uMUX are only all a cmos transmission gate, so its critical path than the shortening of one-out-three data selector MUX half.Correspondingly, the critical data outgoing route of newly-designed four edge triggered flip flop QETFF from data input pin to output also reduced half, and its data outgoing route length has advantages of homogeneity.
Brief description of the drawings is described in further detail the present invention below in conjunction with the drawings and specific embodiments.
Fig. 1 is the line map of selecting the alternative data selector uMUX of control signal TCLK based on three values.
Fig. 2 is the symbol of selecting the alternative data selector uMUX of control signal TCLK based on three values.
Fig. 3 is the structure chart that adopts the four edge triggered flip flop QETFF of new types of data selector uMUX.
Fig. 4 is the two-value four edge triggered flip flop circuit diagrams of the invention.
Fig. 5 is the three value four edge triggered flip flop circuit diagrams of the invention.
Fig. 6 is the voltage transient oscillogram of ternary clock TCLK, two-value input signal D and two value output signal Q in circuit shown in Fig. 4.
Fig. 7 is the voltage transient oscillogram of ternary clock TCLK, three value input signal D and three value output signal Q in circuit shown in Fig. 5.
Embodiment, according to technical scheme of the present invention, can create the alternative data selector uMUX based on three values selection control signal TCLK as shown in Figure 1.The operation principle of this data selector uMUX is: first utilize three values of input to select control signal TCLK to produce two data input pin D
0/2and D
1gating and the control signal of closing: in the time of TCLK=0 or 2, the node a output 2 in Fig. 1, node b output 0, like this with regard to gating data input pin D
0/2and close D
1; In the time of TCLK=1, node a in Fig. 1 output 0, node b output 2, like this with regard to gating data input pin D
1and close D
0/2.As can be seen from Figure 1, two data input pin D
0/2and D
1corresponding passage path from input to output is all a transmission gate, therefore the individual channel path of this data selector uMUX is identical, so also just eliminate the problem that affects four edge triggered flip flop stabilities, and its critical path is 1 transmission gate, subtracts and be a half than original one-out-three data selector MUX.
In four edge triggered flip flops of document [1], remove to replace original one-out-three data selector with this new types of data selector uMUX, the four edge triggered flip flop QETFF that get final product novelly, its circuit structure is as shown in Figure 2.Because the M1 in Fig. 2 and two alternative data selector uMUX of M2 are with feedback, so alternative data selector M1 and M2 have formed respectively latch 1 and latch 2.The operation principle of these novel four edge triggered flip flop QETFF is: 1. in the time that ternary clock TCLK jumps to 0 or 2 from 1, latch 1 is converted to store status from input state, its storing value is the data D of latch 1 last input in the time of input state, be the D value of moment before saltus step, this storing value is exported by the uMUX gating under TCLK=1 controls that is labeled as S as flip-flop states; Meanwhile, latch 2 is converted to input state from store status, and its output valve is shielded by uMUX S.Therefore, trigger is subject to the triggering of clock 0 → 1 and 2 → 1 saltus steps, in all new states more of twice saltus step place.2. in the time that TCLK jumps to 1 from 0 or 2, latch 1 and latch 2 exchange the course of work, the output of uMUX S gating latch 2 under the effect of CLK=0 or 2 and the output of shielding lock storage 1.At this twice clock saltus step place trigger also new states more all.As can be seen here, in four saltus steps place of ternary clock one-period, four edge triggered flip flop QETFF of the present invention are with the same state transitions of can carrying out of four edge triggered flip flops of prior art.And in the QETFF of the invention, do not have unnecessary data input pin and the problem of respective channels thereof, thereby reduce the complexity of circuit.Because the selection control signal of new-create four edge triggered flip flop QETFF three uMUX used is all same ternary clock TCLK, so three uMUX can share the circuit module (this module is the circuit in dotted line frame in Fig. 1) of a processing clock, new like this 20 metal-oxide-semiconductors for four edge triggered flip flop QETFF, and 28 metal-oxide-semiconductors for existing four edge triggered flip flops
[1], therefore, the present invention has saved the use amount of 8 metal-oxide-semiconductors.
Because uMUX does not have shaping feature, therefore when for latch, must export reshaper of termination to recover the signal of latch at it.For this point, four edge triggered flip flop QETFF of the present invention are the same with existing four edge triggered flip flops.Due to the path of uMUX from input to output be one can transmission of analogue signal cmos transmission gate, therefore the base value of the reshaper that connects is just determining the base value of four edge triggered flip flops, if connect R value reshaper, just trigger is R value trigger so.For example, when reshaper be two not gates of series connection form two-value reshaper time, trigger is just two-value four edge triggered flip flops as shown in Figure 4; When reshaper is the three value reshapers that are made up of 8 metal-oxide-semiconductors
[2,3,4]time, trigger is just three value four edge triggered flip flops as shown in Figure 5.
For two-value and three value four edge triggered flip flops of checking the invention, with HSPICE, it is simulated below, when simulation, adopt the CMOS technological parameter of 180nm, output loading is 30fF.As shown in Figure 6, wherein TCLK, D and Q are respectively the output waveform of ternary clock, two-value input signal and trigger to the transient waveform of two-value four edge triggered flip flop simulation gained of the present invention.The analog result of Fig. 6 shows, four edge triggered flip flops of the two-value based on ternary clock of the present invention's design have correct logic function.As shown in Figure 7, wherein TCLK, D and Q are respectively three value output waveforms of ternary clock, three value input signals and trigger to the transient waveform of three value four edge triggered flip flop simulation gained.The analog result of Fig. 7 also shows, three value four edge triggered flip flops based on ternary clock of the present invention's design also have correct logic function.
Sum up: the present invention is ensureing that newly-designed four edge triggered flip flop QETFF have under the prerequisite of correct logic function, reduce the complexity of circuit, use 8 metal-oxide-semiconductors with prior art than few, but also improve the performance of circuit: crucial data outgoing route has shortened the length homogeneous of half and pieces of data outgoing route, has improved the stability of circuit engineering parameter.
Claims (2)
1. the CMOS tetra-edge triggered flip flop QETFF based on ternary clock, this trigger is mainly made up of data selector, it is characterized in that: the data selector using is the alternative data selector (uMUX) of one based on three values selection control signals (TCLK).
2. CMOS tetra-edge triggered flip flop QETFF according to claim 1, what it used selects the alternative data selector (uMUX) of control signal (TCLK) to be characterised in that based on three values: this data selector only has two data input pin (D
0/2) and (D
1); In the time that three values select the level value of control signal (TCLK) to be 0 or 2, data input pin (D
0/2) gating and data input pin (D
1) close; And in the time that three values select the level value of control signal (TCLK) to be 1, data input pin (D
1) gating and data input pin (D
0/2) close.
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| CN201310284373.1A CN104038184B (en) | 2013-07-03 | 2013-07-03 | A kind of QETFF circuit unit based on CMOS technology |
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|---|---|---|---|
| CN201310284373.1A CN104038184B (en) | 2013-07-03 | 2013-07-03 | A kind of QETFF circuit unit based on CMOS technology |
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| CN104038184B CN104038184B (en) | 2016-10-05 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104467809A (en) * | 2014-11-14 | 2015-03-25 | 浙江工商大学 | SIXETFF circuit unit formed by novel MUX |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101197561A (en) * | 2007-12-27 | 2008-06-11 | 复旦大学 | Flip-flop circuit with multiple configurations |
| US20080270861A1 (en) * | 2006-03-14 | 2008-10-30 | Lackey David E | Negative edge flip-flops for muxscan and edge clock compatible lssd |
-
2013
- 2013-07-03 CN CN201310284373.1A patent/CN104038184B/en not_active Expired - Fee Related
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20080270861A1 (en) * | 2006-03-14 | 2008-10-30 | Lackey David E | Negative edge flip-flops for muxscan and edge clock compatible lssd |
| CN101197561A (en) * | 2007-12-27 | 2008-06-11 | 复旦大学 | Flip-flop circuit with multiple configurations |
Non-Patent Citations (2)
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| 胡俊锋等: "多值低功耗双边沿触发器设计", 《浙江大学学报（工学版）》 * |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104467809A (en) * | 2014-11-14 | 2015-03-25 | 浙江工商大学 | SIXETFF circuit unit formed by novel MUX |
| CN104467809B (en) * | 2014-11-14 | 2017-08-01 | 浙江工商大学 | Six edge triggered flip flops of odd and even data selector composition |
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| CN104038184B (en) | 2016-10-05 |
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Inventor after: Xu Zhenwei Inventor after: Wang Xiuping Inventor before: Lang Yanfeng |
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