CN103985667A - Electrical connection structure and preparation method thereof - Google Patents

Electrical connection structure and preparation method thereof Download PDF

Info

Publication number
CN103985667A
CN103985667A CN201310556722.0A CN201310556722A CN103985667A CN 103985667 A CN103985667 A CN 103985667A CN 201310556722 A CN201310556722 A CN 201310556722A CN 103985667 A CN103985667 A CN 103985667A
Authority
CN
China
Prior art keywords
copper
substrate
composition surface
film
face
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201310556722.0A
Other languages
Chinese (zh)
Other versions
CN103985667B (en
Inventor
陈智
刘道奇
黄以撒
刘健民
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
National Yang Ming Chiao Tung University NYCU
Original Assignee
National Chiao Tung University NCTU
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by National Chiao Tung University NCTU filed Critical National Chiao Tung University NCTU
Publication of CN103985667A publication Critical patent/CN103985667A/en
Application granted granted Critical
Publication of CN103985667B publication Critical patent/CN103985667B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204Conductive materials
    • H01L23/53209Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53228Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • H01L24/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B23MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23KSOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K1/00Soldering, e.g. brazing, or unsoldering
    • B23K1/0008Soldering, e.g. brazing, or unsoldering specially adapted for particular articles or work
    • B23K1/0016Brazing of electronic components
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/03Manufacturing methods
    • H01L2224/038Post-treatment of the bonding area
    • H01L2224/0382Applying permanent coating, e.g. in-situ coating
    • H01L2224/03826Physical vapour deposition [PVD], e.g. evaporation, or sputtering
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04026Bonding areas specifically adapted for layer connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/0556Disposition
    • H01L2224/05568Disposition the whole external layer protruding from the surface
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/05599Material
    • H01L2224/056Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05663Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05666Titanium [Ti] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods
    • H01L2224/114Manufacturing methods by blanket deposition of the material of the bump connector
    • H01L2224/1146Plating
    • H01L2224/11462Electroplating
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13005Structure
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/1302Disposition
    • H01L2224/13023Disposition the whole bump connector protruding from the surface
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • H01L2224/131Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13117Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/13124Aluminium [Al] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • H01L2224/131Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13139Silver [Ag] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • H01L2224/131Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13144Gold [Au] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • H01L2224/131Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13147Copper [Cu] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • H01L2224/131Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13155Nickel [Ni] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • H01L2224/131Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13163Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/13164Palladium [Pd] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • H01L2224/131Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13163Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/13169Platinum [Pt] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16135Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/27Manufacturing methods
    • H01L2224/274Manufacturing methods by blanket deposition of the material of the layer connector
    • H01L2224/2746Plating
    • H01L2224/27462Electroplating
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/29005Structure
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/2902Disposition
    • H01L2224/29023Disposition the whole layer connector protruding from the surface
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/29099Material
    • H01L2224/291Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29117Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/29124Aluminium [Al] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/29099Material
    • H01L2224/291Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/29139Silver [Ag] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/29099Material
    • H01L2224/291Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/29144Gold [Au] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/29099Material
    • H01L2224/291Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/29147Copper [Cu] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/29099Material
    • H01L2224/291Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/29155Nickel [Ni] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/29099Material
    • H01L2224/291Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29163Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/29164Palladium [Pd] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/29099Material
    • H01L2224/291Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29163Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/29169Platinum [Pt] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32135Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/75Apparatus for connecting with bump connectors or layer connectors
    • H01L2224/7525Means for applying energy, e.g. heating means
    • H01L2224/75272Oven
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/75Apparatus for connecting with bump connectors or layer connectors
    • H01L2224/757Means for aligning
    • H01L2224/75703Mechanical holding means
    • H01L2224/75704Mechanical holding means in the lower part of the bonding apparatus, e.g. in the apparatus chuck
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/75Apparatus for connecting with bump connectors or layer connectors
    • H01L2224/757Means for aligning
    • H01L2224/75703Mechanical holding means
    • H01L2224/75705Mechanical holding means in the upper part of the bonding apparatus, e.g. in the bonding head
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/81009Pre-treatment of the bump connector or the bonding area
    • H01L2224/8101Cleaning the bump connector, e.g. oxide removal step, desmearing
    • H01L2224/81011Chemical cleaning, e.g. etching, flux
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/81053Bonding environment
    • H01L2224/8109Vacuum
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/81053Bonding environment
    • H01L2224/81095Temperature settings
    • H01L2224/81096Transient conditions
    • H01L2224/81097Heating
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119Arrangement of the bump connectors prior to mounting
    • H01L2224/81193Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/812Applying energy for connecting
    • H01L2224/81201Compression bonding
    • H01L2224/81203Thermocompression bonding, e.g. diffusion bonding, pressure joining, thermocompression welding or solid-state welding
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/812Applying energy for connecting
    • H01L2224/81201Compression bonding
    • H01L2224/81208Compression bonding applying unidirectional static pressure
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/812Applying energy for connecting
    • H01L2224/8121Applying energy for connecting using a reflow oven
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818Bonding techniques
    • H01L2224/81801Soldering or alloying
    • H01L2224/8182Diffusion bonding
    • H01L2224/8183Solid-solid interdiffusion
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818Bonding techniques
    • H01L2224/81894Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces
    • H01L2224/81895Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces between electrically conductive surfaces, e.g. copper-copper direct bonding, surface activated bonding
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/83009Pre-treatment of the layer connector or the bonding area
    • H01L2224/8301Cleaning the layer connector, e.g. oxide removal step, desmearing
    • H01L2224/83011Chemical cleaning, e.g. etching, flux
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/83053Bonding environment
    • H01L2224/8309Vacuum
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/83053Bonding environment
    • H01L2224/83095Temperature settings
    • H01L2224/83096Transient conditions
    • H01L2224/83097Heating
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319Arrangement of the layer connectors prior to mounting
    • H01L2224/83193Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/832Applying energy for connecting
    • H01L2224/83201Compression bonding
    • H01L2224/83203Thermocompression bonding, e.g. diffusion bonding, pressure joining, thermocompression welding or solid-state welding
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/832Applying energy for connecting
    • H01L2224/83201Compression bonding
    • H01L2224/83208Compression bonding applying unidirectional static pressure
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/832Applying energy for connecting
    • H01L2224/8321Applying energy for connecting using a reflow oven
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838Bonding techniques
    • H01L2224/83801Soldering or alloying
    • H01L2224/8382Diffusion bonding
    • H01L2224/8383Solid-solid interdiffusion
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838Bonding techniques
    • H01L2224/83894Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces
    • H01L2224/83895Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces between electrically conductive surfaces, e.g. copper-copper direct bonding, surface activated bonding
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93Batch processes
    • H01L2224/94Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49866Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • H01L24/03Manufacturing methods
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/11Manufacturing methods
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/27Manufacturing methods

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Mechanical Engineering (AREA)
  • Electroplating Methods And Accessories (AREA)
  • Pressure Welding/Diffusion-Bonding (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

The invention relates to an electrical connection structure for electrically connecting a first substrate and a second substrate and a preparation method thereof, wherein the preparation method comprises the following steps: providing a first substrate and a second substrate, wherein the first substrate is provided with a first copper film, the second substrate is provided with a first metal film, a first joint surface of the first copper film is a joint surface containing a (111) surface, and the first metal film is provided with a second joint surface; and (B) bonding the first copper film and the first metal film to each other to form a contact, wherein a first bonding surface of the first copper film and a second bonding surface of the first metal film correspond to each other.

Description

Electric connection structure and preparation method thereof
Technical field
The invention relates to a kind of electric connection structure and preparation method thereof, espespecially a kind of electric connection structure that three dimensional integrated circuits uses and preparation method thereof that is applicable to.
Background technology
Flourish along with electronic industry, also increases day by day for having little, lightweight, the multi-functional and high performance electronic product demand of volume.In the development of current integrated circuit, for multiple active element and passive component are located on same device, the semiconductor packagings that adopt now, to reach the object of the circuit and the electronic component that hold greater number under limited unit are more.
In base plate for packaging or circuit board stacking, can use scolder or copper film to carry out stacking.When using the copper film made of general copper product to carry out when stacking, because general copper product lattice direction there is no unicity, and the scattered little crystal grain of formation directivity, therefore before engaging, need to carry out to process before multiple as meticulous surface finish and etching, then again the many environment of restriction (as, nitrogen, acid gas) under, carry out hot press, in addition, the temperature of hot press need be carried out under the temperature more than 300 DEG C, and this temperature likely can be destroyed the element in circuit board.In addition, although had report copper film can at room temperature engage, copper surface must be the smooth of atom level, and engage environment must be in the ultra high vacuum of 10-8torr, therefore cannot volume production.
As shown in Figure 1A, in the time that two substrates 11,13 engages with copper film 12,14, if when the composition surface of copper film 12,14 does not have satisfactory flatness, easily produce seam or emptying aperture (as shown in Figure 1B) at joint, and cause production reliability to reduce.
Because electronic industry gets over precision, the contact of product, also toward meticulousr future development, causes the bonding area of contact also relatively to reduce.Meanwhile, for the reliability of improving product, joint technology is also relatively more complicated.Therefore, if can develop a kind of structure and preparation method who reduces technique and prevent joint generation seam, can be applicable in various semiconductor technologies, particularly on three dimensional integrated circuits, with the reliability of improving product, also can reach the object that need not use scolding tin, and can reduce product cost simultaneously.
Summary of the invention
Main purpose of the present invention is to be to provide a kind of electric connection structure, contact (particularly junction) between its two substrates has well then, the seam or the emptying aperture that only have minority, even do not have seam or hole, and be not easy to produce the situation of contact fracture.
Another object of the present invention is the preparation method who is to provide a kind of electric connection structure, can produce the electric connection structure with height production reliability.
For reaching above-mentioned purpose, of the present invention in order to be electrically connected the preparation method of electric connection structure of a first substrate and a second substrate, comprise the following steps: that (A) provides a first substrate and a second substrate, wherein first substrate is provided with one first copper film, second substrate is provided with one first metal film, one first composition surface of the first copper film is a composition surface containing (111) face, and this first metal film has one second composition surface; And (B) the first copper film and the first metal film are bonded with each other to form a contact, wherein the first composition surface of the first copper film and the second composition surface of the first metal film are mutually corresponding.
By above-mentioned preparation method, of the present invention in order to be electrically connected the electric connection structure of a first substrate and a second substrate, comprising: a first substrate; One second substrate; An and contact, be located between first substrate and second substrate, wherein this contact is bonded with each other and is formed by one first copper film and one first metal film, and junction between the first copper film and the first metal film comprises multiple crystal grain, and this crystal grain is along stacking the forming of [111] crystalline axis direction.
In the present invention, the first copper film using has height [111] preferred orientations, and this preferred orientations has the highest self diffusion velocity, and its composition surface containing (111) face has the highest face bulk density.At this, need be ben, in preparation method provided by the present invention, only must there is [111] preferred orientations by the first copper film, and another one can be copper film or other different metal materials without any preferred orientations, can form seam or the emptying aperture of minority, even there is no the contact of seam or hole; Even if the first copper film is polycrystalline copper and the first metal film is polycrystalline copper or other different metal materials, also can reach this effect.Its reason is, for example, when at least one copper film with (111) composition surface (is formed to substrate, semiconductor chip or circuit substrate etc.) upper using as being electrically connected medium, because of regularly arranged in (111) composition surface place copper crystal lattice direction, therefore only at low temperatures by simple process for pressing, be also not easy to joint and produce seam or emptying aperture.
In addition, by the prepared electric connection structure of preparation method of the present invention, the joint (, junction) between the first copper film and the first metal film can form the grainiess with [111] preferred orientations, and completely engage and seamless.Because the contact between the first substrate and the second substrate that engage is without seam, therefore can reduce the risk of contact fracture, lift element reliability and useful life, and retained high conductivity and the high-cooling property of copper simultaneously.Particularly, with the prepared electric connection structure of preparation method of the present invention, copper is engaged with different metal materials, still can reach the jointless object of contact.
In the present invention, the material of the first metal film can be identical or different with the first copper film, and be preferably the group that the material of the first metal film selects free gold, silver, platinum, nickel, copper, titanium, aluminium and palladium to form.
In aspect an enforcement of the present invention, the first metal film is one second copper film.Wherein, the material of the first copper film and the second copper film there is no particular restriction, as long as wherein one composition surface is the composition surface containing (111) face.For example, the first copper film of the present invention can be composition surface for the copper layer containing the composition surface of (111) face, and the second copper film is polycrystalline copper and without preferred orientations; Or the first copper film of the present invention and the second copper film can be respectively copper layer or the nanometer twin crystal copper layer of composition surface for the composition surface containing (111) face.No matter be copper layer (comprising polycrystalline copper layer) or nanometer twin crystal copper layer, after engaging, joint (junction) is formed with along the stacking multiple crystal grain that form of [111] crystalline axis direction.Be preferably, this little crystal grain is columnar grain.In the present invention, so-called " (111) face " refers to: in copper film, the normal vector of (111) face of multiple copper crystal grain and the angle of the normal vector on composition surface are in 15 degree.Under the prerequisite of this definition, " containing the composition surface of (111) face " refers to that the gross area of 40-100% is (111) face taking this gross area containing the composition surface of (111) face as benchmark; The gross area that is preferably 50-100% is (111) face; The gross area that is more preferred from 60-100% is (111) face.If when the first copper film of the present invention and the second copper film are nanometer twin crystal copper layer, more than 50% volume that is preferably nanometer twin crystal copper layer comprises multiple crystal grain.Can promote the deelectric transferred ability of copper film due to the twin crystal arrangement of nanometer twin crystal copper, and then increase the reliability of product, and be specially adapted in the making of integrated circuit.
In aspect an enforcement of the present invention, the material of the first metal film can be gold, silver, platinum, nickel, titanium, aluminium, palladium or its alloy.Now, the material of the first copper film and composition surface thereof as hereinbefore, therefore do not repeat them here.
In the preparation method of electric connection structure of the present invention, can also comprise a step (A ') step (A) is front: clean the first composition surface of the first copper film and the second composition surface of the first metal film, to remove oxide or other impurity.Particularly, use acid solution (as: hydrochloric acid) to clean the first composition surface of the first copper film and the second composition surface of the first metal film.In addition, in the preparation method of electric connection structure of the present invention, in step (B), the device engaging there is no particular restriction, can be the conventional technology of the art, as engaged with fixture.In addition, more can be by pressuring method so that the first copper film and the first metal film be bonded with each other.Wherein, the pressure of pressurization there is no particular restriction, is preferably low-pressure, according to appointment 1.5-5kg/cm 2.
In addition, in the preparation method of electric connection structure of the present invention, in step (B), can under heating up, engage, wherein junction temperature there is no particular restriction, as long as can do not affect two substrates structure be issued to engage object, for example can under the low temperature of 100-400 DEG C, engage; And preferably by pressurization and at the temperature of 150-300 DEG C, so that the first copper film and the first metal film are bonded with each other.At this, the temperature of the joint of step (B) is preferably 150-400 DEG C; Be more preferred from 150-250 DEG C.In addition, engaging time there is no particular restriction, as long as two substrates can be completed to joint, and for example reducible 0.1-5 hour, and preferred about 0.1-1.5 hour.
In the preparation method of electric connection structure of the present invention, in step (B), can under rough vacuum, the first copper film and the first metal film be bonded with each other.Be preferably, rough vacuum is 1-10 -3torr.
In the preparation method of electric connection structure of the present invention, in the time engaging, the composition surface of the first copper film is (111) face.(111) mask has higher diffusion rate and the surface can be lower, and is face-centered cubic (FCC) closest packing face, therefore can easily reach without seam and engage.Be no matter using polycrystalline copper or nanometer twin crystal copper as membrane material, as long as the first composition surface has (111) preferred orientations, can simply first surface, composition surface can be engaged by polishing step, and also can reach the contact that little seam engages.Utilize copper atom fast especially in (111) diffusion into the surface speed, can be at 200 DEG C to be issued to the effect of fine joint.Accordingly, and can reduce joint environmental limit, and without using the board of apparatus expensive, production cost also thereby can decline to a great extent.
In electric connection structure of the present invention and preparation method thereof, the crystal grain of nanometer twin crystal copper is column bicrystal (columnar twinned grain).In addition, multiple crystal grain is connected to each other to each other, and this each crystal grain is by multiple nanometer twin crystal copper along stacking the forming of [111] crystalline axis direction, and the angle of this adjacent intercrystalline stacking direction is 0 to 20 degree.
In addition,, in the preparation method of electric connection structure of the present invention, can be direct current electrode position or pulse plating as the nanometer twin crystal copper that contains (111) face of the first copper film and the second copper film material or the formation method of polycrystalline copper.Be preferably, form the nanometer twin crystal copper or the polycrystalline copper that contain (111) face with following method: provide an electroplanting device, this electroplanting device comprises an anode, a negative electrode, an electroplate liquid and a supply of electric power source, supply of electric power source is connected with anode and negative electrode respectively, and anode and negative electrode are to be soaked in this electroplate liquid; And use supply of electric power source to provide electric power to electroplate, by a surperficial growth nanometer twin crystal copper layer of negative electrode.At this, the electroplate liquid using can include: salt, an acid and the chloride ion source of a bronze medal.
In above-mentioned electroplate liquid, one of chloride ion major function is can be in order to inching crystal grain-growth direction, makes copper layer (particularly twin crystal copper layer) have crystallization preferred orientations.In addition, its acid can be an organic or inorganic acid, improves electroplating velocity to increase electrolyte concentration, for example, can use sulfuric acid, pyrovinic acid or its mixing, and in addition, the sour concentration in electroplate liquid preferably can be 80-120g/L.In addition, electroplate liquid need include copper ion source (namely, the salt of copper, for example, copper sulphate or copper methanesulfonate) simultaneously.During this electroplate liquid preferably forms, also can also comprise an additive choosing freely: the group that gelatin (gelatin), interfacial agent, lattice conditioner (1attice modification agent) and mixing thereof form, can be with becoming to have [111] preferred orientations with inching crystal grain-growth in order to adjust these a little materials that add.
At this, the supply of electric power source of electroplanting device preferably direct current electroplates that source of supply or high-speed pulse are electroplated source of supply or direct current electrode position is electroplated the two mutual use for it with high-speed pulse, can make metal level form speed lifting.In the time using direct current to electroplate source of supply in this step (B), current density preferably can be 1-12ASD, and the best can be 2-10ASD (for example, 8ASD).In the time using high-speed pulse to electroplate source of supply in this step (B), its operating condition is preferably: T on/ T off(sec) be (for example, 0.1/2,0.1/1 or 0.1/0.5) between 0.1/2-0.1/0.5, current density is 1-25ASD (the best can be 5ASD).Electroplate with this understanding, the growth rate of copper layer, to calculate actual conduction time, preferably can be 0.22-2.64 μ m/min.For example, in the time that the current density of electroplating is 8ASD, the growth rate of metal level can for example, to 1.5-2 μ m/min (, 1.76 μ m/min).In the present invention, the thickness of copper layer can be adjusted according to electroplating time length, and its scope is preferably about 0.1-500 μ m, is more preferred from 0.8-200 μ m, and the best is 1-20 μ m.
Particularly, the obtained twin crystal copper metal layer with preferred orientations of prior art is without filling perforation, and volume production thickness only can reach approximately 0.1 μ m, therefore only can be used as crystal seed layer and uses, and cannot directly apply to as wire part.But, can reach 0.1-500 μ m with the thickness of the prepared electroplating nano twin crystal of preceding method of the present invention copper layer, and can directly be coated in the opening or groove of dielectric layer, and can be applicable in the line layer making of circuit board of the present invention.
In addition,, in the time that plating is carried out, the rotating speed rotation that this negative electrode or this electroplate liquid can 50-1500rpm, to help crystal grain-growth direction and speed.By suitable plating condition, the diameter of the crystal grain of the nanometer twin crystal copper layer of gained of the present invention preferably can be 0.1-50 μ m, the better 1-10 μ m that can be; Die thickness preferably can be 0.01-500 μ m, the better 0.1-200 μ m that can be.
In addition,, in electric connection structure of the present invention and preparation method thereof, first substrate and second substrate can be independently semiconductor chip, a base plate for packaging or a circuit board separately; And be preferably semiconductor chip.Accordingly, technology of the present invention can be applicable to, for example chip package (Flip chip), wafer engage (wafer bonding), wafer stage chip encapsulation (wafer level chip scale packaging, etc. WLCSP) be common in the various encapsulation technologies that IBM C4 technology derived especially high frequency and high-power components.Particularly, technology of the present invention more can be applicable to need on the three dimensional integrated circuits of high engineering properties and production reliability.For example, in the time that first substrate and second substrate are semiconductor chip, after engaging, can form so-called three dimensional integrated circuits (3D-IC); In addition, also can be using three dimensional integrated circuits as first substrate, and base plate for packaging engages as second substrate.At this, only in order to the use of giving an example, but not in order to limit the present invention.
Brief description of the drawings
Figure 1A is existing contact point structure schematic diagram.
Figure 1B is the joint enlarged diagram of existing contact point structure.
Fig. 2 A to Fig. 2 C is the preparation flow generalized section of the electric connection structure with twin crystal copper of the embodiment of the present invention 1.
Fig. 3 be the embodiment of the present invention 1 in order to form the electroplanting device schematic diagram of copper film.
Fig. 4 is the electronics backscattering diffraction vertical view of the copper layer of the embodiment of the present invention 1.
Fig. 5 A to Fig. 5 B is respectively focused ion beam profile and the schematic perspective view of the nanometer twin crystal copper of the embodiment of the present invention 1.
Fig. 6 is the focused ion beam profile of the joint of the electric connection structure of the embodiment of the present invention 1.
Fig. 7 A to Fig. 7 B is the preparation flow generalized section of the electric connection structure with twin crystal copper of the embodiment of the present invention 2.
Fig. 8 A to Fig. 8 C is the preparation flow generalized section of the electric connection structure forming with copper layer of the embodiment of the present invention 3.
Fig. 9 is the electronics backscattering diffraction vertical view of the copper layer of the embodiment of the present invention 3.
Figure 10 is the section light field image of the transmission electron microscope of the copper layer of the embodiment of the present invention 3.
Figure 11 is the high-resolution transmission electron microscope image of the joint of the electric connection structure of the embodiment of the present invention 3.
Figure 12 is the section light field image of the transmission electron microscope of the joint of the electric connection structure of the embodiment of the present invention 3.
Figure 13 is the focused ion beam profile of the joint of the electric connection structure of the embodiment of the present invention 4.
Figure 14 is the light field cross-sectional images of the transmission electron microscope of the joint of the electric connection structure of the embodiment of the present invention 5.
Figure 15 is the light field image of the transmission electron microscope of the joint of the electric connection structure of the embodiment of the present invention 6.
Figure 16 is the light field cross-sectional images of the transmission electron microscope of the joint of the electric connection structure of the embodiment of the present invention 7.
Figure 17 is the electronics backscattering diffraction vertical view of the copper layer that contains 64% (111) surface of the embodiment of the present invention 8.
Figure 18 is the light field cross-sectional images of the transmission electron microscope of the joint of the electric connection structure of the embodiment of the present invention 8.
Figure 19 is the focused ion beam profile of the joint of the electric connection structure of the embodiment of the present invention 9.
[symbol description]
11,13 tomb plate 12,14 copper films
21 first substrate 221 first following layers
22 first copper film 221 first composition surfaces
23 second substrate 231 second following layers
24 second copper film 241 second composition surfaces
25 contact 261,262 fixtures
27 gold medal film 3 electroplanting devices
32 anode 34 electroplate liquids
36 direct current source of supply 41 columnar grains
411 interior meter Shuan Jing plane 412 crystal boundaries
D diameter T thickness
Embodiment
By particular specific embodiment, embodiments of the present invention are described below, those skilled in the art can understand other advantages of the present invention and effect easily by content disclosed in the present specification.The present invention also can be implemented or be applied by other different specific embodiments, and the every details in this specification also can be based on different viewpoints and application, carries out various modifications and change not deviating under spirit of the present invention.
Embodiment 1
The preparation flow generalized section of the electric connection structure with twin crystal copper that Fig. 2 A to Fig. 2 C is the present embodiment.Fig. 3 be the present embodiment in order to form the electroplanting device schematic diagram of copper film.Fig. 4 is the electronics backscattering diffraction vertical view of the copper layer of the present embodiment, and the ratio of (111) face is 100%.Fig. 5 A and 5B are respectively focused ion beam (FIB) profile and the schematic perspective view of the nanometer twin crystal copper layer of the present embodiment.
As shown in Figure 2 A, first provide a first substrate 21, and first substrate 21 is a wafer.At this, illustrate for simplicity, only represent the structure of first substrate 21 with schematic diagram, its circuit, active element, passive component or other parts are not disclosed in accompanying drawing.
Then, use electroplanting device as shown in Figure 3, first substrate 21 is electroplated.As shown in Figure 3, first substrate 21 is placed in to an electroplanting device 3 as negative electrode; Wherein, this electroplanting device 3 includes anode 32, is soaked in electroplate liquid 34 and is connected to a direct current source of supply 36 (being to use Keithley2400 at this).The material that anode 32 uses can be metallic copper, phosphor-copper or inert anode (as titanium lily gilding); In the present embodiment, the material that anode 32 uses is metallic copper.In addition, electroplate liquid 34 includes copper sulphate (copper ion concentration is 20-60g/L), chloride ion (concentration is 10-100ppm) and pyrovinic acid (concentration is 80-120g/L), and can add other interfacial agents or lattice conditioner (as BASF Lugalvan1-100ml/L).Optionally, the electroplate liquid 34 of the present embodiment more can comprise organic acid (for example, pyrovinic acid), gelatin (gelatin) or above mixture, in order to adjust grainiess and size.
Then, electroplate with the direct current of the current density of 2-10ASD, started towards the direction (as shown in Figure 3) of arrow indication first copper films 22 of growing up on first substrate 21 surfaces, as shown in Figure 2 A by first substrate 21.In developmental process, (111) face of twin crystal and the plane of the first copper film 22 be approximately perpendicular to the direction of electric field, and with the speed growth twin crystal copper of approximately 1.76 μ m/min; More specifically, the first copper film 22 (, nanometer twin crystal copper layer) is along vertical (111) direction, and parallel electric field direction is grown up.
First copper film 22 of having grown up includes multiple twin crystal copper crystal grain, and this twin crystal copper crystal grain is made up of multiple twin crystal copper, and this nanometer twin crystal copper crystal grain extends to surface, and what therefore the first copper film 22 surfaces appeared is (111) face equally.The first copper film 22 thickness approximately 5~20 μ m that obtain after plating completes, and [111] crystallographic axis is the axle of vertical (111) face, the ratio of (111) face is 100%.Then, first substrate 21 is taken out from electroplanting device, can obtain the first substrate 21 that top is formed with the first copper film 22, and the first copper film 22 is nanometer twin crystal copper layer, and its first composition surface 221 is (111) face, (111) ratio of face is 100%, and as shown in electronics backscattering diffraction (EBSD) vertical view of Fig. 4, its Oxford gray part area is (111) face.
At this, refer to Fig. 5 A and Fig. 5 B, it is respectively focused ion beam (FIB) profile and the schematic perspective view of the nanometer twin crystal copper layer of conduct the first copper film that the present embodiment forms.As shown in Figure 5A, more than 50% volume of the nanometer twin crystal copper layer of the present embodiment includes multiple columnar grains 41, and in each crystal grain, have multiple laminar nano twin crystal copper (for example, adjacent one group of black line and white line form a twin crystal copper, with stacking direction 42 stacking and form crystal grain 41, as shown in Figure 5 B).Therefore in the present invention, nanometer twin crystal copper layer entirety includes very many nanometer twin crystal copper.The scope of the diameter D of these a little columnar grains 41 is about 0.5 μ m to 8 μ m and height L is about 2 μ m to 20 μ m, nano double Jinping face 411 (horizontal stripe) and (111) plane parallel, twin crystal intercrystalline is crystal boundary 412, (111) plane of copper is perpendicular to thickness T direction, and the thickness T of twin crystal copper layer is about 20 μ m (can adjust arbitrarily between 0.1 μ m-500 μ m).The angle of adjacent this intercrystalline stacking direction (being almost equal to [111] crystallographic axis) is in 0 to 20 degree.
Then, refer to Fig. 2 B, a second substrate 23 is provided, and second substrate 23 is also a wafer.Same, illustrate for simplicity, only represent the structure of second substrate 23 with schematic diagram, its circuit, active element, passive component or other parts are not disclosed in accompanying drawing.
Meanwhile, use the electro-plating method identical with forming the first copper film 22, to form the second copper film 24 on second substrate 23, its thickness approximately 5~20 μ m, and [111] crystallographic axis is the axle of vertical (111) face.Therefore, the second copper film 24 is nanometer twin crystal copper layer, and its second composition surface 241 is also (111) face.At this, nanometer twin crystal copper layer and first copper film 22 of the second copper film 24 have same structure, therefore do not repeat them here.
After the second composition surface 241 of the first composition surface 221 of the first copper film 22 and the second copper film 24 is cleaned taking aqueous hydrochloric acid solution (volume ratio of hydrochloric acid and deionized water was as 1: 1), respectively first substrate 21 and second substrate 23 are placed in to fixture 261, on 262, and make the first composition surface 221 relative with the second composition surface 241.Then, be placed in vacuum boiler tube, with 10 -3the rough vacuum of torr, is warming up to 200 DEG C by boiler tube and engages and anneal 1 hour, suitably adjusts moulding pressure between joint aging time, can maintain the twin crystal structure of the first copper film 22 and the second copper film 24 and joint thereof.
Via above-mentioned technique, as shown in Figure 2 C, can obtain the electric connection structure with twin crystal copper of the present embodiment, it comprises: a first substrate 21; One second substrate 23; And contact 25, be located between first substrate 21 and second substrate 23, wherein contact 25 is to be bonded with each other and to be formed by one first copper film 22 and one second copper film 24, and the material of contact 25 is nanometer twin crystal copper layer, and more than 50% volume of this nanometer twin crystal copper layer comprises multiple crystal grain.Wherein, the first copper film 22 forms contact 25 with the second copper film 24 after engaging, and its joint is represented by dotted lines.
Fig. 6 is the focused ion beam profile of the joint of the electric connection structure with twin crystal copper of the present embodiment; This result shows, using (111) face during as composition surface, and contact 25 its joints that the first copper film 22 and the second copper film 24 form there are no seam.
Embodiment 2
The preparation flow generalized section of the electric connection structure with twin crystal copper that Fig. 7 A to Fig. 7 B is the present embodiment.
As shown in Fig. 7 A and Fig. 7 B, in the present embodiment, on first substrate 21 and second substrate 23, be formed with respectively multiple the first copper films 22 and multiple the second copper film 24.At this, Patternized technique and the same electrical depositing process as described in Example 1 that can arrange in pairs or groups and develop as gold-tinted, to form respectively multiple the first copper films 22 and multiple the second copper film 24 on first substrate 21 and second substrate 23.Wherein, the first copper film 22 and the second copper film 24 comprise respectively multiple twin crystal copper crystal grain, and this twin crystal copper crystal grain is made up of multiple twin crystal copper, and this nanometer twin crystal copper crystal grain extends to surface; And [111] crystallographic axis is the axle of vertical (111) face.Therefore, the first composition surface 221 of the first copper film 22 and the second composition surface 241 of the second copper film 24 are (111) face, and the ratio of (111) face is 100%, and its electronics backscattering diffraction analysis result is identical with Fig. 4 of embodiment 1.
In the present embodiment, first substrate 21 is semiconductor chip with second substrate 23 simultaneously.Same, illustrate for simplicity, only represent the structure of first substrate 21 and second substrate 23 with schematic diagram, its circuit or other parts are not disclosed in accompanying drawing.
With the method identical with embodiment 1, as shown in Figure 7 A, after the second composition surface 241 of the first composition surface 221 of the first copper film 22 and the second copper film 24 is cleaned taking aqueous hydrochloric acid solution (volume ratio of hydrochloric acid and deionized water was as 1: 1), respectively first substrate 21 and second substrate 23 are placed in to fixture 261, on 262, and make the first composition surface 221 relative with the second composition surface 241.Then, be placed in vacuum boiler tube, with 10 -3the rough vacuum of torr, is warming up to 200 DEG C by boiler tube and engages and anneal 10 minutes to 1 hour, suitably adjusts moulding pressure between joint aging time, can maintain the twin crystal structure of the first copper film 22 and the second copper film 24 and joint thereof.
Via above-mentioned technique, as shown in Figure 7 B, can obtain the electric connection structure with twin crystal copper of the present embodiment, it comprises: a first substrate 21; One second substrate 23; And multiple contacts 25, be located between first substrate 21 and second substrate 23, wherein the material of contact 25 is nanometer twin crystal copper, more than 50% volume of this nanometer twin crystal copper comprises multiple crystal grain.Wherein, the first copper film 22 forms contact 25 with the second copper film 24 after engaging, and its joint is represented by dotted lines.
Embodiment 3
The manufacture method with the copper layer of (111) face is on silicon, to utilize the titanium layer (as following layer) that the first deposit thickness of sputter mode is 100nm, the copper layer with (111) face that to utilize afterwards plating mode deposit thickness on titanium layer be 200nm, at this, can use and previously describe identical electroplating technology.In the present embodiment, be use that Ai Keer Adtec Co., Ltd. provides be formed with the silicon with (111) face copper layer.(111) ratio can be controlled by the different knitting layer on silicon, uses titanium can obtain (111) face of 97% as following (adhesion layer) layer at this.
The preparation flow generalized section of the electric connection structure that Fig. 8 A to Fig. 8 C is the present embodiment; Wherein difference from Example 1 is mainly to use the copper layer with the composition surface that front tool comprises 97% (111) face to replace nanometer twin crystal copper layer.
As shown in Figure 8 A, first provide a first substrate 21, it is a silicon substrate, and top is formed with one first following layer 221; Wherein, this first following layer 221 is that a thickness is the titanium coating of 100nm.But first following layer of the present embodiment is only in order to silicon substrate and the follow-up copper layer that formed are thereon had to good bond, can be along with different substrate material difference, and select the following layer of different materials or do not use following layer.In addition, in the present embodiment, illustrate for simplicity, only represent the structure of first substrate 21 with schematic diagram, its circuit, active element, passive component or other parts are not disclosed in accompanying drawing.
Then, the first bronze medal layer 22 of growing up on the first following layer 221 of first substrate 21, this first bronze medal layer 22 is one to have the copper layer for (111) face, and the about 200nm of its thickness.
After analyzing via electronics backscattering diffraction (EBSD), as shown in Figure 9, it is all (111) face that there is more than 97% area on the prepared copper layer surface of the present embodiment, and Dark grey part area is (111) face.In addition, analyze behind the cross section of copper layer via transmission electron microscope (TEM), the prepared copper layer of the present embodiment presents column structure (column crystal), as shown in figure 10.In addition, find through the image analysing computer of X-ray diffraction, the long axis direction of copper layer is [111] direction; And high-resolution transmission electron microscope (HRTEM) image analysing computer also shows that the cross section of copper layer also shows that the prepared copper layer of the present embodiment surface is (111) plane, as shown in figure 11.
Then, refer to Fig. 8 B, a second substrate 23 is provided, it is a silicon substrate, and top is formed with one second following layer 231.Then, the second bronze medal layer 24 of growing up on the second following layer 231 of second substrate 23, this second bronze medal layer 24 is one to have the copper layer for (111) face, and the about 200nm of its thickness.At this, the second following layer 231 is similar to the second bronze medal layer 24 to aforesaid the first following layer 211 respectively to technique, material, thickness and the function of the second bronze medal layer 24, does not therefore repeat them here.In addition, illustrate for simplicity, only represent the structure of second substrate 23 with schematic diagram, its circuit, active element, passive component or other parts are not disclosed in accompanying drawing.
Then, as shown in Figure 8 B, after the second composition surface 241 of the first composition surface 221 of the first bronze medal layer 22 and the second bronze medal layer 24 is cleaned taking aqueous hydrochloric acid solution (volume ratio of hydrochloric acid and deionized water was as 1: 1), respectively first substrate 21 and second substrate 23 are placed in to fixture 261, on 262, and make the first composition surface 221 relative with the second composition surface 241.Then, be placed in vacuum boiler tube, with approximately 10 -3the rough vacuum of torr, is warming up to 200 DEG C by boiler tube and engages and anneal one hour, suitably adjusts moulding pressure (about 3kg/cm between joint aging time 2).
Via above-mentioned technique, as shown in Figure 8 C, can obtain the having of the present embodiment (111) but without the electric connection structure of twin crystal copper, it comprises: a first substrate 21; One second substrate 23; And contact 25, be located between first substrate 21 and second substrate 23, wherein contact 25 is to be bonded with each other and to be formed by one first bronze medal layer 22 and one second bronze medal layer 24, and junction between the first bronze medal layer 22 and the second bronze medal layer 24 has multiple crystal grain, and crystal grain is along stacking the forming of [111] crystalline axis direction.Wherein, the first bronze medal layer 22 forms contact 25 with the second bronze medal layer 24 after engaging, and its joint (, junction) is represented by dotted lines.
The TEM section result of the electric connection structure being formed with copper layer that Figure 12 is the present embodiment; This result shows, though do not use twin crystal copper, after thering is (111) face and engaging as the copper layer on composition surface, joint (, junction) there are no seam and still keep columnar grain structure.Meanwhile, also show that via HRTEM image analysing computer the cross section of copper layer also shows that joint interface is the existence of grain boundary structure and non-oxidation layer, as shown in figure 11.
Embodiment 4
Please also refer to Fig. 8 A to Fig. 8 C, material, making flow process and the structure of the present embodiment are all identical with embodiment 3, except the first bronze medal layer 22 on the first substrate 21 of the present embodiment is one to have the polycrystalline copper layer on (111) face (the first composition surface 221), and its thickness approximately 2 μ m; The second bronze medal layer 24 of second substrate 23 is for not having the copper layer on (111) face (the second composition surface 241), and its thickness approximately 2 μ m.In addition, condition when joint is 10 -3the rough vacuum of torr, the junction temperature of 200 DEG C, the about 4kg/cm of pressure 2, and engaging time is one hour.
Figure 13 is focused ion beam (FIB) profile of the joint of the electric connection structure of the present embodiment.Its result shows, though do not use twin crystal copper and only a composition surface 221 be (111) face, joint (, junction) has had not yet to see seam.
Aforementioned result shows, when use has the highly copper layer of [111] preferred orientations, only need one of them composition surface to there is (111) face, need not be (111) face in two composition surfaces, can be issued to good hot press result at low vacuum, low-pressure and low temperature, and joint interface non-oxidation layer exists.Meanwhile, because junction temperature is lower, the copper layer (, copper layer) after therefore engaging still has the columnar crystal structure of [111] preferred orientations.
Embodiment 5
Please also refer to Fig. 8 to Fig. 8 C, material, making flow process and the structure of the present embodiment are all identical with embodiment 3, except the second copper film 24 of the first copper film 22 on the first substrate 21 of the present embodiment and second substrate 23 is a nanometer twin crystal copper layer, and its first composition surface 221 and the second composition surface 241 are the composition surface (taking the gross area on the first composition surface 221 or the second composition surface 241 as benchmark) of (111) face that contains 97%.In addition, condition when joint is 10 -3the rough vacuum of torr, the junction temperature of 250 DEG C, the about 100psi of pressure, and engaging time is 10 minutes.
The electronics backscattering diffraction analysis figure of the copper layer of the present embodiment is identical with Fig. 9 of embodiment 3, can learn that the first composition surface 221 in the present embodiment and the second composition surface 241 are the composition surface of (111) face that contains 97%, Dark grey part area is (111) face.In addition,, as shown in the light field image of the transmission electron microscope of Figure 14, joint (, junction) has had not yet to see seam, and produces without hole.
Embodiment 6
Material, making flow process and the structure of the present embodiment are all identical with embodiment 5, and the condition during except joint is 10 -3the rough vacuum of torr, the junction temperature of 200 DEG C, the about 100psi of pressure, and engaging time is 30 minutes.As shown in the light field image of the transmission electron microscope of Figure 15, joint (, junction) has had not yet to see seam, and produces without hole.
Embodiment 7
Material, making flow process and the structure of the present embodiment are all identical with embodiment 5, and the condition during except joint is 10 -3the rough vacuum of torr, the junction temperature of 150 DEG C, the about 100psi of pressure, and engaging time is 60 minutes.As shown in the light field image of the transmission electron microscope of Figure 16, joint (, junction) has had not yet to see seam, and produces without hole.
Embodiment 8
Please also refer to Fig. 8 A to Fig. 8 C, material, making flow process and the structure of the present embodiment are all identical with embodiment 3, except the second copper film 24 of the first copper film 22 on the first substrate 21 of the present embodiment and second substrate 23 is a nanometer twin crystal copper layer, and its first composition surface 221 and the second composition surface 241 are the composition surface (taking the gross area on the first composition surface 221 or the second composition surface 241 as benchmark) of (111) face that contains 64%.In addition, condition when joint is 10 -3the rough vacuum of torr, the junction temperature of 200 DEG C, the about 100psi of pressure, and engaging time is 30 minutes.
Figure 17 is the electronics backscattering diffraction analysis figure of the copper layer of the present embodiment, can learn that the first composition surface 221 in the present embodiment and the second composition surface 241 are the composition surface of (111) face that contains 64%, Dark grey part area is (111) face.(111) ratio can be controlled by the different knitting layer on silicon, uses titanium tungsten can obtain (111) face of 64% as following layer at this.In addition,, as shown in the light field image of the transmission electron microscope of Figure 18, joint (, junction) has had not yet to see seam, and produces without hole.
Shown by aforementioned result, when use has the highly copper layer of [111] preferred orientations, even if only have 50% composition surface for (111) face, still can be issued to good hot press result at low vacuum, low-pressure and low temperature, and joint interface produces without seam and hole.Meanwhile, because junction temperature is lower, the copper layer (, copper film) after therefore engaging still has the columnar crystal structure of [111] preferred orientations.
Embodiment 9
Please also refer to Fig. 8 A to Fig. 8 C, material, making flow process and the structure of the present embodiment are all identical with embodiment 1, except the second bronze medal layer 24 of second substrate 23 is replaced with a gold medal film, and second substrate 23 is one to be sequentially laminated with the silicon substrate of silicon dioxide layer and titanium layer.Wherein, gold film is to use FCTD-0056-6Microfab Au100 electroplate liquid (to buy to Electroplating Engineers of Japan Ltd., direct current with the current density of 5ASD under room temperature is electroplated, the golden film that formation thickness is 100nm, this golden film has (220) preferred orientations.In addition, condition when joint is 10 -3the rough vacuum of torr, the junction temperature of 200 DEG C, the about 4kg/cm of pressure 2, and engaging time is one hour.
Figure 19 is focused ion beam (FIB) profile of the joint of the electric connection structure of the present embodiment.As shown in Figure 19 result, have first copper film 22 (nanometer twin crystal copper film) on (111) composition surface and the direct joint interface of golden film 27 and there is no hole and exist, this result confirms nanometer twin crystal copper film and golden film, and direct to engage result quite good.
Shown by aforementioned result, when use has the highly copper layer of [111] preferred orientations, even if the metal level that the first metal film engaging is other dissimilar materialss, still can be issued to good hot press result at low vacuum, low-pressure and low temperature, and joint interface produces without seam and hole.Meanwhile, because junction temperature is lower, the copper layer (, copper film) after therefore engaging still has the columnar crystal structure of [111] preferred orientations.
Above-described embodiment is only to give an example for convenience of description, and the interest field that the present invention advocates should be as the criterion with described in claim certainly, but not only limits to above-described embodiment.

Claims (20)

1. in order to be electrically connected the preparation method of electric connection structure for a first substrate and a second substrate, it is characterized in that, comprise the following steps:
(A) provide a first substrate and a second substrate, wherein this first substrate is provided with one first copper film, this second substrate is provided with one first metal film, one first composition surface of this first copper film is a composition surface containing (111) face, and this first metal film has one second composition surface; And
(B) this first copper film and this first metal film are bonded with each other to form a contact, wherein this first composition surface of this first copper film and this second composition surface of this first metal film are mutually corresponding.
2. preparation method according to claim 1, wherein this first composition surface of this first copper film and this second composition surface of this first metal film are a composition surface containing (111) face.
3. preparation method according to claim 1, wherein this first copper film comprises multiple copper crystal grain with (111) face, be decided to be under the basis of (111) face taking the normal vector of (111) face of this copper crystal grain and the angle of the normal vector on composition surface as 15 degree, contain in the composition surface of (111) face at this, taking this gross area containing the composition surface of (111) face as benchmark, the gross area of 40-100% is (111) face.
4. preparation method according to claim 1, wherein the material of this first metal film selects the group that free gold, silver, platinum, nickel, copper, titanium, aluminium and palladium form.
5. preparation method according to claim 1, wherein this first metal film is one second copper film.
6. preparation method according to claim 5, wherein the material of this first copper film and this second copper film is respectively copper layer or the nanometer twin crystal copper layer that a composition surface is (111) face.
7. preparation method according to claim 1, wherein in the front step (A ') that also comprises of step (A): clean this first composition surface of this first copper film and this second composition surface of this first metal film with acid solution.
8. preparation method according to claim 6, wherein more than 50% volume of this nanometer twin crystal copper layer comprises multiple crystal grain.
9. preparation method according to claim 7, wherein this crystal grain is column bicrystal.
10. preparation method according to claim 8, wherein this crystal grain is connected to each other to each other, this each crystal grain be by multiple nanometer twin crystal copper along stacking the forming of [111] crystalline axis direction, and the angle of this adjacent intercrystalline stacking direction is 0 to 20 degree.
11. preparation methods according to claim 1, in step (B), are wherein so that this first copper film and this first metal film are bonded with each other by pressurization.
12. preparation methods according to claim 1,, in step (B), are wherein at the temperature of 100-400 DEG C, by pressurizeing so that this first copper film and this first metal film are bonded with each other.
13. preparation methods according to claim 1, in step (B), are wherein at 1-10 -3under torr vacuum degree, this first copper film and this first metal film are bonded with each other.
14. 1 kinds in order to be electrically connected the electric connection structure of a first substrate and a second substrate, it is characterized in that, comprising:
One first substrate;
One second substrate; And
One contact, be located between this first substrate and this second substrate, wherein this contact is bonded with each other and is formed by one first copper film and one first metal film, and junction between this first copper film and this first metal film comprises multiple crystal grain, and this crystal grain is along stacking the forming of [111] crystalline axis direction.
15. electric connection structures according to claim 14, wherein this crystal grain is columnar grain.
16. electric connection structures according to claim 14, wherein the material of this first metal film selects the group that free gold, silver, platinum, nickel, copper, titanium, aluminium and palladium form.
17. electric connection structures according to claim 14, wherein the material of this first copper film is copper layer or the nanometer twin crystal copper layer that a composition surface is (111) face.
18. electric connection structures according to claim 17, wherein more than 50% volume of this nanometer twin crystal copper layer comprises multiple crystal grain.
19. electric connection structures according to claim 18, wherein this crystal grain is column bicrystal.
20. electric connection structures according to claim 18, wherein this crystal grain is connected to each other to each other, and this each crystal grain is by multiple nanometer twin crystal copper along stacking the forming of [111] crystalline axis direction, and the angle of this adjacent intercrystalline stacking direction is 0 to 20 degree.
CN201310556722.0A 2013-02-07 2013-11-11 Electrical connection structure and preparation method thereof Active CN103985667B (en)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
TW102104935 2013-02-07
TW102104935 2013-02-07
TW102134714 2013-09-26
TW102134714A TWI490962B (en) 2013-02-07 2013-09-26 Electrical connecting element and method for manufacturing the same

Publications (2)

Publication Number Publication Date
CN103985667A true CN103985667A (en) 2014-08-13
CN103985667B CN103985667B (en) 2017-03-29

Family

ID=51206239

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201310556722.0A Active CN103985667B (en) 2013-02-07 2013-11-11 Electrical connection structure and preparation method thereof

Country Status (4)

Country Link
US (1) US20140217593A1 (en)
CN (1) CN103985667B (en)
DE (1) DE102014101552A1 (en)
TW (1) TWI490962B (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105332020A (en) * 2014-08-14 2016-02-17 财团法人交大思源基金会 Nano-bicrystal gold film, preparation method thereof and bonding structure comprising nano-bicrystal gold film
CN110071051A (en) * 2019-04-30 2019-07-30 德淮半导体有限公司 Chip connection method
CN110164782A (en) * 2018-02-13 2019-08-23 财团法人工业技术研究院 Encapsulating structure and the method for component connection
CN112242311A (en) * 2019-07-19 2021-01-19 财团法人交大思源基金会 Electrical connection structure with nano-twinned copper and method of forming the same
WO2024087373A1 (en) * 2022-07-08 2024-05-02 铂识科技股份有限公司 Bonding structure and manufacturing method therefor

Families Citing this family (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR3006236B1 (en) * 2013-06-03 2016-07-29 Commissariat Energie Atomique DIRECT METAL BONDING PROCESS
FR3009428B1 (en) * 2013-08-05 2015-08-07 Commissariat Energie Atomique METHOD FOR MANUFACTURING SEMICONDUCTOR STRUCTURE WITH TEMPORARY COLLAGE VIA METAL LAYERS
US10020281B2 (en) * 2016-08-30 2018-07-10 International Business Machines Corporation Metal bonding pads for packaging applications
US10217725B2 (en) 2017-02-23 2019-02-26 International Business Machines Corporation Microstructure modulation for metal wafer-wafer bonding
US10141391B2 (en) 2017-02-23 2018-11-27 International Business Machines Corporation Microstructure modulation for 3D bonded semiconductor containing an embedded resistor structure
US10141392B2 (en) 2017-02-23 2018-11-27 International Business Machines Corporation Microstructure modulation for 3D bonded semiconductor structure with an embedded capacitor
TWI709213B (en) * 2018-02-13 2020-11-01 財團法人工業技術研究院 Package structure and method for conecting components
EP3814551A4 (en) * 2018-06-26 2022-01-19 Purdue Research Foundation High-strength single-crystal like nanotwinned nickel coatings and methods of making the same
US11011494B2 (en) * 2018-08-31 2021-05-18 Invensas Bonding Technologies, Inc. Layer structures for making direct metal-to-metal bonds at low temperatures in microelectronics
TWI731293B (en) * 2019-01-18 2021-06-21 元智大學 Nanotwinned structure
US11901585B2 (en) 2019-11-23 2024-02-13 Apple Inc. Nanotwin copper components
TWI709667B (en) 2019-12-06 2020-11-11 添鴻科技股份有限公司 Nano-twinned copper layer, method for manufacturing the same, and substrate comprising the same
US11538756B2 (en) * 2020-09-16 2022-12-27 Advanced Semiconductor Engineering, Inc. Bonding structure and method for manufacturing the same
US11264357B1 (en) 2020-10-20 2022-03-01 Invensas Corporation Mixed exposure for large die
CN116601750A (en) * 2020-12-16 2023-08-15 香港大学 CU-CU direct soldering for packaging applications in the semiconductor industry
CN114975143A (en) 2021-02-22 2022-08-30 联华电子股份有限公司 Semiconductor structure and manufacturing method thereof
TWI746383B (en) * 2021-03-05 2021-11-11 國立陽明交通大學 Nano-twinned copper layer with doped metal element, substrate comprising the same and method for manufacturing the same
US12000030B2 (en) * 2021-05-07 2024-06-04 Apple Inc. Copper alloy film with high strength and high conductivity
TWI762342B (en) * 2021-06-03 2022-04-21 國立臺灣大學 Methods for forming bonding structures
TWI819339B (en) * 2021-07-20 2023-10-21 樂鑫材料科技股份有限公司 Methods for forming bonding structures
TWI789864B (en) * 2021-08-09 2023-01-11 國立陽明交通大學 Electrical connecting structure and method for manufacturing the same
TWI810079B (en) * 2022-06-14 2023-07-21 南亞科技股份有限公司 Semiconductor structure having hybrid bonding pad

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1357157A (en) * 1999-06-22 2002-07-03 日本电气株式会社 Copper wiring
US20050003664A1 (en) * 2003-07-02 2005-01-06 Shriram Ramanathan Method and apparatus for low temperature copper to copper bonding
CN101213076A (en) * 2005-05-31 2008-07-02 德州仪器公司 Solder joints for copper metallization having reduced interfacial voids
US20100291385A1 (en) * 2009-05-13 2010-11-18 California Institute Of Technology Fabrication of vertically aligned metallic nanopillars
CN102400188A (en) * 2010-09-10 2012-04-04 中国科学院金属研究所 (111) texture nano-grade twin crystal Cu block material and preparation method thereof
WO2012117478A1 (en) * 2011-02-28 2012-09-07 三洋電機株式会社 Metal junction structure and metal junction method

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4455214B2 (en) * 2004-08-05 2010-04-21 Necエレクトロニクス株式会社 Semiconductor device and manufacturing method thereof
JP4987823B2 (en) * 2008-08-29 2012-07-25 株式会社東芝 Semiconductor device
US7868449B2 (en) * 2009-05-25 2011-01-11 Freescale Semiconductor, Inc. Semiconductor substrate and method of connecting semiconductor die to substrate
US8330272B2 (en) * 2010-07-08 2012-12-11 Tessera, Inc. Microelectronic packages with dual or multiple-etched flip-chip connectors

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1357157A (en) * 1999-06-22 2002-07-03 日本电气株式会社 Copper wiring
US20050003664A1 (en) * 2003-07-02 2005-01-06 Shriram Ramanathan Method and apparatus for low temperature copper to copper bonding
CN101213076A (en) * 2005-05-31 2008-07-02 德州仪器公司 Solder joints for copper metallization having reduced interfacial voids
US20100291385A1 (en) * 2009-05-13 2010-11-18 California Institute Of Technology Fabrication of vertically aligned metallic nanopillars
CN102400188A (en) * 2010-09-10 2012-04-04 中国科学院金属研究所 (111) texture nano-grade twin crystal Cu block material and preparation method thereof
WO2012117478A1 (en) * 2011-02-28 2012-09-07 三洋電機株式会社 Metal junction structure and metal junction method

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105332020A (en) * 2014-08-14 2016-02-17 财团法人交大思源基金会 Nano-bicrystal gold film, preparation method thereof and bonding structure comprising nano-bicrystal gold film
US9758886B2 (en) 2014-08-14 2017-09-12 National Chiao Tung University Preferably oriented nanotwinned Au film, method of preparing the same, and bonding structure comprising the same
CN105332020B (en) * 2014-08-14 2018-06-29 财团法人交大思源基金会 Nano-bicrystal gold film, preparation method thereof and bonding structure comprising nano-bicrystal gold film
US10161054B2 (en) 2014-08-14 2018-12-25 National Chiao Tung University Preferably oriented nanotwinned Au film, method of preparing the same, and bonding structure comprising the same
CN110164782A (en) * 2018-02-13 2019-08-23 财团法人工业技术研究院 Encapsulating structure and the method for component connection
US11355472B2 (en) 2018-02-13 2022-06-07 Industrial Technology Research Institute Package structure and method for connecting components
CN110071051A (en) * 2019-04-30 2019-07-30 德淮半导体有限公司 Chip connection method
CN112242311A (en) * 2019-07-19 2021-01-19 财团法人交大思源基金会 Electrical connection structure with nano-twinned copper and method of forming the same
WO2024087373A1 (en) * 2022-07-08 2024-05-02 铂识科技股份有限公司 Bonding structure and manufacturing method therefor

Also Published As

Publication number Publication date
TW201432828A (en) 2014-08-16
CN103985667B (en) 2017-03-29
DE102014101552A1 (en) 2014-08-07
US20140217593A1 (en) 2014-08-07
TWI490962B (en) 2015-07-01

Similar Documents

Publication Publication Date Title
CN103985667A (en) Electrical connection structure and preparation method thereof
CN103730445A (en) Circuit board with bicrystal copper circuit layer and manufacturing method thereof
US8482132B2 (en) Pad bonding employing a self-aligned plated liner for adhesion enhancement
CN103390565B (en) Comprising Cu grown in a preferred direction6Sn5Electrical connection structure of crystal grains and preparation method thereof
US8957323B2 (en) Electrical connecting element having nano-twinned copper, method of fabricating the same, and electrical connecting structure comprising the same
TWI441956B (en) Electrodeposition composition and method for coating a semiconductor substrate using the said composition
CN106298634A (en) The method for filling through hole of a kind of oriented growth nano twin crystal copper and application thereof
US8728934B2 (en) Systems and methods for producing flat surfaces in interconnect structures
CN107924878A (en) Structures and methods for low temperature engagement
WO2016137709A1 (en) Thermal interface materials using metal nanowire arrays and sacrificial templates
TW202038409A (en) Low temperature direct copper-copper bonding
CN105332020B (en) Nano-bicrystal gold film, preparation method thereof and bonding structure comprising nano-bicrystal gold film
TWI513863B (en) Copper-electroplating composition and process for filling a cavity in a semiconductor substrate using this composition
US20130285244A1 (en) Through Silicon Via with Embedded Barrier Pad
Tsyntsaru et al. Co-W nanocrystalline electrodeposits as barrier for interconnects
US11578417B2 (en) Nano-twinned crystal film prepared by water/alcohol-soluble organic additives and method of fabricating the same
Park et al. Electrodeposition of nano-twinned Cu and their applications in electronics
CN105280614B (en) Method for the electrochemical deposition of metal on reactive metal film
US20160121582A1 (en) Electric connection and method of manufacturing the same
CN109637977A (en) The groove structure and its manufacturing method of copper filling
Armini et al. Direct copper electrochemical deposition on Ru-based substrates for advanced interconnects target 30 nm and ½ pitch lines: from coupon to full-wafer experiments
Tian et al. Copper pulse-reverse current electrodeposition to fill blind vias for 3-D TSV integration
US20140034370A1 (en) Metallization mixtures and electronic devices
CN1777990A (en) Thermal interconnect systems methods of production and uses thereof
CN104862675B (en) Use the forming method of the through electrode of chemical plating fluid

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant