CN103984905A - Fractional order circuit gene anti-counterfeiting detector for preventing chip from being cloned - Google Patents

Abstract

The invention provides a fractional order circuit gene anti-counterfeiting detector for preventing a chip from being cloned. A fractance and fractional order steepest descent method is adopted to simulate a circuit mode to achieve the detector. Each fractional order unit circuit of the anti-counterfeiting detector is composed of an operational amplifier, a fractance device and a resistor, and circuit parameters of the fractional order unit circuits can be different. The output ends of the fractional order unit circuits of the anti-counterfeiting detector are connected to the input ends of another fractional order unit circuits through the corresponding feedback resistors, and feedback resistance values can be different. An attractor value of the anti-counterfeiting detector is relevant to the order intrinsic quality of fractional orders of the fractional order unit circuits of the anti-counterfeiting detector, and the attractor value is changed along with the changes of the resistance values of the capacitance values of the fractance devices. Human beings cannot manufacture two anti-counterfeiting detectors with the absolutely identical attractor value in a long time in the future. The anti-counterfeiting detector is especially suitable for application occasions of constructing the high-performance anti-counterfeiting chip prevented from being cloned. The detector belongs to the technical field of applied mathematics and circuit system interdisciplines.

Description

Anti-chip clone's fractional order circuit gene false proof detecting device

Technical field

The anti-chip clone's that the present invention proposes fractional order circuit gene false proof detecting device employing minute resists and fractional order method of steepest descent realizes with mimic channel form.The order v of the fractional calculus the present invention relates to ₁, v _iand v _sbe not traditional integer rank, but non-integral order is generally got mark or reasonable decimal in engineering application.V ₁, v _iand v _scan equate, also can be unequal.Wherein, 1 < i < S, i and S are positive integer.See Fig. 3, i fractional order element circuit of this Anti-counterfeiting detector is by operational amplifier A p _i20, divide anti-F _i11 and resistance R _i17 form.Each fractional order element circuit all has identical circuit structure, but its circuit parameter can be different.The output terminal of S fractional order element circuit of this Anti-counterfeiting detector is by feedback resistance R _iS5 are linked to the input end of i fractional order element circuit.The output terminal of each fractional order element circuit is all linked to the input end of another fractional order element circuit in an identical manner by corresponding feedback resistance, each feedback resistance value can be different mutually.The fractional order order v of the attraction subvalue of this Anti-counterfeiting detector and its fractional order element circuit _ithis qualitative correlation, it attracts subvalue always to follow its minute anti-F _i11 resistance value and the change of capacitance and change.In fact, according to existing Electronic Components Manufacturing technological level, the mankind can not produce absolute identical two resistance of its value or electric capacity within the following long period.Yet this is but very lucky in unfortunate.The mankind likely solve certain difficult math question through great efforts, but the mankind but can not change nature physics law all the time.The faint difference of corresponding resistance value or capacitance in any two anti-chips clones' of the present invention fractional order circuit gene false proof detecting device, be exactly the mankind in its production run naturally, randomly, the fractional order circuit gene that inevitably produces.The mankind can not produce two these Anti-counterfeiting detectors with absolute identical attraction subvalue within the following long period.This Anti-counterfeiting detector is specially adapted to construct the application scenario of anti-chip clone's high-performance anti-counterfeiting chip.The invention belongs to the technical field of applied mathematics and digital circuit cross discipline.

Background technology

At present, the protection of intellecture property worldwide, particularly in China, in eventful period.The punishment of taxation or law patches a leak only can to imprecise system.Defect does not exist only in our society among the understanding theory of intellecture property, and is present among anti-counterfeiting technology.In most of the cases, proof of identification and recognition of qulifications are false proof important method.Although encryption technology and digital watermark technology are ripe day by day, but do not have at present a kind of effective ways can be in order to identify this form of piracy of electronic copy.The greatest weakness of encryption technology and digital watermark technology is to resist electronic copy.Therefore, encryption technology is best suited for secret communication in itself, and digital watermark technology is best suited for Information hiding in itself, but not is good at authentication.About false proof anti-chip clone technology, it is the very few new branch of science branch of research at present.This is a kind of challenge for traditional anti-counterfeiting technology.Therefore, this with regard to an urgent demand, we propose a kind of high level anti-chip clone technology.

Within nearly 300 years, to fall, fractional calculus had become an important branch of mathematical analysis already.Fractional calculus is one and the same ancient subject of integer rank infinitesimal analysis, until its related application is absorbed in art of mathematics in the recent period always.At present, for mathematician and physicists, it is a new research direction to fractional calculus.In fact, most of mathematical functions all can be micro-long-pending.Fractional calculus expand and unified difference quotient and Riemann and.As everyone knows, the stochastic variable in physical process can be regarded as the displacement of particle random motion.So fractional calculus can be applied to analyzing and processing many specific physical problems and biomedical engineering.We are obtained is satisfied with experiment effect and relevant theory and has proved these fractional order mathematical operation methods and can be competent at physics and the attracting and practical instrument of bioengineering problem of solving.The fractional calculus of various functions has a significant feature: the fractional calculus of most of functions equals power series, or equals product or the stack of specific function and power function.Is above-mentioned valuable feature implying natural certain substantial variation rule? scientific research shows, the method for fractional order or dimension is the best approach at present many spontaneous phenomenons being described.At present, fractional calculus has been applied to many research fields such as diffusion process, Theory of Viscoelasticity, fractal dynamics and fractional order control.Yet unfortunately,, its main application still concentrates on to be described the transient state of physical change, seldom dabbles the evolutionary process of system.

Among how fractional calculus being applied to Modern Signal Analysis and processing, particularly about among false proof anti-chip clone technology, be all a new branch of science branch that research is very few in the world at present.The fractional calculus characteristic of signal and its integer rank infinitesimal analysis characteristic have marked difference.The fractional order differential of constant is not equal to zero, and the integer rank differential identically vanishing of constant.Therefore, fractional order differential can be for the complex texture minutia of non-linear enhancing image.The fractional order differential of image has special Mach stem effect and antagonistic properties, so that has the wild model of the bionical visual experience of a kind of fractional order.Fractional order differential can not only non-linear maintenance smoothed image region low frequency profile information, fractional order multi-scale enhancement gradation of image value changes frequent and significant high frequency edge and grain details simultaneously.Based on above-mentioned fractional calculus feature, and from the viewpoint of phylogeny, partial fractional differential equation (Fractional Partial Differential Equation, is abbreviated as FPDE) is applied among Denoising of Texture Images.In denoising simultaneously, the Denoising of Texture Images algorithm based on FPDE is obviously better than the traditional algorithm based on integer exponent arithmetic(al) to the hold facility of high frequency edge and complex texture detailed information, particularly for being rich in the texture image of grain details.Other is studied and shows in early days, among fractional order Adaptive Signal Processing and fractional order adaptive control, and fractional order extreme point and traditional integer rank extreme point, single order stationary point, makes a marked difference.In order to search for the fractional order extreme point of energy functional, we are generalized to fractional order by integer rank method of steepest descent, have proposed fractional order method of steepest descent.Based on above-mentioned early-stage Study, the present invention introduces a kind of mathematical method of novelty: fractional calculus is in order to realize anti-chip clone's of the present invention fractional order circuit gene false proof detecting device.

Correlative study shows, the anti-chip clone technology of highest level must meet devil's technical indicators of following 4 anti-chip clones simultaneously: the 1st, and all dependency basis present principles and mathematical algorithm full disclosure; The 2nd, the full disclosure of all interlock circuit structure and parameters; The 3rd, the production and processing technology of all interlock circuits and raw materials full disclosure; The 4th, can also accomplish even inventor and chip production manufacturer oneself all must not produce two absolute identical chip circuits simultaneously.Pertinent literature is looked into newly and is shown, anti-chip clone's of the present invention fractional order circuit gene false proof detecting device is the anti-chip clone technology of the highest level of unique devil's technical indicator that can really simultaneously meet above-mentioned 4 anti-chips clones in the world at present.This Anti-counterfeiting detector is specially adapted to construct the application scenario of anti-chip clone's high-performance anti-counterfeiting chip.Anti-chip clone's of the present invention fractional order circuit gene false proof detecting device has the original and utmost point of high theory market application foreground widely.

Summary of the invention

The anti-chip clone's that the present invention proposes fractional order circuit gene false proof detecting device employing minute resists and fractional order method of steepest descent realizes with mimic channel form.The order v of the fractional calculus the present invention relates to ₁, v _iand v _sbe not traditional integer rank, but non-integral order is generally got mark or reasonable decimal in engineering application.V ₁, v _iand v _scan equate, also can be unequal.Wherein, 1 < i < S, i and S are positive integer.See Fig. 3, i fractional order element circuit of this Anti-counterfeiting detector is by operational amplifier A p _i20, divide anti-F _i11 and resistance R _i17 form.Each fractional order element circuit all has identical circuit structure, but its circuit parameter can be different.The output terminal of S fractional order element circuit of this Anti-counterfeiting detector is by feedback resistance R _iS5 are linked to the input end of i fractional order element circuit.The output terminal of each fractional order element circuit is all linked to the input end of another fractional order element circuit in an identical manner by corresponding feedback resistance, each feedback resistance value can be different mutually.The fractional order order v of the attraction subvalue of this Anti-counterfeiting detector and its fractional order element circuit _ithis qualitative correlation, it attracts subvalue always to follow its minute anti-F _i11 resistance value and the change of capacitance and change.The mankind can not produce two these Anti-counterfeiting detectors with absolute identical attraction subvalue within the following long period.Anti-chip clone's of the present invention fractional order circuit gene false proof detecting device has high anti-chip clone performance.Correlative study shows, the anti-chip clone technology of highest level must meet devil's technical indicators of following 4 anti-chip clones simultaneously: the 1st, and all dependency basis present principles and mathematical algorithm full disclosure; The 2nd, the full disclosure of all interlock circuit structure and parameters; The 3rd, the production and processing technology of all interlock circuits and raw materials full disclosure; The 4th, can also accomplish even inventor and chip production manufacturer oneself all must not produce two absolute identical chip circuits simultaneously.Pertinent literature is looked into newly and is shown, anti-chip clone's of the present invention fractional order circuit gene false proof detecting device is the anti-chip clone technology of the highest level of unique devil's technical indicator that can really simultaneously meet above-mentioned 4 anti-chips clones in the world at present.This Anti-counterfeiting detector is specially adapted to construct the application scenario of anti-chip clone's high-performance anti-counterfeiting chip.Anti-chip clone's of the present invention fractional order circuit gene false proof detecting device has the original and utmost point of high theory market application foreground widely.

In order to clearly demonstrate the circuit of anti-chip clone's of the present invention fractional order circuit gene false proof detecting device, form, be necessary first the ultimate principle of this Anti-counterfeiting detector and mathematical algorithm derivation thereof to be carried out to following brief description:

Within nearly 300 years, to fall, fractional calculus has become an important branch of mathematical analysis.Yet fractional calculus is for most mathematicians, physicist and engineering scholar are also rarely known by the people in the world.Among how fractional calculus being applied to Modern Signal Analysis and processing, particularly, among anti-chip clone, be one and worldwide all study very few new branch of science branch at present.Early-stage Study of the present invention shows, the long-term memory that fractional calculus has and nonlocality.Therefore, a kind of very natural idea is: how to use fractional calculus to realize anti-chip clone's fractional order circuit gene false proof detecting device.The present invention resists with mimic channel form realization minute, and application minute resists and fractional order method of steepest descent realizes the fractional order circuit gene false proof detecting device that anti-chip is cloned, and builds its Lyapunov function, further analyzes its attractor.The present invention's application fractional calculus is realized anti-chip clone's fractional order circuit gene false proof detecting device, is mainly because its long-term memory having and non-locality.Main research contribution of the present invention is: by form and the fractional order method of steepest descent of mimic channel, proposed the fractional order circuit gene false proof detecting device that anti-chip is cloned, constructed its Lyapunov function, proved its Lyapunov stability, analyzed its attractor, and the significant advantage of the fractional order circuit gene false proof detecting device of simultaneously having found anti-chip clone in the anti-chip clone about false proof.The arbitrariness of the fractional order order value of anti-chip clone's of the present invention fractional order circuit gene false proof detecting device, portrays such as power law long-term memory and the so special dynamic behavior of power law non-locality extra degree of freedom is provided for it.A significant advantage of anti-chip clone's of the present invention fractional order circuit gene false proof detecting device is its attractor and this qualitative correlation of fractional order order of its fractional order element circuit, and its attraction subvalue always follows the change of its minute anti-resistance value and capacitance and changes.In fact, according to existing Electronic Components Manufacturing technological level, the mankind can not produce absolute identical two resistance of its value or electric capacity within the following long period.Yet this is but very lucky in unfortunate.The mankind likely solve certain difficult math question through great efforts, but the mankind but can not change nature physics law all the time.The faint difference of corresponding resistance value or capacitance in any two anti-chips clones' of the present invention fractional order circuit gene false proof detecting device, be exactly the mankind in its production run naturally, randomly, the fractional order circuit gene that inevitably produces.The mankind can not produce two these Anti-counterfeiting detectors with absolute identical attraction subvalue within the following long period.This Anti-counterfeiting detector is specially adapted to construct the application scenario of anti-chip clone's high-performance anti-counterfeiting chip.

As everyone knows, fractal mathematical theory has produced the transformation of estimating sight, and fractal geometry have negated the existence of newton-Leibnitz derivative.The Hausdorff of take estimates as basic fractal theory, although gone through research a kind of very incomplete mathematical theory still so far of more than 90 years.The structure of the infinitesimal analysis mathematical theory under Hausdorff estimates not yet can complete so far.Development comparative maturity is to estimate undefined fractional calculus at Euclidean at present, and it requires to use Euclidean to estimate on mathematics.Under Euclidean is estimated, what fractional calculus was the most frequently used is that Gr ü mwald-Letnikov definition, Riemann-Liouville and Caputo define three kinds.The v rank infinitesimal analysis of Gr ü mwald-Letnikov definition signal s (x) is $D_{G-L}^{v}s\left(x\right)=\frac{d^v}{{\left[d(x-a)\right]}^v}s\left(x\right){|}_{G-L}=\underset{N\&RightArrow;\&infin;}{\lim }\left\{\frac{{\left(\frac{x-a}{N}\right)}^{-v}}{\mathrm{\&Gamma;}(-v)}\underset{k=0}{\overset{N-1}{\mathrm{\&Sigma;}}}\frac{\mathrm{\&Gamma;}(k-v)}{\mathrm{\&Gamma;}(k+1)}s(x-k\left(\frac{x-a}{N}\right))\right\}.$ Wherein, the extended period of signal s (x) is [a, x], and v is any real number (comprising mark), the fractional order differential operator of expression based on Gr ü mwald-Letnikov definition, Γ is gamma (Gamma) function.From the Gr ü mwald-Letnikov definition of fractional calculus, Gr ü mwald-Letnikov is defined in Euclidean to be estimated the lower integer step by integer rank infinitesimal analysis and is generalized to mark step-length, thereby the integer rank of infinitesimal analysis are generalized to fractional order.The calculating of the Gr ü mwald-Letnikov definition of fractional calculus is simple and easy to do, and it only needs relevant to signal s (x) self discrete sampling value, and derivative and the integrated value of undesired signal s (x).The v rank integration (v < 0) of Riemann-Liouville definition signal s (x) is $D_{R-L}^{v}s\left(x\right)=\frac{d^v}{{\left[d(x-a)\right]}^v}s\left(x\right){|}_{R-L}=\frac{1}{\mathrm{\&Gamma;}(-v)}\underset{a}{\overset{x}{\&Integral;}}{(x-\mathrm{\&eta;})}^{-v-1}s\left(\mathrm{\&eta;}\right)\mathrm{d\&eta;}=\frac{-1}{\mathrm{\&Gamma;}(-v)}\underset{a}{\overset{x}{\&Integral;}}s\left(\mathrm{\&eta;}\right)d{(x-\mathrm{\&eta;})}^{-v},$ v＜0。Wherein, the fractional order differential operator of expression based on Riemann-Liouville definition.For the v rank differential (v >=0) of signal s (x), n meets n-1 < v≤n.So by Riemann-Liouville Definitions On Integration formula, the Riemann-Liouville that the present invention can derive the v rank differential of signal s (x) is defined as $D_{R-L}^{v}s\left(x\right)=\frac{d^v}{{\left[d(x-a)\right]}^v}s\left(x\right){|}_{R-L}=\underset{k=0}{\overset{n-1}{\mathrm{\&Sigma;}}}\frac{{(x-a)}^{k-v}{s}^{\left(k\right)}\left(a\right)}{\mathrm{\&Gamma;}(k-v+1)}+\frac{1}{\mathrm{\&Gamma;}(n-v)}\underset{a}{\overset{x}{\&Integral;}}\frac{s^{\left(n\right)}\left(\mathrm{\&eta;}\right)}{{(x-\mathrm{\&eta;})}^{v-n+1}}\mathrm{d\&eta;},$ 0≤v＜n。By the Riemann-Liouville definition of fractional order differential, can the derive Fourier (Fourier) of signal s (x) of the present invention is transformed to $\mathrm{FT}\left[D^{v}s\left(x\right)\right]={\left(\mathrm{i\&omega;}\right)}^v\mathrm{FT}\left[s\left(x\right)\right]-\underset{k=0}{\overset{n-1}{\mathrm{\&Sigma;}}}{\left(\mathrm{i\&omega;}\right)}^k\frac{d^{v-1-k}}{{\mathrm{dx}}^{v-1-k}}s\left(0\right).$ Wherein, i is imaginary unit, and ω is numerical frequency.When signal s (x) is causal signal, above formula can be reduced to FT[D ^vs (x)]=(i ω) ^vfT[s (x)].The v rank differential of Caputo definition signal s (x) is $D_x^v{}_a{}^{C}s\left(x\right)=\frac{1}{\mathrm{\&Gamma;}(n-v)}\underset{a}{\overset{x}{\&Integral;}}{(t-\mathrm{\&tau;})}^{n-v-1}{s}^{\left(n\right)}\left(\mathrm{\&tau;}\right)\mathrm{d\&tau;}.$ Wherein, 0≤n-1 < v < n, n ∈ R, represent Caputo fractional order differential operator.? $D_x^v{}_a{}^{C}s\left(x\right)=\frac{1}{\mathrm{\&Gamma;}(n-v)}\underset{a}{\overset{x}{\&Integral;}}{(t-\mathrm{\&tau;})}^{n-v-1}{s}^{\left(n\right)}\left(\mathrm{\&tau;}\right)\mathrm{d\&tau;}$ In, first signal s (x) is carried out to n rank and differentiate, then carry out the integral operation of n-v rank.

For the fractional order circuit gene false proof detecting device with mimic channel formal construction anti-chip clone of the present invention, first the present invention must realize the fractional calculus of signal with mimic channel form.Along with correlative study successfully realizes fractional order differential filter with mimic channel form, there is a kind of by name minute anti-brand-new circuit elements device.Early-stage Study of the present invention shows, minute anti-is to consist of with the mimic channel form of other infinite recursion structures such as dendritic, double circuit type, H type, grid type common resistance r and electric capacity c, has the fractal structure of height self similarity.Say in this sense, divide the anti-fractional order impedance that means.Therefore, the present invention's symbol represent minute anti-ly, wherein F fractional order element circuit is an english abbreviation that minute resists (Fractance).Early-stage Study of the present invention shows, on v rank, divides anti-F _vin, F _vinput voltage V _i(t) perseverance and F _vinput current I _i(t) v rank are integrated into direct ratio.Meanwhile, I _i(t) perseverance and V _i(t) v rank differential is directly proportional.So can obtain $I_i\left(t\right)=\frac{1}{{\mathrm{\&xi;}}^v\mathrm{\&Gamma;}(n-v)}\underset{0}{\overset{t}{\&Integral;}}{(t-\mathrm{\&tau;})}^{n-v-1}{V_i}^{\left(n\right)}\left(\mathrm{\&tau;}\right)\mathrm{d\&tau;}.$ Wherein n meets 0≤n-1 < v≤n, ξ=r/c.

See Fig. 1, i fractional order element circuit of anti-chip clone's of the present invention fractional order circuit gene false proof detecting device is by an operational amplifier A p _iresist with associated dividing and resistance R _iform.Each fractional order element circuit all has identical circuit structure, but its circuit parameter can be different.Wherein, the resistance R of i fractional order element circuit _ican be zero, also can be non-vanishing.For convenience of explanation, mathematical algorithm below makes R in deriving _i=R.Divide anti- in order to realize v rank fractional calculus.The present invention makes dividing of the 1st fractional order element circuit anti- dividing of i fractional order element circuit is anti- and resist dividing of S fractional order element circuit in other words, even the fractional-order of each fractional order element circuit of anti-chip clone's fractional order circuit gene false proof detecting device equals respectively v ₁, v _iand v _s.So, v _irank are divided anti- input current with input voltage n _i(t) v _irank fractional order differential perseverance is directly proportional.In Laplace transform domain, order represent v _irank are divided anti- laplace conversion.

See Fig. 2, the present invention adopts a minute anti-and fractional order method of steepest descent, with the anti-chip clone's of mimic channel formal construction fractional order circuit gene false proof detecting device.By Kirchhoff current law, can derive anti-chip clone's the operation rule of fractional order circuit gene false proof detecting device of the present invention is $I_{F_i}\left(S\right)=\frac{N_i\left(S\right)}{F_{v_i}\left(S\right)}=\underset{j=1}{\overset{S}{\mathrm{\&Sigma;}}}{T}_{i,j}\&CenterDot;A_j\left(S\right)-\frac{N_i\left(S\right)}{Z_i}+I_i\left(S\right).$ Wherein n _i(S), a _jand I (S) _i(S) be respectively n _i(t), a _jand i (t) _i(t) Laplace conversion.N _i(t) be the operational amplifier A p of i fractional order element circuit _iinput voltage, a _i(t) be the output voltage of i fractional order element circuit, i _i(t) be the input current of i fractional order element circuit.R _{i, j}it is the feedback resistance of the link output terminal of j fractional order element circuit and the input end of i fractional order element circuit.Therefore, can obtain electric leading it is symmetrical that the present invention makes the circuit structure of anti-chip clone's fractional order circuit gene false proof detecting device, so T _{i, j}=T _{j, i}.The present invention's order

So, by $i_i\left(t\right)=\frac{1}{{\mathrm{\&xi;}}^v\mathrm{\&Gamma;}(n-v)}\underset{0}{\overset{t}{\&Integral;}}{(t-\mathrm{\&tau;})}^{n-v-1}{v_i}^{\left(n\right)}\left(\mathrm{\&tau;}\right)\mathrm{d\&tau;}$ Can obtain, $I_{F_i}\left(S\right)=\frac{N_i\left(S\right)}{F_{v_i}\left(S\right)}=\underset{j=1}{\overset{S}{\mathrm{\&Sigma;}}}{T}_{i,j}\&CenterDot;A_j\left(S\right)-\frac{N_i\left(S\right)}{Z_i}+I_i\left(S\right)$ Laplace contravariant be changed to $i_{F_i}\left(t\right)=K\frac{d^{v_i}{n}_i\left(t\right)}{{\mathrm{dt}}^{v_i}}=\frac{K}{\mathrm{\&Gamma;}(n-v_i)}\underset{0}{\overset{t}{\&Integral;}}{(t-\mathrm{\&tau;})}^{n-v_i-1}{n_i}^{\left(n\right)}\left(\mathrm{\&tau;}\right)\mathrm{d\&tau;}=\underset{j=1}{\overset{S}{\mathrm{\&Sigma;}}}{T}_{i,j}\&CenterDot;a_j\left(t\right)-\frac{n_i\left(t\right)}{Z_i}+i_i\left(t\right).$ 0≤n-1 < v wherein _i< n, a normal number, and ξ=r/c.The present invention exists $i_{F_i}\left(t\right)=K\frac{d^{v_i}{n}_i\left(t\right)}{{\mathrm{dt}}^{v_i}}=\frac{K}{\mathrm{\&Gamma;}(n-v_i)}\underset{0}{\overset{t}{\&Integral;}}{(t-\mathrm{\&tau;})}^{n-v_i-1}{n_i}^{\left(n\right)}\left(\mathrm{\&tau;}\right)\mathrm{d\&tau;}=\underset{j=1}{\overset{S}{\mathrm{\&Sigma;}}}{T}_{i,j}\&CenterDot;a_j\left(t\right)-\frac{n_i\left(t\right)}{Z_i}+i_i\left(t\right)$ Z is multiplied by both sides simultaneously _iso, can obtain $Z_{i}K\frac{d^{v_i}{n}_i\left(t\right)}{{\mathrm{dt}}^{v_i}}=\underset{j=1}{\overset{S}{\mathrm{\&Sigma;}}}{Z}_i{T}_{i,j}\&CenterDot;a_j\left(t\right)-n_i\left(t\right)+Z_i{i}_i\left(t\right).$ The present invention makes χ _i=Z _ik, it is a normal number.Make w _{i, j}=Z _it _{i, j}, b _i=Z _ii _i.Therefore, can obtain ${\mathrm{\&chi;}}_i\frac{d^{v_i}{n}_i\left(t\right)}{{\mathrm{dt}}^{v_i}}=-n_i\left(t\right)+\underset{j=1}{\overset{S}{\mathrm{\&Sigma;}}}{w}_{i,j}{a}_j\left(t\right)+b_i\left(t\right).$ So, can obtain its vector form and be $\mathrm{\&chi;}\frac{d^{v}n\left(t\right)}{{\mathrm{dt}}^v}=-n\left(t\right)+\mathrm{Wa}\left(t\right)+b.$ χ=[χ wherein ₁χ _iχ _s] ^t, v=[v ₁v _iv _s] ^t, W is the weight matrix of anti-chip clone's of the present invention fractional order circuit gene false proof detecting device. ${\mathrm{\&chi;}}_i\frac{d^{v_i}{n}_i\left(t\right)}{{\mathrm{dt}}^{v_i}}=-n_i\left(t\right)+\underset{j=1}{\overset{S}{\mathrm{\&Sigma;}}}{w}_{i,j}{a}_j\left(t\right)+b_i\left(t\right)$ With be the state equation of anti-chip clone's of the present invention fractional order circuit gene false proof detecting device.The state equation of the fractional order circuit gene false proof detecting device of being cloned from anti-chip of the present invention, this state equation comprises it is obviously a partial fractional differential equation, rather than a first order partial differential equation.Further, from the definition of fractional calculus, due to fractional order differential be non-local and there is weak singular kernel, so it can provide a kind of fabulous method in order to portray long-term memory and the non-locality of nonlinear kinetics process.Because the order of fractional order differential has arbitrariness, cause it to describe special dynamic behavior and there is extra degree of freedom, so partial fractional differential equation is used to describe the Kind of Nonlinear Dynamical System such as anti-chip clone's of the present invention fractional order circuit gene false proof detecting device.These Kind of Nonlinear Dynamical Systems have power law non-locality, power law long-term memory, Fractal Properties and chaotic behavior.Another key property of fractional order differential is that its value not only depends on assessment local situation constantly, but also depends on all accounts of the history of signal.The fractional order circuit gene false proof detecting device of cloning due to anti-chip of the present invention has long-term memory, and the value of its any observation station all depends on all past values of signal, so this characteristic of fractional order differential is normally useful for anti-chip clone's of the present invention fractional order circuit gene false proof detecting device.It is corresponding with the non-locality of fractional order differential, it is a kind of expression formula of non-local.The non-locality voltage obtaining thus can produce fixedly charging effect to circuit, and can be converted into successively non-locality storage charging effect.

On this basis, the present invention just can construct anti-chip clone fractional order circuit gene false proof detecting device Lyapunov function and analyze its equilibrium point.As mentioned above, Ap _iit is an operational amplifier.With circuit form, f represents operational amplifier A p _iinput-output characteristic function, there is the inappreciable corresponding time.The present invention makes f (0)=0.The present invention also can define its contrary output-input characteristics easily, i.e. the inverse function f of f ^-1for a _i(t)=f[n _i(t)].So can obtain its vector form is a (t)=f[n (t)].The present invention makes parsing increasing function f have inverse function f ^-1.Therefore, f ^-1also be one and resolve increasing function.So can obtain n _i(t)=f ^-1[a _i(t)].So can obtain its vector form is n (t)=f ^-1[a (t)].The present invention adopts variable gradient method to construct the Lyapunov function of anti-chip clone's fractional order circuit gene false proof detecting device.The practical application of anti-chip clone's of the present invention fractional order circuit gene false proof detecting device depends on its dynamic behavior to a great extent, such as its Lyapunov stability and Asymptotic Stability.Anti-chip clone's of the present invention fractional order circuit gene false proof detecting device does not have weight matrix learning rules correspondingly.This anti-chip clone's fractional order circuit gene false proof detecting device is neither trained, also not self-teaching.In fact, definite design based on its Lyapunov function of the weight matrix of anti-chip clone's of the present invention fractional order circuit gene false proof detecting device.By ${\mathrm{\&chi;}}_i\frac{d^{v_i}{n}_i\left(t\right)}{{\mathrm{dt}}^{v_i}}=-n_i\left(t\right)+\underset{j=1}{\overset{S}{\mathrm{\&Sigma;}}}{w}_{i,j}{a}_j\left(t\right)+b_i\left(t\right)$ And a _i(t)=f[n _i(t)] known, anti-chip clone's of the present invention fractional order circuit gene false proof detecting device is a fractional order nonlinear system.The Lyapunov function of this anti-chip clone's fractional order circuit gene false proof detecting device is used for solving a class fractional order Asymptotic Stability.By ${\mathrm{\&chi;}}_i\frac{d^{v_i}{n}_i\left(t\right)}{{\mathrm{dt}}^{v_i}}=-n_i\left(t\right)+\underset{j=1}{\overset{S}{\mathrm{\&Sigma;}}}{w}_{i,j}{a}_j\left(t\right)+b_i\left(t\right),$ The present invention defines an analytical function ρ _i(t) be ${\mathrm{\&rho;}}_i\left(t\right)={\mathrm{\&chi;}}_i\frac{d^{v_i}{n}_i\left(t\right)}{{\mathrm{dt}}^{v_i}}=-n_i\left(t\right)+\underset{j=1}{\overset{S}{\mathrm{\&Sigma;}}}{w}_{i,j}{a}_j\left(t\right)+b_i\left(t\right).$ ρ _i(t) be one can micro-long-pending function.According to the character of fractional calculus, can obtain $D_t^v\mathrm{\&psi;}\left(t\right)=\underset{n=0}{\overset{\&infin;}{\mathrm{\&Sigma;}}}\frac{D_t^n\mathrm{\&psi;}\left(t\right)}{\mathrm{\&Gamma;}(1+n-v)}{t}^{n-v}.$ Wherein be v rank fractional order differential operators, ψ (t) is analytical function, n rank differentiating operators.So, by formula $D_t^v\mathrm{\&psi;}\left(t\right)=\underset{n=0}{\overset{\&infin;}{\mathrm{\&Sigma;}}}\frac{D_t^n\mathrm{\&psi;}\left(t\right)}{\mathrm{\&Gamma;}(1+n-v)}{t}^{n-v}$ Can obtain with Fa à de Bruno formula wherein a function of functions, $\left(\begin{array}{c}v\\ n\end{array}\right)=\frac{{(-1)}^{-n}\mathrm{\&Gamma;}(n-v)}{\mathrm{\&Gamma;}(-v)\mathrm{\&Gamma;}(1+n)},$ with integer rank differentiating operators, and P _kmeet $\left\{\begin{array}{c}\underset{k=1}{\overset{n}{\mathrm{\&Sigma;}}}k{P}_k=n\\ \underset{k=1}{\overset{n}{\mathrm{\&Sigma;}}}{P}_k=m\end{array}\right..$ in the 3rd summation symbol ∑ represent for meeting $\left\{\begin{array}{c}\underset{k=1}{\overset{n}{\mathrm{\&Sigma;}}}k{P}_k=n\\ \underset{k=1}{\overset{n}{\mathrm{\&Sigma;}}}{P}_k=m\end{array}\right.$ All and P _k| _{m=1 → n}combine corresponding summation.By the Riemann-Liouville definition of fractional calculus and known, the fractional order differential of function of functions equals infinite sum.Therefore, the present invention by the Lyapunov construction of function of anti-chip clone's fractional order circuit gene false proof detecting device is $E\left[a\left(t\right)\right]=\frac{{-t}^{v_i}}{\mathrm{\&Gamma;}(1+v_i)}\underset{i=1}{\overset{S}{\mathrm{\&Sigma;}}}{\left(D_t^1{a}_i\right)}^2-\underset{i=1}{\overset{S}{\mathrm{\&Sigma;}}}\underset{n=1}{\overset{\&infin;}{\mathrm{\&Sigma;}}}\left(\begin{array}{c}-v_i\\ n\end{array}\right)\frac{t^{{n+v}_i}n!}{\mathrm{\&Gamma;}(1+n+v_i)}\underset{m=1}{\overset{n}{\mathrm{\&Sigma;}}}{D}_{D_t^1{a}_i}^m{\left(D_t^1{a}_i\right)}^2\mathrm{\&Sigma;}\underset{k=1}{\overset{n}{\mathrm{\&Pi;}}}\frac{1}{P_k!}{\left(\frac{D_t^{k+1}{a}_i}{k!}\right)}^{P_k}.$ Wherein $D_t^1{a}_i\left(t\right)=\left(D^{1}f\right)\left[D_t^{1-v_i}({\mathrm{\&rho;}}_i\left(t\right)/{\mathrm{\&chi;}}_i)\right],$ v _irank fractional order integration operator.Because $D_{D_t^1{a}_i}^1{\left(D_t^1{a}_i\right)}^2=2D_t^1{a}_i,$ $D_{D_t^1{a}_i}^2{\left(D_t^1{a}_i\right)}^2=2,$ And $D_{D_t^1{a}_i}^m{\left(D_t^1{a}_i\right)}^2\stackrel{m\&GreaterEqual;3}{\&equiv;}0.$ Therefore, the Lyapunov function of anti-chip clone's of the present invention fractional order circuit gene false proof detecting device can be reduced to $E\left[a\left(t\right)\right]=\frac{-t^{v_i}}{\mathrm{\&Gamma;}(1+v_i)}\underset{i=1}{\overset{S}{\mathrm{\&Sigma;}}}{\left(D_t^1{a}_i\right)}^2-\left(\begin{array}{c}-v_i\\ 1\end{array}\right)\frac{2t^{1+v_i}}{\mathrm{\&Gamma;}(2+v_i)}\underset{i=1}{\overset{S}{\mathrm{\&Sigma;}}}\left(D_t^1{a}_i\right)\left(D_t^2{a}_i\right)$ $-\underset{i=1}{\overset{S}{\mathrm{\&Sigma;}}}\underset{n=2}{\overset{\&infin;}{\mathrm{\&Sigma;}}}\left(\begin{array}{c}-v_i\\ n\end{array}\right)\frac{2t^{n+v_i}n!}{\mathrm{\&Gamma;}(1+n+v_i)}\{D_t^1{a}_i{\left[\underset{k=1}{\overset{n}{\mathrm{\&Pi;}}}\frac{1}{P_k!}{\left(\frac{D_t^{k+1}{a}_i}{k!}\right)}^{P_k}\right]}_{m=1}+{\left[\underset{k=1}{\overset{n}{\mathrm{\&Pi;}}}\frac{1}{P_k!}{\left(\frac{D_t^{k+1}{a}_i}{k!}\right)}^{P_k}\right]}_{m=2}\}.$ So, on above formula both sides simultaneously to E[a _i(t)] be v _irank fractional order differential, so can obtain $D_t^{v}E=\frac{d^{v}E}{{\mathrm{dt}}^v}=-\underset{i=1}{\overset{S}{\mathrm{\&Sigma;}}}{\left[D_t^1{a}_i\left(t\right)\right]}^2\&le;0.$ It is therefore known, it is a negative semidefinite function.E (t) is an effective Lyapunov function of anti-chip clone's of the present invention fractional order circuit gene false proof detecting device.When time, the system capacity of anti-chip clone's of the present invention fractional order circuit gene false proof detecting device just remains unchanged, and its system reaches steady state (SS).By $D_t^{v}E=\frac{d^{v}E}{{\mathrm{dt}}^v}=-\underset{i=1}{\overset{S}{\mathrm{\&Sigma;}}}{\left[D_t^1{a}_i\left(t\right)\right]}^2\&le;0,$ The present invention can push away $D_t^{v_i}E=\frac{d^{v_i}E}{{\mathrm{dt}}^{v_i}}=0$ The equivalent form of value be $D_t^1{a}_i\left(t\right)=\frac{{\mathrm{da}}_i\left(t\right)}{\mathrm{dt}}=0.$ So, can obtain its vector form and be $D_t^{1}a\left(t\right)=\frac{\mathrm{da}\left(t\right)}{\mathrm{dt}}=0.$ So the present invention just can be according to LaSalle invariance theorem and fractional order method of steepest descent, determine the equilibrium point of Lyapunov function of anti-chip clone's fractional order circuit gene false proof detecting device.Because fractional order method of steepest descent is different from single order method of steepest descent.Each step optimizing search of fractional order method of steepest descent is all carried out, but not is carried out in the negative direction of its First-order Gradient in the negative direction of the fractional order gradient of Lyapunov function.In addition, the character based on fractional order differential is known, the single order differential identically vanishing of any single order Local Extremum, but its fractional order differential is not equal to zero, and vice versa.Therefore, fractional order Local Extremum and its integer rank Local Extremum are not same point.The equilibrium point of the Lyapunov function of anti-chip clone's of the present invention fractional order circuit gene false proof detecting device is the potential attractor of this anti-chip clone's fractional order circuit gene false proof detecting device.

On this basis, the present invention just can analyze the attractor of anti-chip clone's fractional order circuit gene false proof detecting device.As known in above-mentioned analysis, the equilibrium point of the Lyapunov function of anti-chip clone's of the present invention fractional order circuit gene false proof detecting device is the potential attractor of this anti-chip clone's fractional order circuit gene false proof detecting device.By $D_t^v\mathrm{\&psi;}\left(t\right)=\underset{n=0}{\overset{\&infin;}{\mathrm{\&Sigma;}}}\frac{D_t^n\mathrm{\&psi;}\left(t\right)}{\mathrm{\&Gamma;}(1+n-v)}{t}^{n-v}$ Lyapunov function with anti-chip clone's of the present invention fractional order circuit gene false proof detecting device, can obtain $D_{a_i}^{v_i}E=\frac{d^{v_i}E}{{\mathrm{da}}_i^{v_i}}=-\underset{n=0}{\overset{\&infin;}{\mathrm{\&Sigma;}}}\left[\frac{a_i^{n-v_i}{D}_t^{n-v_i}{\left[D_t^1{a}_i\left(t\right)\right]}^2}{\mathrm{\&Gamma;}(1+n-v_i)}\right].$ So, can obtain its vector form and be $D_a^{v}E=\frac{d^{v}E}{{\mathrm{da}}^v}=-\underset{i=1}{\overset{S}{\mathrm{\&Sigma;}}}\underset{n=0}{\overset{\&infin;}{\mathrm{\&Sigma;}}}\left[\frac{a_i^{n-v_i}{D}_t^{n-v_i}{\left[D_t^1{a}_i\left(t\right)\right]}^2}{\mathrm{\&Gamma;}(1+n-v_i)}\right].$ V=[v wherein ₁v _iv _s] ^t.By $D_t^1{a}_i\left(t\right)=\frac{{\mathrm{da}}_i\left(t\right)}{\mathrm{dt}}=0$ With $D_{a_i}^{v_i}E=\frac{d^{v_i}E}{{\mathrm{da}}_i^{v_i}}=-\underset{n=0}{\overset{\&infin;}{\mathrm{\&Sigma;}}}\left[\frac{a_i^{n-v_i}{D}_t^{n-v_i}{\left[D_t^1{a}_i\left(t\right)\right]}^2}{\mathrm{\&Gamma;}(1+n-v_i)}\right],$ The present invention can be derived from, when $D_t^1{a}_i\left(t\right)=\frac{{\mathrm{da}}_i\left(t\right)}{\mathrm{dt}}=0$ Time, have $D_{a_i}^{v_i}E=\frac{d^{v_i}E}{{\mathrm{da}}_i^{v_i}}=0.$ So the present invention can obtain its vector form and be, when $D_t^{1}a\left(t\right)=\frac{\mathrm{da}\left(t\right)}{\mathrm{dt}}=0$ Time, have $\frac{d^{v}E}{{\mathrm{da}}^v}=0.$ Therefore, when a (t) meets $D_t^{1}a\left(t\right)=\frac{\mathrm{da}\left(t\right)}{\mathrm{dt}}=0$ Time, the equilibrium point of the Lyapunov function of anti-chip clone's of the present invention fractional order circuit gene false proof detecting device is the attractor of this anti-chip clone's fractional order circuit gene false proof detecting device.Here it is the anti-chip clone's of the present invention complete mathematical algorithm of fractional order circuit gene false proof detecting device is derived.

As the above analysis, anti-chip clone's of the present invention the attraction subvalue of fractional order circuit gene false proof detecting device and the fractional order order v of its fractional order element circuit _ithis qualitative correlation.By ${\mathrm{\&chi;}}_i\frac{d^{v_i}{n}_i\left(t\right)}{{\mathrm{dt}}^{v_i}}=-n_i\left(t\right)+\underset{j=1}{\overset{S}{\mathrm{\&Sigma;}}}{w}_{i,j}{a}_j\left(t\right)+b_i\left(t\right)$ Known, the fractional order order v of its fractional order element circuit _iagain with its v _irank are divided anti- this qualitative correlation.In addition, for the v of fractional order element circuit _irank are divided anti- , by $i_i\left(t\right)=\frac{1}{{\mathrm{\&xi;}}^v\mathrm{\&Gamma;}(n-v)}\underset{0}{\overset{t}{\&Integral;}}{(t-\mathrm{\&tau;})}^{n-v-1}{v_i}^{\left(n\right)}\left(\mathrm{\&tau;}\right)\mathrm{d\&tau;},$ Divide anti- conventionally and ξ=r/c proportional.Therefore, the attraction subvalue of anti-chip clone's of the present invention fractional order circuit gene false proof detecting device always follows the change of its minute anti-resistance value and capacitance and changes.In fact, according to existing Electronic Components Manufacturing technological level, the mankind can not produce absolute identical two resistance of its value or electric capacity within the following long period.Yet this is but very lucky in unfortunate.The mankind likely solve certain difficult math question through great efforts, but the mankind but can not change nature physics law all the time.The faint difference of corresponding resistance value or capacitance in anti-chip clone's of the present invention fractional order circuit gene false proof detecting device, be exactly the mankind in its production run naturally, randomly, the fractional order circuit gene that inevitably produces.According to existing Electronic Components Manufacturing technological level, the mankind can not produce the fractional order circuit gene false proof detecting device of two anti-chip clones of the present invention with absolute identical attraction subvalue within the following long period.Therefore, anti-chip clone's of the present invention fractional order circuit gene false proof detecting device is specially adapted to construct the application scenario of anti-chip clone's high-performance anti-counterfeiting chip.The ultimate principle of Here it is anti-chip clone's of the present invention fractional order circuit gene false proof detecting device.

Based on above-mentioned ultimate principle and mathematical algorithm thereof, anti-chip clone's of the present invention fractional order circuit gene false proof detecting device has high anti-chip clone performance.Correlative study shows, the anti-chip clone technology of highest level must meet devil's technical indicators of following 4 anti-chip clones simultaneously: the 1st, and all dependency basis present principles and mathematical algorithm full disclosure; The 2nd, the full disclosure of all interlock circuit structure and parameters; The 3rd, the production and processing technology of all interlock circuits and raw materials full disclosure; The 4th, can also accomplish even inventor and chip production manufacturer oneself all must not produce two absolute identical chip circuits simultaneously.Pertinent literature is looked into newly and is shown, anti-chip clone's of the present invention fractional order circuit gene false proof detecting device is the anti-chip clone technology of the highest level of unique devil's technical indicator that can really simultaneously meet above-mentioned 4 anti-chips clones in the world at present.This Anti-counterfeiting detector is specially adapted to construct the application scenario of anti-chip clone's high-performance anti-counterfeiting chip.Anti-chip clone's of the present invention fractional order circuit gene false proof detecting device has the original and utmost point of high theory market application foreground widely.

The ultimate principle of the fractional order circuit gene false proof detecting device based on the above-mentioned anti-chip clone that the present invention is proposed and the brief description that mathematical algorithm is derived thereof, the circuit that illustrates this Anti-counterfeiting detector below forms:

See Fig. 3, the anti-chip clone's that the present invention proposes fractional order circuit gene false proof detecting device employing minute resists and fractional order method of steepest descent realizes with mimic channel form.The order v of the fractional calculus the present invention relates to ₁, v _iand v _sbe not traditional integer rank, but non-integral order is generally got mark or reasonable decimal in engineering application.V ₁, v _iand v _scan equate, also can be unequal.Wherein, 1 < i < S, i and S are positive integer.See Fig. 3, i fractional order element circuit of this Anti-counterfeiting detector is by operational amplifier A p _i20, divide anti-F _i11 and resistance R _i17 form.Each fractional order element circuit all has identical circuit structure, but its circuit parameter can be different.The output terminal of S fractional order element circuit of this Anti-counterfeiting detector is by feedback resistance R _iS5 are linked to the input end of i fractional order element circuit.The output terminal of each fractional order element circuit is all linked to the input end of another fractional order element circuit in an identical manner by corresponding feedback resistance, each feedback resistance value can be different mutually.The fractional order order v of the attraction subvalue of this Anti-counterfeiting detector and its fractional order element circuit _ithis qualitative correlation, it attracts subvalue always to follow its minute anti-F _i11 resistance value and the change of capacitance and change.In fact, according to existing Electronic Components Manufacturing technological level, the mankind can not produce absolute identical two resistance of its value or electric capacity within the following long period.Yet this is but very lucky in unfortunate.The mankind likely solve certain difficult math question through great efforts, but the mankind but can not change nature physics law all the time.The faint difference of corresponding resistance value or capacitance in any two anti-chips clones' of the present invention fractional order circuit gene false proof detecting device, be exactly the mankind in its production run naturally, randomly, the fractional order circuit gene that inevitably produces.The mankind can not produce two these Anti-counterfeiting detectors with absolute identical attraction subvalue within the following long period.This Anti-counterfeiting detector is specially adapted to construct the application scenario of anti-chip clone's high-performance anti-counterfeiting chip.The invention belongs to the technical field of applied mathematics and digital circuit cross discipline.

See Fig. 3, the 1st, the input end of the 1st fractional order element circuit of anti-chip clone's of the present invention fractional order circuit gene false proof detecting device, completes the curtage input of the 1st fractional order element circuit.2 is input ends of i fractional order element circuit, completes the curtage input of i fractional order element circuit.3 is input ends of S fractional order element circuit, completes the curtage input of S fractional order element circuit.The 4th, the feedback resistance R of the link output terminal of S fractional order element circuit and the input end of the 1st fractional order element circuit _1S, the output terminal of S fractional order element circuit is by feedback resistance R _1S4 are linked to the input end of the 1st fractional order element circuit.The 5th, the feedback resistance R of the link output terminal of S fractional order element circuit and the input end of i fractional order element circuit _iS, the output terminal of S fractional order element circuit is by feedback resistance R _iS5 are linked to the input end of i fractional order element circuit.The 6th, the feedback resistance R of the link output terminal of i fractional order element circuit and the input end of the 1st fractional order element circuit _1i, the output terminal of i fractional order element circuit is by feedback resistance R _1i6 are linked to the input end of the 1st fractional order element circuit.The 7th, the feedback resistance R of the link output terminal of i fractional order element circuit and the input end of S fractional order element circuit _si, the output terminal of i fractional order element circuit is by feedback resistance R _si7 are linked to the input end of S fractional order element circuit.The 8th, link the feedback resistance R of the 1st output terminal of fractional order element circuit and the input end of i fractional order element circuit _i1, the output terminal of the 1st fractional order element circuit is by feedback resistance R _i18 are linked to the input end of i fractional order element circuit.The 9th, link the feedback resistance R of the 1st output terminal of fractional order element circuit and the input end of S fractional order element circuit _s1, the output terminal of the 1st fractional order element circuit is by feedback resistance R _s19 are linked to the input end of S fractional order element circuit.The 10th, minute anti-F of the 1st fractional order element circuit of anti-chip clone's of the present invention fractional order circuit gene false proof detecting device ₁, complete v ₁rank fractional order differential.The v of its input current perseverance and input voltage ₁rank differential is directly proportional.11 is minute anti-F of i fractional order element circuit _i, complete v _irank fractional order differential.The v of its input current perseverance and input voltage _irank differential is directly proportional.12 is minute anti-F of S fractional order element circuit _s, complete v _srank fractional order differential.The v of its input current perseverance and input voltage _srank differential is directly proportional.The 13rd, the earth point of the 1st fractional order element circuit of anti-chip clone's of the present invention fractional order circuit gene false proof detecting device, by the 1st fractional order element circuit ground connection.14 is earth points of i fractional order element circuit, by i fractional order element circuit ground connection.15 is earth points of S fractional order element circuit, by S fractional order element circuit ground connection.The 16th, the resistance R of the 1st fractional order element circuit of anti-chip clone's of the present invention fractional order circuit gene false proof detecting device ₁, complete minute anti-F to the 1st fractional order element circuit ₁10 carry out current distributing.Wherein, the resistance R of the 1st fractional order element circuit ₁16 can be zero, also can be non-vanishing.17 is resistance R of i fractional order element circuit _i, complete minute anti-F to i fractional order element circuit _i11 carry out current distributing.Wherein, the resistance R of i fractional order element circuit _i17 can be zero, also can be non-vanishing.18 is resistance R of S fractional order element circuit _s, complete minute anti-F to S fractional order element circuit _s12 carry out current distributing.Wherein, the resistance R of S fractional order element circuit _s18 can be zero, also can be non-vanishing.The 19th, the operational amplifier A p of the 1st fractional order element circuit of anti-chip clone's of the present invention fractional order circuit gene false proof detecting device ₁, the operational amplifier A p of the 1st fractional order element circuit ₁19 voltages that its forward or negative input A are ordered carry out non-linear amplification.20 is operational amplifier A p of i fractional order element circuit _i, the operational amplifier A p of i fractional order element circuit _i20 voltages that its forward or negative input B are ordered carry out non-linear amplification.21 is operational amplifier A p of S fractional order element circuit _s, the operational amplifier A p of S fractional order element circuit _s21 voltages that its forward or negative input C are ordered carry out non-linear amplification.The 22nd, the output terminal of the 1st fractional order element circuit of anti-chip clone's of the present invention fractional order circuit gene false proof detecting device, completes the curtage output of the 1st fractional order element circuit.23 is output terminals of i fractional order element circuit, completes the curtage output of i fractional order element circuit.24 is output terminals of S fractional order element circuit, completes the curtage output of S fractional order element circuit.

In addition, feedback resistance R _1S4, feedback resistance R _iS5, feedback resistance R _1i6, feedback resistance R _si7, feedback resistance R _i18 and feedback resistance R _s1the 9th, the feedback resistance that function is identical, but its parameter can be different.Divide anti-F ₁10, divide anti-F _i11 and a minute anti-F _sthe 12nd, dividing that function is identical is anti-, but its order v ₁, v _iand v _scan be different.Resistance R ₁16, resistance R _i17 and resistance R _sthe 18th, the resistance that function is identical, but its parameter can be different.Operational amplifier A p ₁19, operational amplifier A p _i20 and operational amplifier A p _sthe 21st, the operational amplifier that function is identical, but its parameter can be different.

See Fig. 4, i fractional order element circuit of anti-chip clone's of the present invention fractional order circuit gene false proof detecting device is by an operational amplifier A p _i20 and associated minute anti-F _i11 and resistance R _i17 form.Each fractional order element circuit all has identical circuit structure, but its circuit parameter can be different.Wherein, the resistance R of i fractional order element circuit _i17 can be zero, also can be non-vanishing.

See Fig. 3 and Fig. 4, i fractional order element circuit of anti-chip clone's of the present invention fractional order circuit gene false proof detecting device feeds back to the curtage of its output terminal 23 outputs by its feedback end 25 input end of other fractional order element circuit, in particular cases also can feed back to the input end of i fractional order element circuit.Each fractional order element circuit all feeds back to the curtage of its output terminal output the input end of other fractional order element circuit in the same way, in particular cases also feeds back to the input end of self fractional order element circuit.Thereby form the fractional order circuit gene false proof detecting device of the of the present invention anti-chip clone with fractional order multilayer dynamic feedback structure.

New departure below in conjunction with accompanying drawing and example in detail anti-chip clone's of the present invention fractional order circuit gene false proof detecting device:

Accompanying drawing explanation

Fig. 1 is the principle schematic of fractional order element circuit of anti-chip clone's of the present invention fractional order circuit gene false proof detecting device.

Fig. 2 is the principle schematic of anti-chip clone's of the present invention fractional order circuit gene false proof detecting device.

Fig. 3 is the circuit diagram of anti-chip clone's of the present invention fractional order circuit gene false proof detecting device.

Fig. 4 is the circuit diagram of i fractional order element circuit of anti-chip clone's of the present invention fractional order circuit gene false proof detecting device.

Wherein, the 1st, the input end of the 1st fractional order element circuit of anti-chip clone's of the present invention fractional order circuit gene false proof detecting device; 2 is input ends of i fractional order element circuit; 3 is input ends of S fractional order element circuit; The 4th, the feedback resistance R of the link output terminal of S fractional order element circuit and the input end of the 1st fractional order element circuit _1S; The 5th, the feedback resistance R of the link output terminal of S fractional order element circuit and the input end of i fractional order element circuit _iS; The 6th, the feedback resistance R of the link output terminal of i fractional order element circuit and the input end of the 1st fractional order element circuit _1i; The 7th, the feedback resistance R of the link output terminal of i fractional order element circuit and the input end of S fractional order element circuit _si; The 8th, link the feedback resistance R of the 1st output terminal of fractional order element circuit and the input end of i fractional order element circuit _i1; The 9th, link the feedback resistance R of the 1st output terminal of fractional order element circuit and the input end of S fractional order element circuit _s1; The 10th, minute anti-F of the 1st fractional order element circuit of anti-chip clone's of the present invention fractional order circuit gene false proof detecting device ₁; 11 is minute anti-F of i fractional order element circuit _i; 12 is minute anti-F of S fractional order element circuit _s; The 13rd, the earth point of the 1st fractional order element circuit of anti-chip clone's of the present invention fractional order circuit gene false proof detecting device; 14 is earth points of i fractional order element circuit; 15 is earth points of S fractional order element circuit; The 16th, the resistance R of the 1st fractional order element circuit of anti-chip clone's of the present invention fractional order circuit gene false proof detecting device ₁; 17 is resistance R of i fractional order element circuit _i; 18 is resistance R of S fractional order element circuit _s; The 19th, the operational amplifier A p of the 1st fractional order element circuit of anti-chip clone's of the present invention fractional order circuit gene false proof detecting device ₁; 20 is operational amplifier A p of i fractional order element circuit _i; 21 is operational amplifier A p of S fractional order element circuit _s; The 22nd, the output terminal of the 1st fractional order element circuit of anti-chip clone's of the present invention fractional order circuit gene false proof detecting device; 23 is output terminals of i fractional order element circuit; 24 is output terminals of S fractional order element circuit; The 25th, the feedback end of i fractional order element circuit of anti-chip clone's of the present invention fractional order circuit gene false proof detecting device.In addition, 4,5,6,7,8 and 9 is feedback resistances that function is identical, but its parameter can be different; 10,11 and 12 is that identical the dividing of function resists, but its order can be different; 16,17 and 18 is the resistance that function is identical, but its parameter can be different; 19,20 and 21 is operational amplifiers that function is identical, but its parameter can be different.

Wherein, symbol i ₁(t) represent the input current of the 1st fractional order element circuit of the fractional order circuit gene false proof detecting device that anti-chip of the present invention is cloned; Symbol i _i(t) represent the input current of i fractional order element circuit; Symbol i _s(t) represent the input current of S fractional order element circuit; Symbol R _1Sthe feedback resistance that represents the link output terminal of S fractional order element circuit and the input end of the 1st fractional order element circuit; Symbol R _iSthe feedback resistance that represents the link output terminal of S fractional order element circuit and the input end of i fractional order element circuit; Symbol R _1ithe feedback resistance that represents the link output terminal of i fractional order element circuit and the input end of the 1st fractional order element circuit; Symbol R _sithe feedback resistance that represents the link output terminal of i fractional order element circuit and the input end of S fractional order element circuit; Symbol R _i1the feedback resistance that represents the 1st output terminal of fractional order element circuit of link and the input end of i fractional order element circuit; Symbol R _s1the feedback resistance that represents the 1st output terminal of fractional order element circuit of link and the input end of S fractional order element circuit; Symbol F ₁resist the dividing of the 1st fractional order element circuit that represents anti-chip clone's of the present invention fractional order circuit gene false proof detecting device; Symbol F _irepresent that dividing of i fractional order element circuit is anti-; Symbol F _srepresent that dividing of S fractional order element circuit is anti-; Symbol R ₁the resistance that represents the 1st fractional order element circuit of the fractional order circuit gene false proof detecting device that anti-chip of the present invention is cloned; Symbol R _ithe resistance that represents i fractional order element circuit; Symbol R _sthe resistance that represents S fractional order element circuit; Symbol n ₁(t) represent the input voltage of operational amplifier of the 1st fractional order element circuit of anti-chip clone's of the present invention fractional order circuit gene false proof detecting device; Symbol n _i(t) represent the input voltage of the operational amplifier of i fractional order element circuit; Symbol n _s(t) represent the input voltage of the operational amplifier of S fractional order element circuit; Symbol Ap ₁the operational amplifier that represents the 1st fractional order element circuit of the fractional order circuit gene false proof detecting device that anti-chip of the present invention is cloned; Symbol Ap _ithe operational amplifier that represents i fractional order element circuit; Symbol Ap _sthe operational amplifier that represents S fractional order element circuit; Symbol a ₁(t) represent the output voltage of the 1st fractional order element circuit of the fractional order circuit gene false proof detecting device that anti-chip of the present invention is cloned; Symbol a _i(t) represent the output voltage of i fractional order element circuit; Symbol a _s(t) represent the output voltage of S fractional order element circuit.

Wherein, A point is forward or the negative input of operational amplifier of the 1st fractional order element circuit of anti-chip clone's of the present invention fractional order circuit gene false proof detecting device; B point is forward or the negative input of the operational amplifier of i fractional order element circuit; C point is forward or the negative input of the operational amplifier of S fractional order element circuit.

Embodiment

Now be described below for example:

See Fig. 3 and Fig. 4, in practical implementation, the order v of the fractional calculus that anti-chip clone's of the present invention fractional order circuit gene false proof detecting device relates to ₁, v ₂and v ₃be not traditional integer rank, but non-integral order is generally got mark or reasonable decimal.V ₁, v _iand v _scan equate, also can be unequal.Wherein, 1 < i < S, i and S are positive integer.

The first, construct the fractional order circuit gene false proof detecting device that two-dimentional anti-chip is cloned.The fractional order circuit gene false proof detecting device of supposing anti-chip clone of the present invention only has two fractional order element circuits.Therefore, S=2.From Fig. 3 and Fig. 4, the output terminal of arbitrary fractional order element circuit of this anti-chip clone's fractional order circuit gene false proof detecting device all feeds back to the input end of another fractional order element circuit by feedback resistance.Therefore, the present invention makes R _1,2=R _2,1=1 Ω (ohm), R _1,1=R _2,2=∞ Ω.In Fig. 3, make the R of fractional order element circuit of this anti-chip clone's fractional order circuit gene false proof detecting device ₁=R ₂=R=1 Ω and i ₁=i ₂=0.So can obtain T _1,2=T _2,1=1s (Siemens), T _1,1=T _2,2=0s, Z ₁=Z ₂=1/2 and b ₁=b ₂=0.In addition, the present invention's order minute resists in r=1 Ω and c=1nF (nanofarad).So can obtain, χ ₁=χ ₂=Z ₁k=Z ₂k=1/2, w _1,2=w _2,1=1/2 and w _1,1=w _2,2=0.The weight matrix of the fractional order circuit gene false proof detecting device that therefore, the present invention can this anti-chip clone is $W=\left[\begin{array}{cc}0& 1/2\\ 1/2& 0\end{array}\right].$ Suppose operational amplifier A p ₁and Ap ₂transport function be f (τ)=2/ π tan ^-1(γ π τ/2).So, can obtain respectively $a_1\left(t\right)=\frac{2}{\mathrm{\&pi;}}{\tan }^{-1}\left[\frac{{\mathrm{\&gamma;\&pi;n}}_1\left(t\right)}{2}\right],$ $a_2\left(t\right)=\frac{2}{\mathrm{\&pi;}}{\tan }^{-1}\left[\frac{{\mathrm{\&gamma;\&pi;n}}_2\left(t\right)}{2}\right],$ $n_1\left(t\right)=\frac{2}{\mathrm{\&gamma;\&pi;}}\tan \frac{{\mathrm{\&pi;a}}_1\left(t\right)}{2}$ With $n_2\left(t\right)=\frac{2}{\mathrm{\&gamma;\&pi;}}\tan \frac{{\mathrm{\&pi;a}}_2\left(t\right)}{2}.$ Wherein, γ is operational amplifier A p ₁and Ap ₂the gain coefficient of transport function.So the state equation that can obtain anti-chip clone's of the present invention fractional order circuit gene false proof detecting device is respectively $\frac{d^{v_1}{n}_1\left(t\right)}{{\mathrm{dt}}^{v_1}}=-2n_1\left(t\right)+a_2\left(t\right)$ With $\frac{d^{v_2}{n}_2\left(t\right)}{{\mathrm{dt}}^{v_2}}=-2n_2\left(t\right)+a_1\left(t\right).$

The second, construct the fractional order circuit gene false proof detecting device that three-dimensional anti-chip is cloned.The fractional order circuit gene false proof detecting device of supposing anti-chip clone of the present invention has three fractional order element circuits.Therefore, S=3.For fear of arbitrary angle at 8 angles of hypercube, become the saddle point of this anti-chip clone's fractional order circuit gene false proof detecting device, the present invention is set to unsymmetrical matrix by the weight matrix W of this anti-chip clone's fractional order circuit gene false proof detecting device.In order to keep the symmetry of circuit structure of this anti-chip clone's fractional order circuit gene false proof detecting device, the present invention makes R _1,2=R _2,1=1 Ω, R _1,3=R _3,1=2 Ω, R _2,3=R _3,2=3 Ω, R _1,1=R _2,2=R _3,3=∞ Ω.R with the fractional order element circuit of anti-chip clone's of the present invention fractional order circuit gene false proof detecting device in seasonal Fig. 3 ₁=R ₂=R ₃=R=1 Ω, i ₁=i ₂=i ₃=0.So can obtain T _1,2=T _2,1=1s, T _1,3=T _3,1=1/2s, T _2,3=T _3,2=1/3s, T _1,1=T _2,2=T _3,3=0s, b ₁=b ₂=b ₃=0.In addition, the present invention also makes minute anti- r=1 Ω, c=1nF.So can obtain Z ₁=2/5, Z ₂=3/7, Z ₃=6/11, χ ₁=Z ₁k=2/5, χ ₂=Z ₂k=3/7, χ ₃=Z ₃k=6/11, w _1,2=2/5, w _1,3=1/5, w _2,1=3/7, w _2,3=1/7, w _3,1=3/11, w _3,2=2/11 and w _1,1=w _2,2=w _3,3=0.The weight matrix that therefore, can obtain anti-chip clone's of the present invention fractional order circuit gene false proof detecting device is $W=\left[\begin{array}{ccc}0& 2/5& 1/5\\ 3/7& 0& 1/7\\ 3/11& 2/11& 0\end{array}\right].$ So the state equation that can obtain anti-chip clone's of the present invention fractional order circuit gene false proof detecting device is respectively $\frac{d^{v_1}{n}_1\left(t\right)}{{\mathrm{dt}}^{v_1}}=-\frac{5}{2}{n}_1\left(t\right)+a_2\left(t\right)+\frac{1}{2}{a}_3\left(t\right),$ $\frac{d^{v_2}{n}_2\left(t\right)}{{\mathrm{dt}}^{v_2}}=-\frac{7}{3}{n}_2\left(t\right)+a_1\left(t\right)+\frac{1}{3}{a}_3\left(t\right)$ With $\frac{d^{v_3}{n}_3\left(t\right)}{{\mathrm{dt}}^{v_3}}=-\frac{11}{6}{n}_3\left(t\right)+\frac{1}{2}{a}_1\left(t\right)+\frac{1}{3}{a}_2\left(t\right).$

In like manner, can construct easily the anti-chip clone's of other dimension fractional order circuit gene false proof detecting device.So, as shown in Figure 3 and Figure 4, according to circuit structure and the physical circuit parameter thereof of the of the present invention anti-chip clone's who describes in detail in the summary of the invention of this instructions fractional order circuit gene false proof detecting device, just can construct easily the physical circuit of this anti-chip clone's fractional order circuit gene false proof detecting device.Do not affecting under the prerequisite of accurate statement, for more clear the physical circuit of describing anti-chip clone's of the present invention fractional order circuit gene false proof detecting device, Fig. 3 and Fig. 4 do not draw signal generating circuit and power supply wherein.

Claims (5)

1. anti-chip clone's fractional order circuit gene false proof detecting device, is characterized in that: this anti-chip clone's fractional order circuit gene false proof detecting device employing minute resists and fractional order method of steepest descent realizes with mimic channel form; I fractional order element circuit of this anti-chip clone's fractional order circuit gene false proof detecting device is by operational amplifier A p _i(20), divide anti-F _iand resistance R (11) _i(17) form; Each fractional order element circuit all has identical circuit structure, but its circuit parameter can be different; The output terminal of S fractional order element circuit of this anti-chip clone's fractional order circuit gene false proof detecting device is by feedback resistance R _iS(5) be linked to the input end of i fractional order element circuit; The output terminal of each fractional order element circuit is all linked to the input end of another fractional order element circuit in an identical manner by corresponding feedback resistance, each feedback resistance value can be different mutually; This anti-chip clone's the attraction subvalue of fractional order circuit gene false proof detecting device and the fractional order order v of its fractional order element circuit _ithis qualitative correlation, it attracts subvalue always to follow its minute anti-F _i(11) resistance value and the change of capacitance and change; Wherein, the order v of fractional calculus ₁, v _iand v _sbe not traditional integer rank, but non-integral order is generally got mark or reasonable decimal in engineering application; v ₁, v _iand v _scan equate, also can be unequal; Wherein, 1 < i < S, i and S are positive integer.

2. the fractional order circuit gene false proof detecting device that anti-chip according to claim 1 is cloned, it is characterized in that: the input end (1) of the 1st fractional order element circuit of this anti-chip clone's fractional order circuit gene false proof detecting device, completes the curtage input of the 1st fractional order element circuit; The input end of its i fractional order element circuit (2), completes the curtage input of i fractional order element circuit; The input end of its S fractional order element circuit (3), completes the curtage input of S fractional order element circuit; The output terminal of its S fractional order element circuit is by feedback resistance R _1S(4) be linked to the input end of the 1st fractional order element circuit; The output terminal of its S fractional order element circuit is by feedback resistance R _iS(5) be linked to the input end of i fractional order element circuit; The output terminal of its i fractional order element circuit is by feedback resistance R _1i(6) be linked to the input end of the 1st fractional order element circuit; The output terminal of its i fractional order element circuit is by feedback resistance R _si(7) be linked to the input end of S fractional order element circuit; The output terminal of its 1st fractional order element circuit is by feedback resistance R _i1(8) be linked to the input end of i fractional order element circuit; The output terminal of its 1st fractional order element circuit is by feedback resistance R _s1(9) be linked to the input end of S fractional order element circuit; Minute anti-F of the 1st fractional order element circuit of this anti-chip clone's fractional order circuit gene false proof detecting device ₁(10), complete v ₁rank fractional order differential; The v of its input current perseverance and input voltage ₁rank differential is directly proportional; Minute anti-F of its i fractional order element circuit _i(11), complete v _irank fractional order differential; The v of its input current perseverance and input voltage _irank differential is directly proportional; Minute anti-F of its S fractional order element circuit _s(12), complete v _srank fractional order differential; The v of its input current perseverance and input voltage _srank differential is directly proportional; The earth point (13) of the 1st fractional order element circuit of this anti-chip clone's fractional order circuit gene false proof detecting device, by the 1st fractional order element circuit ground connection; The earth point of its i fractional order element circuit (14), by i fractional order element circuit ground connection; The earth point of its S fractional order element circuit (15), by S fractional order element circuit ground connection; The resistance R of the 1st fractional order element circuit of this anti-chip clone's fractional order circuit gene false proof detecting device ₁(16), complete minute anti-F to the 1st fractional order element circuit ₁(10) carry out current distributing; Wherein, the resistance R of the 1st fractional order element circuit ₁(16) can be zero, also can be non-vanishing; The resistance R of its i fractional order element circuit _i(17), complete minute anti-F to i fractional order element circuit _i(11) carry out current distributing; Wherein, the resistance R of i fractional order element circuit _i(17) can be zero, also can be non-vanishing; The resistance R of its S fractional order element circuit _s(18), complete minute anti-F to S fractional order element circuit _s(12) carry out current distributing; Wherein, the resistance R of S fractional order element circuit _s(18) can be zero, also can be non-vanishing; The operational amplifier A p of the 1st fractional order element circuit of this anti-chip clone's fractional order circuit gene false proof detecting device ₁(19) voltage of its forward or negative input (A) is carried out to non-linear amplification; The operational amplifier A p of its i fractional order element circuit _i(20) voltage of its forward or negative input (B) is carried out to non-linear amplification; The operational amplifier A p of its S fractional order element circuit _s(21) voltage of its forward or negative input (C) is carried out to non-linear amplification; The output terminal (22) of the 1st fractional order element circuit of this anti-chip clone's fractional order circuit gene false proof detecting device, completes the curtage output of the 1st fractional order element circuit; The output terminal of its i fractional order element circuit (23), completes the curtage output of i fractional order element circuit; The output terminal of its S fractional order element circuit (24), completes the curtage output of S fractional order element circuit.

3. anti-chip clone's according to claim 1 fractional order circuit gene false proof detecting device, is characterized in that: feedback resistance R wherein _1S(4), feedback resistance R _iS(5), feedback resistance R _1i(6), feedback resistance R _si(7), feedback resistance R _i1and feedback resistance R (8) _s1(9) be the feedback resistance that function is identical, but its parameter can be different; Divide anti-F ₁(10), divide anti-F _iand minute anti-F (11) _s(12) be that identical the dividing of function resists, but its order v ₁, v _iand v _scan be different; Resistance R ₁(16), resistance R _iand resistance R (17) _s(18) be the resistance that function is identical, but its parameter can be different; Operational amplifier A p ₁(19), operational amplifier A p _iand operational amplifier A p (20) _s(21) be the operational amplifier that function is identical, but its parameter can be different.

4. anti-chip clone's according to claim 1 fractional order circuit gene false proof detecting device, is characterized in that: i fractional order element circuit of this anti-chip clone's fractional order circuit gene false proof detecting device is by an operational amplifier A p _iand associated minute anti-F (20) _iand resistance R (11) _i(17) form; Each fractional order element circuit all has identical circuit structure, but its circuit parameter can be different; Wherein, the resistance R of i fractional order element circuit _i(17) can be zero, also can be non-vanishing.

5. the fractional order circuit gene false proof detecting device that anti-chip according to claim 1 is cloned, it is characterized in that: i fractional order element circuit of this anti-chip clone's fractional order circuit gene false proof detecting device feeds back to the curtage of its output terminal (23) output by its feedback end (25) input end of other fractional order element circuit, in particular cases also can feed back to the input end of i fractional order element circuit; Each fractional order element circuit all feeds back to the curtage of its output terminal output the input end of other fractional order element circuit in the same way, in particular cases also feeds back to the input end of self fractional order element circuit; Thereby form the fractional order circuit gene false proof detecting device of this anti-chip clone with fractional order multilayer dynamic feedback structure.