CN103974069A - Reusable video coding method and encoder - Google Patents
Reusable video coding method and encoder Download PDFInfo
- Publication number
- CN103974069A CN103974069A CN201410219372.3A CN201410219372A CN103974069A CN 103974069 A CN103974069 A CN 103974069A CN 201410219372 A CN201410219372 A CN 201410219372A CN 103974069 A CN103974069 A CN 103974069A
- Authority
- CN
- China
- Prior art keywords
- inter prediction
- predicting unit
- image
- prediction parameter
- result
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000000034 method Methods 0.000 title claims abstract description 58
- 238000012545 processing Methods 0.000 claims abstract description 82
- 230000000694 effects Effects 0.000 claims abstract description 30
- 230000000052 comparative effect Effects 0.000 claims description 13
- 238000002203 pretreatment Methods 0.000 claims description 13
- 230000001186 cumulative effect Effects 0.000 claims description 7
- 230000006872 improvement Effects 0.000 abstract description 4
- 230000008569 process Effects 0.000 description 26
- 230000006835 compression Effects 0.000 description 12
- 238000007906 compression Methods 0.000 description 12
- 150000001875 compounds Chemical class 0.000 description 11
- 230000014509 gene expression Effects 0.000 description 10
- 238000010586 diagram Methods 0.000 description 8
- 230000008859 change Effects 0.000 description 7
- 238000013461 design Methods 0.000 description 5
- 238000004364 calculation method Methods 0.000 description 3
- 238000006243 chemical reaction Methods 0.000 description 3
- 230000008030 elimination Effects 0.000 description 3
- 238000003379 elimination reaction Methods 0.000 description 3
- 238000013139 quantization Methods 0.000 description 3
- 230000000007 visual effect Effects 0.000 description 3
- 230000005540 biological transmission Effects 0.000 description 2
- 230000033001 locomotion Effects 0.000 description 2
- 238000011002 quantification Methods 0.000 description 2
- 230000000153 supplemental effect Effects 0.000 description 2
- 238000013459 approach Methods 0.000 description 1
- 238000005284 basis set Methods 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 239000003086 colorant Substances 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
- 238000005192 partition Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 238000012795 verification Methods 0.000 description 1
Landscapes
- Compression Or Coding Systems Of Tv Signals (AREA)
Abstract
The embodiment of the invention provides a reusable video coding method and an encoder. The reusable video coding method comprises the steps of obtaining a frame of image; obtaining the processing sequence of a predicating unit for performing inter-frame prediction on the image according to the preset inter-frame predication parameters, wherein the inter-frame predication parameters comprise an inter-frame predication mode, the position of the predication unit, the type of the predication unit, processing time control information of the predication unit, a predication effect comparison algorithm, next-time predication skip information and ending tags; performing inter-frame predication on the corresponding positions of the image and the predication unit in sequence according to the processing sequence of the predication unit, and encoding the image according to the inter-frame predication result. The method solves the problem that a PU selection algorithm is fixed and single, and when application scenarios are changed to enable the PU type and the processing sequence to be changed, the method can adapt to new scenarios only when hardware is modified, and improvement and expanding of a coding system are not facilitated.
Description
Technical field
The embodiment of the present invention relates to video compression technology, relates in particular to a kind of reusable method for video coding and encoder.
Background technology
In recent years, information technology develops rapidly, and people require to improve constantly to the visual quality of video, and the appearance of high definition, ultra high-definition and 3D video is subject to everybody extensive favor.But, the high-definition image uncompressed of a 720P takies 2.2 Mbytes (MByte, be called for short MB) memory space, if the frame rate of a video was 30 frame/seconds, even if only have five minutes, data volume also will reach 19 GB (GigaByte, be called for short GB), the shared data volume of high-quality video of the visible people's of meeting demand is very huge, the original video data of uncompressed is all difficult to accept now even in the future, is that storage or transmission all exist very large problem.
In video data, exist a large amount of redundancies, redundancy mainly comprises following a few class, spatial redundancy, if for example have larger background area in piece image, the pixel value in these regions is closely similar so; Time redundancy, between the former frame in the successive frame of video sequence and a rear frame, conversion is little conventionally, has very strong similitude, and the main distinction is just only slightly different on the locus of moving object between different frame; Statistical redundancy, adopts different coding methods to carry out entropy coding to information, and the bit number of the whole symbol sebolic addressing of encoding will be not quite alike; Visual redundancy, the vision system of human eye is defective, it is not can both identify all colors, contrast and frequency, the therefore precision of suitable reduction image, human eye can't be perceived, and can reach the object of amount of compressed data simultaneously.Known the reason that produces redundancy, just can adopt corresponding method to carry out redundancy elimination, realized video compression, the principle of video compression coding and starting point are just to eliminate to greatest extent various redundancies.Specifically, for different redundancies, video compression coding standard adopts different strategies to eliminate, and for example, eliminates time redundancy with inter prediction; Eliminate spatial redundancy with infra-frame prediction; By conversion, quantification elimination visual redundancy; By entropy coding elimination statistical redundancy.
As mentioned above, the object of video compression coding is the space of code stream or the store video of saving transmission of video, and the processing procedure of video can comprise following step: the 1) collection of video, and the collection of video is obtained by image acquisition equipments such as video cameras; 2) coding of video, carries out compression coding to video sequence, obtains corresponding video code flow; 3) video code flow after compression coding is transmitted or stored; 4) video code flow obtaining is decoded, obtain decoded video; 5) user utilizes display device to play video, wherein, the 2nd) Video coding of step mainly comprises prediction (infra-frame prediction and inter prediction), change quantization and coding.
Efficient video coding (High Efficiency Video Coding, being called for short HEVC) (H.265) technology is as video encoding standard of new generation, be devoted to code efficiency to improve 50% than advanced video coding (AdvancedVideo Coding is called for short AVC).Inter prediction is memory access and Calculation bottleneck main in video compression coding, in order to improve the accuracy of inter prediction, in HEVC standard, increase merging (merge) predictive mode, merge pattern is by the whole motion compensated area that comprises multiple adjacent blocks being used to single movement parametric degree, removing the redundancy on kinematic parameter.In order to select optimum predictive mode from all merge patterns of inter prediction, need to carry out the operation of multiple spot merge pattern to all predicting unit (Prediction Unit is called for short PU).HEVC standard has expanded to 64 × 64 by macro block from 16 × 16, be convenient to the compression of high-resolution video, adopt coding unit (Coding Unit simultaneously, be called for short CU), predicting unit (Prediction Unit, be called for short PU) and converter unit (Transform Unit is called for short TU) coding structure improve code efficiency, wherein, CU is for cataloged procedure, and PU is the elementary cell of predicting, TU is the elementary cell of carrying out transform and quantization.
But, in current implementation, be according to image applications Scenario Design merge pattern, its hardware configuration and concrete application scenarios close-coupled, in the time of logic realization, design fixing PU processing sequence, and by the processing of state machine control PU, can cause like this PU selection algorithm to be fixed and single, when application scenarios changes when PU type and processing sequence are changed, must carry out hardware change and could adapt to new scene, be unfavorable for coded system improvement in performance and expansion.
Summary of the invention
The embodiment of the present invention provides a kind of reusable method for video coding and encoder, to solve that PU selection algorithm is fixed and single, in the time that PU processing sequence changes, must carry out hardware change and just can complete the problem of PU order upgrading.
First aspect, the embodiment of the present invention provides a kind of reusable method for video coding, comprising:
Obtain a two field picture;
According to the inter prediction parameter acquiring setting in advance, described image is carried out the processing sequence of the predicting unit of inter prediction, described inter prediction parameter comprises inter-frame forecast mode, the position of predicting unit, the type of predicting unit, the processing time control information of predicting unit, prediction effect comparison algorithm, predict jump information next time and finish mark, wherein, described inter-frame forecast mode is used to indicate the reconnaissance mode of carrying out described inter prediction, the position of described predicting unit is used to indicate described predicting unit residing position in coding unit layer, the processing time control information of described predicting unit is used to indicate the duration that carries out inter prediction on the described image position corresponding with described predicting unit, described prediction effect comparison algorithm is used to indicate the algorithm of the result of more described inter prediction, describedly predicts that jump information is used to indicate the described coding unit layer that next time carries out described inter prediction next time,
On the described image position corresponding with described predicting unit, carry out inter prediction successively according to the processing sequence of described predicting unit, and according to the result of described inter prediction, described image is encoded.
In conjunction with first aspect, in the possible implementation of the first of first aspect, describedly on the described image position corresponding with described predicting unit, carry out inter prediction successively according to the processing sequence of described predicting unit, and according to the result of described inter prediction, described image is encoded, comprising:
Obtain successively described inter prediction parameter corresponding to pending described predicting unit according to the processing sequence of described predicting unit, on the described image position corresponding with described predicting unit, carry out inter prediction according to described inter prediction parameter;
According to the result of described inter prediction, described image is encoded.
In conjunction with the possible implementation of the first of first aspect or first aspect, in the possible implementation of the second of first aspect, describedly obtain successively described inter prediction parameter corresponding to pending described predicting unit according to the processing sequence of described predicting unit, on the described image position corresponding with described predicting unit, carry out inter prediction according to described inter prediction parameter, comprising:
Obtain successively described inter prediction parameter corresponding to pending described predicting unit according to the processing sequence of described predicting unit, and determine the position of described predicting unit correspondence in described image according to the type of the position of described predicting unit, predicting unit;
In described image, on corresponding position, carry out described inter prediction according to the processing time control information of described inter-frame forecast mode, predicting unit, and described in determining by the processing time control information of described predicting unit, carry out the duration of described inter prediction;
Determine the algorithm of the result of more described inter prediction according to described prediction effect comparison algorithm, and according to described prediction effect comparison algorithm, the result of described inter prediction is processed and obtained comparative result.
In conjunction with the possible implementation of the second of first aspect, in the third possible implementation of first aspect, describedly according to the result of described inter prediction, described image is encoded, comprising:
Determine coded system and described image is encoded according to described comparative result.
In conjunction with the second of first aspect, first aspect to any possible implementation in the second, in the 4th kind of possible implementation of first aspect, described in obtain a two field picture before, also comprise:
Set in advance described inter prediction parameter according to image applications scene or hardware capabilities, and preserve described inter prediction parameter.
Second aspect, the embodiment of the present invention provides a kind of encoder, comprising: processor, memory and addressable controller;
Described memory, for store video images and inter prediction parameter, described inter prediction parameter comprise type, the predicting unit of position, the predicting unit of inter-frame forecast mode, predicting unit processing time control information, prediction effect comparison algorithm, predict jump information and finish mark next time;
Described processor, for obtaining a two field picture from described memory, carries out inter prediction according to the described inter prediction parameter setting in advance to described image, and according to the result of described inter prediction, described image is encoded;
Described addressable controller, for carrying out addressing of address at described memory to described inter prediction parameter.
In conjunction with second aspect, in the possible implementation of the first of second aspect, described addressing register, specifically for working as the base address of the coding unit layer of pre-treatment, the base address of predicting unit combination according to described inter prediction parameter acquiring; The cumulative quantity of obtaining the predicting unit of processing; The quantity of the base address of described coding unit layer, the base address of predicting unit combination and the predicting unit of described processing is carried out to address and add up, obtain the address of pending described inter prediction parameter in described memory;
Described processor, specifically for according to described pending described inter prediction parameter, the address in described memory obtains described pending inter prediction parameter from described memory, and according to described pending inter prediction parameter, described image is carried out to inter prediction, and according to the result of described inter prediction, described image is encoded.
Also comprise:
Trigger, cumulative and in described memory addressing for triggering the quantity of described addressable controller.
In conjunction with the first of second aspect, second aspect to any possible implementation in the second, in the third possible implementation of second aspect, described processor, specifically for determining the position of described predicting unit correspondence in described image according to the type of the position of described predicting unit, predicting unit; In described image, on corresponding position, carry out described inter prediction according to the processing time control information of described inter-frame forecast mode, predicting unit, and described in determining by the processing time control information of described predicting unit, carry out the duration of described inter prediction; Determine the algorithm of the result of more described inter prediction according to described prediction effect comparison algorithm, and according to described prediction effect comparison algorithm, the result of described inter prediction is processed and obtained comparative result; Determine coded system and described image is encoded according to described comparative result.
The reusable method for video coding of the embodiment of the present invention and encoder, by the operating process of the predicting unit PU that carries out inter prediction designing in advance according to image applications scene and hardware capabilities is formed to inter prediction parameter, and by this inter prediction parameter read-in memory, read again inter prediction parameter acquiring and carry out the parameter information of HEVC coding, and carry out HEVC and encode, realize the application scenarios of HEVC coding and the decoupling zero of hardware configuration, solution PU selection algorithm is fixed and is single, in the time that application scenarios change changes PU type and processing sequence, hardware change must be carried out and new scene could be adapted to, be unfavorable for the problem of coded system improvement in performance and expansion.
Brief description of the drawings
In order to be illustrated more clearly in the embodiment of the present invention or technical scheme of the prior art, to the accompanying drawing of required use in embodiment or description of the Prior Art be briefly described below, apparently, accompanying drawing in the following describes is some embodiments of the present invention, for those of ordinary skill in the art, do not paying under the prerequisite of creative work, can also obtain according to these accompanying drawings other accompanying drawing.
Fig. 1 is the flow chart of the reusable method for video coding embodiment of the present invention;
Fig. 2 is CU structural representation of the present invention;
Fig. 3 A is PU structural representation one of the present invention;
Fig. 3 B is PU structural representation two of the present invention;
Fig. 3 C is PU structural representation three of the present invention;
Fig. 3 D is PU structural representation four of the present invention;
Fig. 4 is PU compound mode schematic diagram of the present invention;
Fig. 5 is PU execution sequence schematic diagram of the present invention;
Fig. 6 is inter prediction supplemental characteristic form schematic diagram of the present invention;
Fig. 7 is the structural representation of encoder embodiment mono-of the present invention;
Fig. 8 is the structural representation of encoder embodiment bis-of the present invention;
Fig. 9 is the structural representation of encoder embodiment tri-of the present invention;
Figure 10 be encoder of the present invention read address control module structural representation;
Figure 11 is the comparison algorithm modular structure schematic diagram of encoder of the present invention;
Figure 12 is the flow chart that encoder of the present invention is realized efficient video coding.
Embodiment
For making object, technical scheme and the advantage of the embodiment of the present invention clearer, below in conjunction with the accompanying drawing in the embodiment of the present invention, technical scheme in the embodiment of the present invention is clearly and completely described, obviously, described embodiment is the present invention's part embodiment, instead of whole embodiment.Based on the embodiment in the present invention, those of ordinary skill in the art, not making the every other embodiment obtaining under creative work prerequisite, belong to the scope of protection of the invention.
The present invention is in order to improve the real-time of HEVC video compression coding, on encoder, pass through field programmable gate array (Field Programmable Gate Array, be called for short FPGA) or application-specific integrated circuit (ASIC) (Application Specific Integrated Circuit, be called for short ASIC) realize HEVC video compression coding, it is reusable that the programmable characteristic of FPGA or ASIC makes the inter prediction process of merge pattern, can adjust in real time number and the order of PU according to application scenarios and hardware capabilities, can meet different application schemes, by hardware configuration, from application scenarios, decoupling zero is out, improve greatly the flexibility that merge realizes.
Fig. 1 is the flow chart of the reusable method for video coding embodiment of the present invention, and as shown in Figure 1, the method for the present embodiment can comprise:
Step 101, obtain a two field picture;
In the present embodiment, image is taken and is preserved by camera head, and encoder can directly get image from local memory.
The inter prediction parameter acquiring that step 102, basis set in advance is carried out the processing sequence of the predicting unit of inter prediction to image;
In the present embodiment, inter prediction parameter comprise type, the predicting unit of position, the predicting unit of inter-frame forecast mode, predicting unit processing time control information, prediction effect comparison algorithm, predict jump information and finish mark next time, wherein, inter-frame forecast mode is used to indicate the reconnaissance mode of carrying out inter prediction, the position of predicting unit is used to indicate predicting unit residing position in coding unit layer, and the processing time control information of predicting unit is used to indicate the duration that carries out inter prediction on the image position corresponding with predicting unit; Prediction effect comparison algorithm is used to indicate the algorithm of the result of comparison inter prediction, predicts that jump information is used to indicate the coding unit layer that next time carries out inter prediction next time.
For the more effective compression of carrying out data, HEVC has adopted mode more flexibly to represent block structure: CU, PU and converter unit, wherein, CU predicts, conversion, the elementary cell of quantification and entropy coding, maximum CU is 64 × 64, minimum coding unit is 8 × 8, HEVC takes the mode of quaternary tree iteration to carry out the division of CU, the shape of CU must be foursquare, the size that is four pieces of quad-tree partition is duplicate, Fig. 2 is CU structural representation of the present invention, as shown in Figure 2, comprise altogether four layers of CU layer, respectively 64 × 64, 32 × 32, 16 × 16 and 8 × 8, PU is the elementary cell of predicting, its shape can not be foursquare, a CU can comprise one or more PU, Fig. 3 A is PU structural representation one of the present invention, Fig. 3 B is PU structural representation two of the present invention, Fig. 3 C is PU structural representation three of the present invention, Fig. 3 D is PU structural representation four of the present invention, as shown in Fig. 3 A-3D, the PU that carries out inter prediction comprises 2N × 2N, 2N × N, tetra-kinds of patterns of N × 2N and N × N, wherein, N represent the residing CU layer of PU specification 1/2nd, for example current PU in CU layer be 32 × 32, PU2N × 2N is 32 × 32, PU2N × N is 32 × 16, PU N × 2N is 16 × 32, PU N × N is 16 × 16, converter unit is the elementary cell of carrying out transform and quantization, and its size can from 4 × 4 to 32 × 32, must be foursquare, and in the time of inter prediction, the size of converter unit can be greater than the size of PU, but can not exceed the size of CU.
Merge pattern is that PU is processed, and need to consider the order that different PU process.Fig. 4 is PU compound mode schematic diagram of the present invention, as shown in Figure 4, consider the difference of application scenarios and hardware capabilities, the merge performance difference needing, cause PU number and the also difference of order processed, for the popularity of supporting that PU selects, every one deck CU can comprise 7 kinds of PU compound modes: 1) PU2N × 2N; 2) PU2N × N; 3) PUN × 2N; 4) PU2N × 2N and PUN × 2N; 5) PU2N × 2N and PU2N × N; 6) PUN × 2N and PU2N × N; 7) PUN × 2N, PU2N × N and PU2N × 2N.Each compound mode can corresponding multiple PU operating process, comprise PU0, PU1, PU2 ... PUn, n can be any one integer that is greater than 0, it is compound mode in above-mentioned 7, no matter select which kind of compound mode to carry out inter prediction, can be according to application scenarios, hardware capabilities in the time determining the processing sequence of PU, and the demand such as encoding precision, particularly the PU pattern in this combination is sorted.
For example, Fig. 5 is PU execution sequence schematic diagram of the present invention, CU layer is 32 × 32, the PU selecting is combined as PU16 × 32 and PU32 × 32, be the above-mentioned the 4th) kind compound mode, so corresponding to CU32 × 32, the processing of PU can be carried out according to the sequence shown in Fig. 5 in PU2N × 2N and PUN × 2N compound mode, blank parts is to need the free time to go out certain periodicity, C1 is PU16 × 32, C2 is PU32 × 32, C1-0 merges (being that merge processes) 0 first point that is illustrated in selection to be in advance the merge of PU16 × 32 for the first time and to process, C1-0 merges 1 second point that is illustrated in selection in advance and does the merge processing of PU16 × 32 for the first time, C2 merges 0 first point that is illustrated in selection in advance and does the merge processing of PU32 × 32, C2 merges 1 second point that is illustrated in selection in advance and does the merge processing of PU32 × 32, C1-1 merges 0 first point that is illustrated in selection in advance and does the merge processing of PU16 × 32 for the second time, C1-1 merges 1 second point that is illustrated in selection in advance and does the merge processing of PU16 × 32 for the second time.Fig. 5 has shown the PU processing sequence of doing for CU32 × 32 layer, can realize the HEVC coding to CU32 × 32 according to this order, optionally, determining the 4th) plant after compound mode, can also carry out HEVC coding with other PU order, in addition, difference according to demand, also can determine other compound mode, for example the 1st) plant, the 3rd) plant etc., and then PU that can be corresponding different order, here final definite PU order is relevant to application scenarios and hardware capabilities, consider the pixel request of different scenes to video, the factor such as image definition and continuity, and the data processing limit that can bear of hardware maximum, design applicable PU order, and this PU order does not affect hardware configuration, be that hardware configuration in the present embodiment can be general, by coded program being write in FPGA or ASIC, get default processing sequence by coded program read memory again, and finally carry out HEVC according to this order and encode and reach the encoding efficiency of expection.
Step 103, on the described image position corresponding with described predicting unit, carry out inter prediction successively according to the processing sequence of described predicting unit, and according to the result of described inter prediction, described image is encoded.
In the present embodiment, determining after the compound mode and processing sequence of PU according to image applications scene and hardware capabilities, encoder forms inter prediction parameter according to this order, and this inter prediction parameter comprises data message corresponding to each PU choosing in HEVC encoding operation flow process.Specifically, according to the process of above-mentioned definite PU order, HEVC encoder gets the operating process of the follow-up HEVC of carrying out coding, operating process comprises how many PU numbers, in this inter prediction parameter, just comprise how many data messages, when which PU each data message be HEVC coder processes to, the instruction that this PU is corresponding, wherein, inter-frame forecast mode represents the mode of merge reconnaissance; The position of the current PU of positional representation of PU; PU type represents CU layer, PU type and the PU call number at PU place; PU processing time control information represents the processing time counter of current PU; Prediction effect comparison algorithm represents can to weigh different performance in actual applications and Different Logic realizes cost, select current PU to adopt different comparative approach in different phase, mainly comprise absolute difference and (Sum of Absolute Differences, be called for short: SAD) algorithm, definitely propagate difference and (Sum of Absolute Transformed Difference, be called for short: SATD) and squared differences and (Sum of Squared Differences, be called for short: SSD) algorithm; Predict that jump information represents to handle after current PU the CU layer information at PU to be processed place next time next time; Finish mark and represent whether current PU operation is last PU.
HEVC encoder by bus write memory, is kept at this locality by the inter prediction parameter setting in advance, so that the FPGA of follow-up HEVC encoder while carrying out coded program, can directly read the information as the PU of pre-treatment from memory.
HEVC encoder reads inter prediction parameter from memory, get the processing sequence of image being carried out to the PU of inter prediction, on the image position corresponding with PU, carry out inter prediction successively according to this PU processing sequence again, and according to the result of inter prediction, image is encoded.The FPGA of HEVC encoder is in the time of operation coded program, from memory, read inter prediction parameter, reading each time can get the information of current PU and the jump information of next PU, can realize HEVC coding according to the information coding program of these PU, implementation so repeatedly can, by being disposed one by one of all PU in the operating process of design in advance, reach the HEVC encoding efficiency of expection.
The present embodiment, by the operating process of the predicting unit PU that carries out inter prediction designing in advance according to image applications scene and hardware capabilities is formed to inter prediction parameter, and by this inter prediction parameter read-in memory, read again inter prediction parameter acquiring and carry out the parameter information of HEVC coding, and carry out HEVC and encode, realize the application scenarios of HEVC coding and the decoupling zero of hardware configuration, solution PU selection algorithm is fixed and is single, in the time that application scenarios change changes PU type and processing sequence, hardware change must be carried out and new scene could be adapted to, be unfavorable for the problem of coded system improvement in performance and expansion.
Further, Fig. 6 is inter prediction supplemental characteristic form schematic diagram of the present invention, as shown in Figure 6, data message corresponding to each PU in the operating process that inter prediction parameter comprises can be to be stored in memory with the data format of 32 bits, in this 32 bit, 5-0 bit: totally 6 bits, represent the position of PU, wherein, 5-4 bit represents the particular location of current PU in CU32 × 32 layer, for example 00 CU32 × 32 that represent the upper left corner, and 01 represents CU32 × 32 in the upper right corner, 10 represent CU32 × 32 in the lower left corner, and 11 represent CU32 × 32 in the lower right corner; 3-2 bit represents the particular location of current PU in CU16 × 16 layer; 1-0 bit represents the particular location of current PU in CU8 × 8 layer.13-8 bit: totally 6 bits, the type of expression PU, wherein, 13-12 bit represents the CU layer of current processing, and what for example pre-treatment was worked as in 00 expression is CU64 × 64, and what pre-treatment was worked as in 01 expression is CU32 × 32,10 expressions are CU16 × 16 when pre-treatment, and what pre-treatment was worked as in 11 expressions is CU8 × 8; 11-10 bit represents the pattern of PU, and for example 00 represents 2N × 2N; 01 represents PU2N × N; 10 represent PUN × 2N; 11 represent PUN × N; 9-8 bit represents PU index.17-16 bit: totally 2 bits, represent to predict jump information next time, what for example 00 expression was processed next time is CU64 × 64; What 01 expression was processed next time is CU32 × 32; What 10 expressions were processed next time is CU16 × 16; What 11 expressions were processed next time is CU8 × 8.19-18 bit: totally 2 bits, represent prediction effect comparison algorithm, for example 00 represents SAD algorithm; 01 represents SATD algorithm; 10 represent SSD algorithm.20 bits: totally 1 bit, represents to finish mark.23-21 bit: totally 3 bits, represent inter-frame forecast mode.31-24: totally 8 bits, the expression time is controlled.It should be noted that, the example that the data message form shown in Fig. 6 is data format of the present invention, this data format also can have other bit method to set up, is not specifically limited herein.
Further, in the step 103 of said method embodiment, on the described image position corresponding with described predicting unit, carry out inter prediction successively according to the processing sequence of described predicting unit, and according to the result of described inter prediction, described image is encoded, concrete implementation method can be: obtain successively described inter prediction parameter corresponding to pending described predicting unit according to the processing sequence of described predicting unit, carry out inter prediction according to described inter prediction parameter on the described image position corresponding with described predicting unit; According to the result of described inter prediction, described image is encoded.
Specifically, HEVC encoder obtains described inter prediction parameter corresponding to pending described predicting unit successively according to the processing sequence of described predicting unit, and determines the position of described predicting unit correspondence in described image according to the type of the position of described predicting unit, predicting unit; In described image, on corresponding position, carry out described inter prediction according to the processing time control information of described inter-frame forecast mode, predicting unit, and described in determining by the processing time control information of described predicting unit, carry out the duration of described inter prediction; Determine the algorithm of the result of more described inter prediction according to described prediction effect comparison algorithm, and according to described prediction effect comparison algorithm, the result of described inter prediction is processed and obtained comparative result; Determine coded system and described image is encoded according to described comparative result.
HEVC encoder is reading from memory inter prediction parameter, can obtain according to the data message in inter prediction parameter the processing sequence of PU, HEVC encoder carries out inter prediction successively according to this order on the image position corresponding with predicting unit, the degree that is HEVC encoder is being read after the data message of PU, example data message as shown in Figure 6, can know the position of current PU according to the information of 13-8 bit and 5-0 bit, CU layer, and the point of the PU pattern adopting at this CU layer and merge processing, can be on image and the inter prediction at this PU opposite position place according to these information HEVC encoder.When after the complete current PU of HEVC coder processes, determine according to the end mark of 25-24 bit whether HEVC coding finishes, if do not finished, HEVC encoder obtains the jump information of next time carrying out inter prediction according to the jump information of predicting of 17-16 bit next time, the CU layer of next time processing, it should be noted that, the sequence of positions of the PU next time processing is fixed, for example four CU32 × 32, in CU32 × 32, the order of layer processing can be the upper left corner so, the upper right corner, the lower left corner, the order in the lower right corner, more special is CU64 × 64, only have one therefore not have processing sequence.HEVC encoder can continue to carry out inter prediction according to the data message of next PU, and the PU order corresponding to CU of every one deck is identical.If 25-24 bit represents to finish coding, HEVC encoder finishes coding, it should be noted that, CU8 × 8 if current, finish that mark needs and the end mark of CU16 × 16, CU32 × 32, CU64 × 64 simultaneously effective, CU16 × 16 if current, finish that mark needs and the end mark of CU32 × 32, CU64 × 64 is simultaneously effective, CU32 × 32 if current, finish that mark needs and the end mark of CU64 × 64 is simultaneously effective, be CU64 × 64 if current, directly finish.HEVC encoder is processed the result of prediction according to prediction effect comparison algorithm in the time that image is carried out to inter prediction, to obtain the coded system of this image optimum, then according to coded system, image is encoded.
Further, before the step 101 of said method embodiment, also comprise: set in advance described inter prediction parameter according to image applications scene or hardware capabilities, and preserve described inter prediction parameter.
Specifically, the hardware capabilities of the coding of video and application scenarios or encoder is closely related, therefore, in the time of default inter prediction encoding parameter, need to consider this two factors.When the application scenarios of video changes, mean variation has all been occurred in the requirement such as definition, continuity of video, now need to adjust the operating process of PU, hardware capabilities changes in addition, represents that the ability of hardware handles data raises or reduces, and no matter is which kind of variation, also need to adjust the operating process of PU, above-mentioned two situations, occur that at least one situation just need to upgrade according to concrete variation the operating process of the PU that carry out inter prediction, and generate new inter prediction parameter.
Fig. 7 is the structural representation of encoder embodiment mono-of the present invention, as shown in Figure 7, the encoder of the present embodiment can comprise: processor 11, memory 12 and addressable controller 13, wherein, memory 12, for store video images and inter prediction parameter, described inter prediction parameter comprise type, the predicting unit of position, the predicting unit of inter-frame forecast mode, predicting unit processing time control information, prediction effect comparison algorithm, predict jump information and finish mark next time; Processor 11, for obtaining a two field picture from described memory, carries out inter prediction according to the described inter prediction parameter setting in advance to described image, and according to the result of described inter prediction, described image is carried out; Addressable controller 13, for carrying out addressing of address at described memory to described inter prediction parameter.
Further, addressable controller 13, specifically for working as the base address of the coding unit layer of pre-treatment, the base address of predicting unit combination according to described inter prediction parameter acquiring; The cumulative quantity of obtaining the predicting unit of processing; The quantity of the base address of described coding unit layer, the base address of predicting unit combination and the predicting unit of described processing is carried out to address and add up, obtain the address of pending described inter prediction parameter in described memory; Processor 11, specifically for according to described pending described inter prediction parameter, the address in described memory obtains described pending inter prediction parameter from described memory, and according to described pending inter prediction parameter, described image is carried out to inter prediction, and according to the result of described inter prediction, described image is encoded.
The device of the present embodiment, can be for the technical scheme of execution graph 1～Fig. 6 either method embodiment, and it realizes principle and technique effect is similar, repeats no more herein.
Fig. 8 is the structural representation of encoder embodiment bis-of the present invention, as shown in Figure 8, the encoder of the present embodiment is on the basis of coder structure shown in Fig. 7, further, can also comprise: trigger 14, cumulative and in described memory addressing for triggering the quantity of described addressable controller.
The device of the present embodiment, can be for the technical scheme of either method embodiment in execution graph 1～Fig. 6, and it realizes principle and technique effect is similar, repeats no more herein.
Further, processor 11, specifically for determining the position of described predicting unit correspondence in described image according to the type of the position of described predicting unit, predicting unit; In described image, on corresponding position, carry out described inter prediction according to the processing time control information of described inter-frame forecast mode, predicting unit, and described in determining by the processing time control information of described predicting unit, carry out the duration of described inter prediction; Determine the algorithm of the result of more described inter prediction according to described prediction effect comparison algorithm, and according to described prediction effect comparison algorithm, the result of described inter prediction is processed and obtained comparative result; Determine coded system and described image is encoded according to described comparative result.
Adopt two specific embodiments below, the technical scheme of Fig. 7 and Fig. 8 shown device embodiment is elaborated.
Fig. 9 is the structural representation of encoder embodiment tri-of the present invention, as shown in Figure 9, the encoder of the present embodiment can comprise: memory module 11, read address control module 12, address state of a control machine module 13, comparison algorithm module 14, bus 15 and read parameter acquisition module 16.Inter prediction parameter writes in memory module 11 by bus 15, reading of address state of a control machine module 13 trigger messages, i.e. triggering is read address control module 12 and in memory module 11, is read inter prediction parameter, reading address control module 12 receives and reads after triggering, the address of reading according to inter prediction parameter acquiring, make the inter prediction parameter of storing in memory module 11 these addresses of output, comprise PU type, PU position, prediction effect comparison algorithm etc., comparison algorithm module 14 is carried out corresponding algorithm according to prediction effect comparison algorithm, and export result of calculation, there is above-mentioned output information, the program of HEVC encoder can complete HEVC coding.
Further, Figure 10 be encoder of the present invention read address control module structural representation, as shown in figure 10, the address control module 12 of reading in Fig. 9 comprises: CU layer selects module 21, PU combination to select module 22, current PU determination module 23 and address accumulator module 24, wherein, CU layer is selected module 21, for the base address when the CU layer of pre-treatment according to inter prediction parameter acquiring; Module 22 is selected in PU combination, for combining corresponding base address according to the PU of the current use of inter prediction parameter acquiring; Current PU determination module 23, for determining the PU flow process address when pre-treatment according to the counting situation of PU flow process; Address accumulator module 24, for the base address of the CU layer when pre-treatment, the PU of current use are combined to corresponding base address, add up when the PU of pre-treatment flow process address, obtains the reading address in memory module.Read address control module above-mentioned three is cumulative, export current reading address to memory module, to realize the read operation of memory module.
Further, Figure 11 is the comparison algorithm modular structure schematic diagram of encoder of the present invention, as shown in figure 11, comparison algorithm module 14 in Fig. 9 comprises: interpolating module 31, the first algoritic module 32, the second algoritic module 33, algorithm module 34 and arithmetic result processing module 35, wherein interpolating module 31, for obtaining the residual values of video; The first algoritic module 32, the second algoritic module 33 and algorithm module 34 are respectively used to realize three kinds of distortion factor optimization algorithms, and these three kinds of algorithms can be for example SAD algorithm, SATD algorithm and SSD algorithm; Arithmetic result processing module 35, for processing the result of calculation of respective algorithms according to the prediction effect comparison algorithm of the data format of current PU execution.
Figure 12 is the flow chart that encoder of the present invention is realized efficient video coding, and as shown in figure 12, the flow process of the present embodiment is applicable to the structure of the embodiment of encoder shown in Fig. 7～Figure 11, and this flow process comprises:
The inter prediction parameter of design is in advance passed through bus write memory by s101, processor;
The inter prediction parameter of s102, processor verification write memory;
S103, processor start to carry out Video coding;
S104, processor read inter prediction parameter from memory according to addressable controller;
S105, processor carry out inter prediction according to inter prediction parameter to image;
In the present embodiment, processor can be divided and process branch according to the combination of PU, for example, PU combination shown in Figure 10 has comprised seven kinds of patterns, each pattern can one of correspondence be processed branch, while prediction between processor conducting frame, need only according to inter prediction parameter acquiring current PU combination, can in corresponding branch, process.
S106, processor complete the inter prediction of the image-region corresponding when the maximum coding unit of pre-treatment;
In the present embodiment, image is divided into multiple regions according to the specification of maximum coding unit, and inter prediction is carried out according to the PU processing sequence in inter prediction parameter in each region, and processor is processed according to default PU order each region respectively.
S107, processor judge whether image to be all disposed, otherwise turn s108, are to turn s109;
In the present embodiment, processor is being handled after the image-region that maximum coding unit is corresponding, first judge whether processes complete two field picture, whether also have the image-region of not processing, if be disposed, processor finishes Video coding, and start for the default inter prediction parameter of new image, encode, if be not also disposed, processor continues to read inter prediction parameter next image-region is carried out to inter prediction again.
S108, processor start image-region corresponding to the maximum coding unit of the next one to carry out inter prediction, turn s104;
S109, processor finish Video coding, turn s101.
One of ordinary skill in the art will appreciate that: all or part of step that realizes above-mentioned each embodiment of the method can complete by the relevant hardware of program command.Aforesaid program can be stored in a computer read/write memory medium.This program, in the time carrying out, is carried out the step that comprises above-mentioned each embodiment of the method; And aforesaid storage medium comprises: various media that can be program code stored such as ROM, RAM, magnetic disc or CDs.
Finally it should be noted that: above each embodiment, only in order to technical scheme of the present invention to be described, is not intended to limit; Although the present invention is had been described in detail with reference to aforementioned each embodiment, those of ordinary skill in the art is to be understood that: its technical scheme that still can record aforementioned each embodiment is modified, or some or all of technical characterictic is wherein equal to replacement; And these amendments or replacement do not make the essence of appropriate technical solution depart from the scope of various embodiments of the present invention technical scheme.
Claims (9)
1. a reusable method for video coding, is characterized in that, comprising:
Obtain a two field picture;
According to the inter prediction parameter acquiring setting in advance, described image is carried out the processing sequence of the predicting unit of inter prediction, described inter prediction parameter comprises inter-frame forecast mode, the position of predicting unit, the type of predicting unit, the processing time control information of predicting unit, prediction effect comparison algorithm, predict jump information next time and finish mark, wherein, described inter-frame forecast mode is used to indicate the reconnaissance mode of carrying out described inter prediction, the position of described predicting unit is used to indicate described predicting unit residing position in coding unit layer, the processing time control information of described predicting unit is used to indicate the duration that carries out inter prediction on the described image position corresponding with described predicting unit, described prediction effect comparison algorithm is used to indicate the algorithm of the result of more described inter prediction, describedly predicts that jump information is used to indicate the described coding unit layer that next time carries out described inter prediction next time,
On the described image position corresponding with described predicting unit, carry out inter prediction successively according to the processing sequence of described predicting unit, and according to the result of described inter prediction, described image is encoded.
2. method according to claim 1, it is characterized in that, describedly on the described image position corresponding with described predicting unit, carry out inter prediction successively according to the processing sequence of described predicting unit, and according to the result of described inter prediction, described image encoded, comprising:
Obtain successively described inter prediction parameter corresponding to pending described predicting unit according to the processing sequence of described predicting unit, on the described image position corresponding with described predicting unit, carry out inter prediction according to described inter prediction parameter;
According to the result of described inter prediction, described image is encoded.
3. method according to claim 2, it is characterized in that, describedly obtain successively described inter prediction parameter corresponding to pending described predicting unit according to the processing sequence of described predicting unit, on the described image position corresponding with described predicting unit, carry out inter prediction according to described inter prediction parameter, comprising:
Obtain successively described inter prediction parameter corresponding to pending described predicting unit according to the processing sequence of described predicting unit, and determine the position of described predicting unit correspondence in described image according to the type of the position of described predicting unit, predicting unit;
In described image, on corresponding position, carry out described inter prediction according to the processing time control information of described inter-frame forecast mode, predicting unit, and described in determining by the processing time control information of described predicting unit, carry out the duration of described inter prediction;
Determine the algorithm of the result of more described inter prediction according to described prediction effect comparison algorithm, and according to described prediction effect comparison algorithm, the result of described inter prediction is processed and obtained comparative result.
4. method according to claim 3, is characterized in that, describedly according to the result of described inter prediction, described image is encoded, and comprising:
Determine coded system and described image is encoded according to described comparative result.
5. according to the method described in any one in claim 1～4, it is characterized in that, described in obtain a two field picture before, also comprise:
Set in advance described inter prediction parameter according to image applications scene or hardware capabilities, and preserve described inter prediction parameter.
6. an encoder, is characterized in that, comprising: processor, memory and addressable controller;
Described memory, for store video images and inter prediction parameter, described inter prediction parameter comprise type, the predicting unit of position, the predicting unit of inter-frame forecast mode, predicting unit processing time control information, prediction effect comparison algorithm, predict jump information and finish mark next time;
Described processor, for obtaining a two field picture from described memory, carries out inter prediction according to the described inter prediction parameter setting in advance to described image, and according to the result of described inter prediction, described image is encoded;
Described addressable controller, for carrying out addressing of address at described memory to described inter prediction parameter.
7. encoder according to claim 6, is characterized in that, described addressing register, specifically for working as the base address of the coding unit layer of pre-treatment, the base address of predicting unit combination according to described inter prediction parameter acquiring; The cumulative quantity of obtaining the predicting unit of processing; The quantity of the base address of described coding unit layer, the base address of predicting unit combination and the predicting unit of described processing is carried out to address and add up, obtain the address of pending described inter prediction parameter in described memory;
Described processor, specifically for according to described pending described inter prediction parameter, the address in described memory obtains described pending inter prediction parameter from described memory, and according to described pending inter prediction parameter, described image is carried out to inter prediction, and according to the result of described inter prediction, described image is encoded.
8. according to the encoder described in claim 6 or 7, it is characterized in that, also comprise:
Trigger, cumulative and in described memory addressing for triggering the quantity of described addressable controller.
9. according to the encoder described in any one in claim 6～8, it is characterized in that, described processor, specifically for determining the position of described predicting unit correspondence in described image according to the type of the position of described predicting unit, predicting unit; In described image, on corresponding position, carry out described inter prediction according to the processing time control information of described inter-frame forecast mode, predicting unit, and described in determining by the processing time control information of described predicting unit, carry out the duration of described inter prediction; Determine the algorithm of the result of more described inter prediction according to described prediction effect comparison algorithm, and according to described prediction effect comparison algorithm, the result of described inter prediction is processed and obtained comparative result; Determine coded system and described image is encoded according to described comparative result.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410219372.3A CN103974069B (en) | 2014-05-22 | 2014-05-22 | Reusable method for video coding and encoder |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410219372.3A CN103974069B (en) | 2014-05-22 | 2014-05-22 | Reusable method for video coding and encoder |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103974069A true CN103974069A (en) | 2014-08-06 |
| CN103974069B CN103974069B (en) | 2017-06-20 |
Family
ID=51243040
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410219372.3A Active CN103974069B (en) | 2014-05-22 | 2014-05-22 | Reusable method for video coding and encoder |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN103974069B (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104363458A (en) * | 2014-10-29 | 2015-02-18 | 复旦大学 | Hardware addressing method for prediction units used for intra-frame prediction in HEVC (high efficiency video coding) standard |
| CN105791866A (en) * | 2014-12-24 | 2016-07-20 | 北京数码视讯科技股份有限公司 | Video coding intermediate data obtaining method, device and system |
| CN107613298A (en) * | 2017-09-27 | 2018-01-19 | 郑州云海信息技术有限公司 | The inter-frame prediction method and system of VP8 videos based on OpenCL |
| CN111757104A (en) * | 2020-06-29 | 2020-10-09 | 北京百度网讯科技有限公司 | Image coding method and device, electronic equipment and storage medium |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101415122A (en) * | 2007-10-15 | 2009-04-22 | 华为技术有限公司 | Forecasting encoding/decoding method and apparatus between frames |
| US20090285285A1 (en) * | 2007-08-21 | 2009-11-19 | Kabushiki Kaisha Toshiba | Information processing apparatus and inter-prediction mode determination method |
| US8379726B2 (en) * | 2007-08-29 | 2013-02-19 | Sony Corporation | Coding apparatus, coding method, decoding apparatus, and decoding method |
| CN103369316A (en) * | 2012-03-29 | 2013-10-23 | 索尼公司 | Image processing apparatus and method |
-
2014
- 2014-05-22 CN CN201410219372.3A patent/CN103974069B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20090285285A1 (en) * | 2007-08-21 | 2009-11-19 | Kabushiki Kaisha Toshiba | Information processing apparatus and inter-prediction mode determination method |
| US8379726B2 (en) * | 2007-08-29 | 2013-02-19 | Sony Corporation | Coding apparatus, coding method, decoding apparatus, and decoding method |
| CN101415122A (en) * | 2007-10-15 | 2009-04-22 | 华为技术有限公司 | Forecasting encoding/decoding method and apparatus between frames |
| CN103369316A (en) * | 2012-03-29 | 2013-10-23 | 索尼公司 | Image processing apparatus and method |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104363458A (en) * | 2014-10-29 | 2015-02-18 | 复旦大学 | Hardware addressing method for prediction units used for intra-frame prediction in HEVC (high efficiency video coding) standard |
| CN104363458B (en) * | 2014-10-29 | 2017-10-10 | 复旦大学 | A kind of hardware addressing addressing method for being used for the predicting unit of infra-frame prediction in HEVC standard |
| CN105791866A (en) * | 2014-12-24 | 2016-07-20 | 北京数码视讯科技股份有限公司 | Video coding intermediate data obtaining method, device and system |
| CN107613298A (en) * | 2017-09-27 | 2018-01-19 | 郑州云海信息技术有限公司 | The inter-frame prediction method and system of VP8 videos based on OpenCL |
| CN111757104A (en) * | 2020-06-29 | 2020-10-09 | 北京百度网讯科技有限公司 | Image coding method and device, electronic equipment and storage medium |
| CN111757104B (en) * | 2020-06-29 | 2022-11-18 | 北京百度网讯科技有限公司 | Image coding method and device, electronic equipment and storage medium |
Also Published As
| Publication number | Publication date |
|---|---|
| CN103974069B (en) | 2017-06-20 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP7237874B2 (en) | Image prediction method and apparatus | |
| RU2699258C2 (en) | Image prediction method and an image prediction device | |
| CN101127902B (en) | Interframe prediction processor with address management mechanism for motion vector storage | |
| CN110024384A (en) | Method and apparatus for the method based on inter-frame forecast mode processing video | |
| CN108781284A (en) | The method and device of coding and decoding video with affine motion compensation | |
| GB2519616A (en) | Method and apparatus for displacement vector component prediction in video coding and decoding | |
| CN105141955A (en) | Apparatus for encoding and decoding image by skip encoding and method for same | |
| CN103430545A (en) | Content adaptive motion compensation filtering for high efficiency video coding | |
| CN103748880A (en) | Method and device for encoding a sequence of images and method and device for decoding a sequence of images | |
| JP2010171729A (en) | Device, method and program for image prediction encoding, device, method and program for image prediction decoding, and encoding/decoding system and method | |
| JP2022515995A (en) | Video processing methods, equipment, non-volatile storage media, computer programs | |
| CN103974069A (en) | Reusable video coding method and encoder | |
| KR20190107944A (en) | Image processing apparatus for performing filtering on restored images and filtering method thereof | |
| US20180199058A1 (en) | Video encoding and decoding method and device | |
| JP2007189276A (en) | Image compression apparatus and image compression program | |
| KR20220003020A (en) | Encoding and decoding methods, apparatus, and apparatus | |
| JP4888919B2 (en) | Moving picture encoding apparatus and moving picture decoding apparatus | |
| CN102685506B (en) | Intra-frame predication method and predication device | |
| CN101005627A (en) | Image decoding method, image decoding apparatus, and data storage medium | |
| CN110166770B (en) | Video encoding method, video encoding device, computer equipment and storage medium | |
| CN104104947B (en) | A kind of method for video coding and device | |
| CN103828366A (en) | Adaptive filtering based on pattern information | |
| CN102801980A (en) | Scalable video coding decoding device and method | |
| CN112422971B (en) | Encoding and decoding method, device and equipment | |
| CN103327340A (en) | Method and device for searching integer |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| TR01 | Transfer of patent right | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20220211 Address after: 550025 Huawei cloud data center, jiaoxinggong Road, Qianzhong Avenue, Gui'an New District, Guiyang City, Guizhou Province Patentee after: Huawei Cloud Computing Technologies Co.,Ltd. Address before: 518129 Bantian HUAWEI headquarters office building, Longgang District, Guangdong, Shenzhen Patentee before: HUAWEI TECHNOLOGIES Co.,Ltd. |