CN103973623B - Multi-system phase shift keying signal detection system - Google Patents
Multi-system phase shift keying signal detection system Download PDFInfo
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- CN103973623B CN103973623B CN201410241147.XA CN201410241147A CN103973623B CN 103973623 B CN103973623 B CN 103973623B CN 201410241147 A CN201410241147 A CN 201410241147A CN 103973623 B CN103973623 B CN 103973623B
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Abstract
The invention provides a multi-system phase shift keying signal detection system based on a field programmable gate array. The multi-system phase shift keying signal detection system comprises Q multi-system phase shift keying signal detection subsystems and a determiner, wherein the determiner is used for determining that a transmitting data signal which corresponds to the minimal cost function value of Q cost function values is a multi-system phase shift keying signal detection result; any one multi-system phase shift keying signal detection subsystem comprises r updaters, a comparer and a phase updater, an error counter, a controller and a random storage, so that the realization is easy, and the complexity of the hardware design of the multi-system phase shift keying signal detection system is lowered, and the detection system can be suitable for a large-scale multi-user/multi-antenna system.
Description
Technical field
The application is related to signal processing technology field, particularly to a kind of multiple phase-shift keying signal detecting system.
Background technology
All the time, multi-user in CDMA (Code Division Multiple Access, CDMA) system
The computational complexity that (Multi-user, MU) detection method acquisition optimal performance is paid is an important problem.For little
Scale MU system, ball-type detection method can obtain close to optimal performance, but when MU system scale becomes big, its operand also becomes
Obtain extremely complex.Positive semidefinite relaxation method detects M system phase shift keying (M-ary phase shift keying, MPSK) signal
Computer Simulation multi-user environment is done well, but practical application or very complicated.Some researchers considered in recent years
Using aerial array, it is referred to as multiple antennas (MIMO, Multiple-Input Multiple-Output) technology, to obtain wireless
The spectrum efficiency that communication system is likely to be breached.Although said method can provide preferably detection performance, for extensive
Mimo system computing is unduly complex.
With updating for extensive mimo system RF/ antenna/e measurement technology, how to design a kind of actually active
Method, in extensive mimo system, with lower complexity, significantly more efficient raising systematic function, become the weight of research
Point.Extensively used based on the detection method of field programmable gate array (Field-programmable gate-array, FPGA)
In MU and mimo system.But, the detecting system based on FPGA relative with the detection method based on FPGA, it is applied to little rule more
Mould MU/MIMO system, for large-scale and multiple users/multiaerial system, the complexity of hardware design is very high.
Content of the invention
For solving above-mentioned technical problem, the embodiment of the present application provides a kind of multiple phase-shift keying signal detecting system, with
Reduce the purpose of hardware design complexity, technical scheme is as follows：
A kind of multiple phase-shift keying signal detecting system, based on field programmable gate array, including：Q multi-system phase
Shift keyed signals detect subsystem, and described Q multiple phase-shift keying signal detects the same user's of subsystem parallel computation
Cost function value, and each multiple phase-shift keying signal detects that the initial value of subsystem is different, described Q is more than or equal to 1
Integer；
Determiner, for determining that minimum cost function value corresponding transmission data signal in Q cost function value is many
System phase shift keying signal detecting result；
Wherein, any one multiple phase-shift keying signal detection subsystem includes：R renovator, comparator ＆ phase place update
Device, error calculator, controller and random access memory；
Described r renovator, for calculating vectorial r, described y=H according to formula r=y-R × expROM (Φ)hZ, described Φ
For angle index vector, described expROM (Φ) is the exponential quantity of described Φ, described R=HhH, described h are conjugate transposition, described H
For channel matrix vector or Spread Spectrum Matrix vector, described z is received signal vector, and the initial value of described Φ is Φq, described ΦqIt is
During q-th leggy down and out options, bk, the initial angle set of k=1,2 ... K, described K represents K user, described bkFor kth
The transmission data signal of individual user, described q=1 ... Q；
Described comparator ＆ phase place renovator, for updating described Φ；
Described error calculator, for according to formulaCalculate described J (b),
Described J (b) is cost function value, describedIt is the mathematic sign taking real part, described b is that the respective transmission data of k user is believed
Number composition transmission data signal vector；
Described controller, for controlling the behaviour between described r renovator, comparator ＆ phase place renovator and error calculator
Make；
Described random access memory, for storing described R, described y, described Φ and described r.
Preferably, described random access memory includes：
R random access memory, for storing described R；
Y random access memory, for storing described y；
Φ random access memory, for storing described Φ；
R random access memory, for storing described r.
Preferably, described r renovator includes：
First dual-ported memory, for exportingWithDescribedDefeated for the A of described first dual-ported memory
The exponential quantity of exit port output, describedExponential quantity for the B output port output of described first dual-ported memory；
6 DSP, the respectively the first DSP, the 2nd DSP, the 3rd DSP, the 4th DSP, the 5th DSP and the 6th DSP, described
One DSP, described 2nd DSP and described 3rd DSP are a DSP group, and described 4th DSP, the 5th DSP and the 6th DSP are second
DSP group, a described DSP group and described 2nd DSP group parallel running, a described DSP group for calculating the real part of described r,
Described 2nd DSP group is for calculating the imaginary part of described r；
Described 3rd DSP, for exporting the real part of described r, the real part of described r is
rkIt is k-th value of vectorial r, ΦnIt is n-th angle, n=0,1 ... K-1, Rk,nIt is the n-th train value of the row k of matrix R,It is
Take the mathematic sign of imaginary part；
Described 6th DSP, for exporting the imaginary part of described r, the imaginary part of described r is
A described DSP, described 2nd DSP, described 4th DSP and described 5th DSP are all deposited with described first dual-port
The output port of reservoir is connected；
Each DSP in a described DSP group each B end with the B port of R random access memory, y random access memory respectively
Mouthful it is connected with the B port of r random access memory, each B end with R random access memory respectively of each DSP in described 2nd DSP group
Mouth, the B port of y random access memory are connected with the B port of r random access memory；
5 logic multiplexers MUX, the respectively the first MUX, the 2nd MUX, the 3rd MUX, the 4th MUX and the 5th MUX；
A described MUX is used for selecting Φ random access memory port, and described 2nd MUX and described 3rd MUX are used for selecting y
Random access memory port, described 4th MUX is used for exporting the real part of described r, and described 5th MUX is used for exporting the imaginary part of described r；
Multiple first registers, described first register and the DSP in a described DSP group and corresponding random access memory
It is connected；
Multiple second registers, described second register and the DSP in described 2nd DSP group and corresponding random access memory
It is connected.
Preferably, a described DSP includes the 6th MUX, and described 2nd DSP includes the 7th MUX and the 8th MUX, and described
Three DSP include the 9th MUX, and described 4th DSP includes the tenth MUX, and described 5th DSP includes the 11st MUX and the 12nd MUX,
Described 6th DSP includes the 13rd MUX；
Described 6th MUX, the 7th MUX, the tenth MUX and the 11st MUX, are respectively used to set the pre- adder of bypass；
Described 8th MUX and described 12nd MUX, is respectively used to first clock cycle choosing in every K clock cycle
Select the 2nd MUX and the 3rd MUX output and in remaining K-1 clock period selection 0；
Described 9th MUX and described 13rd MUX, is respectively used to first clock cycle choosing in every K clock cycle
Select 0, feed back in K-1 clock period selection.
Preferably, described comparator ＆ phase place renovator includes：
Second dual-ported memory, for exportingWithDescribed ΦkAngle for k-th user's transmission information
Degree, described d is the step-length of travel(l)ing phase, and described j is imaginary unit, the Φ of described second dual-ported memorykInput port with
The A port of described Φ random access memory is connected, and described d is input to the d port of described second dual-ported memory；
3rd dual-ported memory, for exportingAnd ejd, the Φ of described 3rd dual-ported memorykInput port
It is connected with the A port of described Φ random access memory, described d is input to the d port of described 3rd dual-ported memory；
4 DSP, the respectively the 7th DSP, the 8th DSP, the 9th DSP and the tenth DSP, wherein said 7th DSP and the 8th
DSP forms the 3rd DSP group, and described 9th DSP and the tenth DSP forms the 4th DSP group, and described 3rd DSP group and the 4th DSP group are simultaneously
Row runs, and described 3rd DSP group is for calculating cp, described cpFor positive rotation, described 4th DSP group is for calculating cn, described cnFor
Negative rotation turns；
The A port of r random access memory is connected with the r port of described 7th DSP, the 8th DSP, the 9th DSP and the tenth DSP respectively
Connect；
Described 7th DSP, for exporting described cp；
Described 9th DSP, for exporting described cn；
Determining device, is connected with described 7th DSP and described 9th DSP, for judging c respectivelypAnd cnSign bit, in institute
State cpSign bit be 1 when, triggering the 14th MUX outputIn described cnSign bit when being 1, triggering is described
14th MUX output
Described 14th MUX is connected with described r renovator, will be described：WithIt is respectively written into described r renovatorPort andPort；
Multiple 3rd registers, described 3rd register and the DSP in described 3rd DSP group and corresponding random access memory
It is connected；
Multiple 4th registers, described 4th register and the DSP in described 4th DSP group and corresponding random access memory
It is connected.
Preferably, described error calculator includes：
4th dual-ported memory, for exporting ejΦ；
3 DSP, the respectively the 11st DSP, the 12nd DSP and the 13rd DSP；
15th MUX；
Wherein, Φ random access memory B port is connected with the A address port of the 4th dual-ported memory, described 4th both-end
The A data-out port of mouth memory is connected with the 11st DSP and the 12nd DSP respectively, and the B port of r random access memory is respectively
It is connected with the 11st DSP and the 12nd DSP, the B port of y random access memory is connected with the 11st DSP and the 12nd DSP respectively；
Described 13rd DSP, for exporting
Preferably, described 11st DSP, the connected mode of described 12nd DSP and described 13rd DSP are cascade.
Preferably, the type of described DSP is specially DSP48E1.
Compared with prior art, the having the beneficial effect that of the application：
In this application, Q is included based on the multiple phase-shift keying signal detecting system of field programmable gate array individual many
System phase shift keying signal detection subsystem.
Multiple phase-shift keying signal detection subsystem is by r renovator, comparator ＆ phase place renovator, error calculator, control
Device processed and random access memory composition, realize simple, reduce the complexity of multiple phase-shift keying signal detecting system hardware design
Degree, can be applied to large-scale and multiple users/multiaerial system.
Brief description
For the technical scheme being illustrated more clearly that in the embodiment of the present application, will make to required in embodiment description below
Accompanying drawing be briefly described it should be apparent that, drawings in the following description are only some embodiments of the present application, for
For those of ordinary skill in the art, without having to pay creative labor, it can also be obtained according to these accompanying drawings
His accompanying drawing.
Fig. 1 is a kind of structural representation that the multiple phase-shift keying signal that the application provides detects subsystem；
Fig. 2 is a kind of structural representation of the random access memory that the application provides；
Fig. 3 is a kind of hardware structure schematic diagram that the multiple phase-shift keying signal that the application provides detects subsystem；
Fig. 4 is a kind of configuration diagram of the r renovator that the application provides；
Fig. 5 is a kind of configuration diagram of the comparator ＆ phase place renovator that the application provides；
Fig. 6 is a kind of configuration diagram of the error calculator that the application provides；
Fig. 7 is the multiple phase-shift keying signal detecting system under awgn channel of the application offer in big numerical value of N and K (N
=K) and Q=8, MbPerformance comparision figure with single antenna input and output in the case of=6.
Specific embodiment
Below in conjunction with the accompanying drawing in the embodiment of the present application, the technical scheme in the embodiment of the present application is carried out clear, complete
Site preparation describes it is clear that described embodiment is only some embodiments of the present application, rather than whole embodiments.It is based on
Embodiment in the application, it is every other that those of ordinary skill in the art are obtained under the premise of not making creative work
Embodiment, broadly falls into the scope of the application protection.
Before the multiple phase-shift keying signal detecting system that the application is provided is described, first to prior art
The detection process of middle MU and mimo system is simply introduced, as follows：
In MU and mimo system, received N × 1 signal vector z can be expressed as：
Z=Hb+n (1)
Wherein b is in multi-level modulation AkIn obtain K × 1 transmission data signal vector.This group transmission data signal to
Measurer has M phase angle and can be expressed asH is a N × K matrix.In MU detecting system, N is spread spectrum
The factor, H is Spread Spectrum Matrix.In mimo system, H is channel matrix, and N is reception antenna number, and K represents K user.N is variance
For σ2, average be 0 N × 1 Gauss arbitrarily vectorial.B can be obtained and be expressed as follows by maximal possibility estimation detector：
It is the estimate of b.
Wherein
And R=HhH, y=HhZ, can be obtained by loosening (2) inner constraint:
Unknown symbols phasekMeet | bk|=1, its result can be expressed as：
Embodiment one
In the present embodiment, the multiple phase-shift keying signal detecting system that the application provides, wherein, multi-system are shown
Phase shift keyed signal detecting system is based on field programmable gate array, and multiple phase-shift keying signal detecting system includes：Q many
System phase shift keying signal detection subsystem and determiner.
In the present embodiment, described Q multiple phase-shift keying signal detection subsystem is used for the same use of parallel computation
The cost function value at family, and each multiple phase-shift keying signal detects that the initial value of subsystem is different, described Q be more than or equal to
1 integer.
In the present embodiment, the numerical value of Q is specifically determined by current detection mission requirements.
Determiner, for determining that minimum cost function value corresponding transmission data signal in Q cost function value is many
System phase shift keying signal detecting result.
In the present embodiment, each multiple phase-shift keying signal detection subsystem all can adopt pipeline system, point
Do not calculate the respective cost function value of multiple users.
Because each multiple phase-shift keying signal detects that the structure of subsystem is identical, therefore only to any in the present embodiment
One multiple phase-shift keying signal detects that the structure of subsystem is described.
Refer to Fig. 1, Fig. 1 shows that the multiple phase-shift keying signal that the application provides detects a kind of structure of subsystem
Schematic diagram, multiple phase-shift keying signal detection subsystem includes：R renovator 11, comparator ＆ phase place renovator 12, mistake meter
Calculate device 13, controller 14 and random access memory 15.
R renovator 11, for calculating vectorial r, described y=H according to formula r=y-R × expROM (Φ)hZ, described Φ are
Angle index vector, described expROM (Φ) is the exponential quantity of described Φ, described R=HhH, described h are conjugate transposition, and described H is
Channel matrix vector or Spread Spectrum Matrix vector, described z is received signal vector, and the initial value of described Φ is Φq, described ΦqIt is
During q leggy down and out options, bk, the initial angle set of k=1,2 ... K, described K represents K user, described bkFor k-th
The transmission data signal of user, described q=1 ... Q.
In the present embodiment, hardware design 2 π constellation clusters circle be divided into equirotalEqual portions are simultaneously often a
Angle is respectively labeled as 0 and arrivesThisThe exponential quantity of part angle is precalculated, is then saved in dual-ported memory
In.Therefore gauge index function can be obtained by reading the value in dual-ported memory, and the address of its dual-ported memory is exactly
Angle index value, angle index vector Φ substitutes vectorial b.Can significantly improve by using Q different initial value combining local searchings
Detection performance.Wherein,In part angle, the exponential quantity of arbitrarily a angle can be expressed as：B=exp (j Φ).
When using leggy down and out options q-th, the index value set of each self-corresponding angle of K user is：
bq=exp (j Φq), (6)
ΦqWhen being to use leggy down and out options q-th, bk, the initial angle set of k=1,2 ... K.bqIt is exactly q-th
During leggy down and out options, bk, k=1,2 ... K correspondence ΦqThe exponential function value of angle, is also initial value.
Wherein Φq, q=1 ... Q, is Q independent satisfaction equally distributed Any Digit in [0,2 π].There is identical square
The Q phase place down and out options of battle array R and vectorial y are using different initial results vector bq(its corresponding vector Φq) parallel computation, simultaneously
Generate Q result.
Comparator ＆ phase place renovator 12, for updating described Φ.
Error calculator 13, for according to formulaCalculate described J (b), described
J (b) is cost function value, describedIt is the mathematic sign taking real part, described b is the respective transmission data signal group of k user
The transmission data signal vector becoming.
In the present embodiment, cost function J (b) of formula (3) is simplified to：
After cost function J (b) to formula (3) carries out simplifying operation, can be the complexity of hardware design from O (K2)
It is reduced to the individual arithmetical operation of O (K).
Wherein, map operation can only use add operation in hardware, and its scope meets：
Element ΦkFor ΦqIn element, ΦkIt is mapped to v-th phase place, v=0,1 ... M-1.By plus side-play amountTo Φk, v-th phase range becomeTherefore quantity v is equal toTwo
The most important log of system representation2M position.Low Mb-log2M position is cleared.Wherein, M represents the corresponding system of signal modulation mode
Number.
Controller 14, for controlling the operation between described r renovator, comparator ＆ phase place renovator and error calculator.
Random access memory 15, for storing described R, described y, described Φ and described r.
In the present embodiment, the concrete structure of random access memory 15 refers to Fig. 2, Fig. 2 show the application provide with
A kind of structural representation of machine memory, random access memory 15 includes：R random access memory 21, y random access memory 22, Φ are random
Memory 23 and r random access memory 24.
R random access memory 21, for storing described R.
Y random access memory 22, for storing described y.
Φ random access memory 23, for storing described Φ.
R random access memory 24, for storing described r.
In the present embodiment, refer to Fig. 3, Fig. 3 shows multiple phase-shift keying signal detection that the application provides
A kind of hardware structure schematic diagram of system.Wherein, in Fig. 3, R random access memory 21 is shown by R ram table, and y random access memory 22 is by y
Ram table shows, Φ random access memory 23 is shown by Φ ram table, and r random access memory 24 is shown by r ram table.
The multiple phase-shift keying signal detecting system that the application provides specifically can be realized with fpga chip.
In this application, Q is included based on the multiple phase-shift keying signal detecting system of field programmable gate array individual many
System phase shift keying signal detection subsystem.
Multiple phase-shift keying signal detection subsystem is by r renovator, comparator ＆ phase place renovator, error calculator, control
Device processed and random access memory composition, realize simple, reduce the complexity of multiple phase-shift keying signal detecting system hardware design
Degree, can be applied to large-scale and multiple users/multiaerial system.
Further, because Q multiple phase-shift keying signal detects that subsystem is capable of the same user's of parallel computation
Cost function value, therefore improves Detection accuracy.
It should be noted that the value of Q is bigger, the accuracy rate of detection is higher.
Embodiment two
In the present embodiment thus it is shown that the concrete framework of r renovator, r renovator includes：First dual-ported memory, 6
Individual DSP, 5 logic multiplexers MUX, multiple first register and multiple second register.Wherein：
First dual-ported memory, for exportingWithDescribedDefeated for the A of described first dual-ported memory
The exponential quantity of exit port output, describedExponential quantity for the B output port output of described first dual-ported memory.
6 DSP, the respectively the first DSP, the 2nd DSP, the 3rd DSP, the 4th DSP, the 5th DSP and the 6th DSP, described
One DSP, described 2nd DSP and described 3rd DSP are a DSP group, and described 4th DSP, the 5th DSP and the 6th DSP are second
DSP group, a described DSP group and described 2nd DSP group parallel running, a described DSP group for calculating the real part of described r,
Described 2nd DSP group is for calculating the imaginary part of described r.
Described 3rd DSP, for exporting the real part of described r, the real part of described r is
rkIt is k-th value of vectorial r, ΦnIt is n-th angle, n=0,1 ... K-1, Rk,nIt is the n-th train value of the row k of matrix R,It is the mathematic sign taking imaginary part；
Described 6th DSP, for exporting the imaginary part of described r, the imaginary part of described r is
A described DSP, described 2nd DSP, described 4th DSP and described 5th DSP are all deposited with described first dual-port
The output port of reservoir is connected.
Each DSP in a described DSP group each B end with the B port of R random access memory, y random access memory respectively
Mouthful it is connected with the B port of r random access memory, each B end with R random access memory respectively of each DSP in described 2nd DSP group
Mouth, the B port of y random access memory are connected with the B port of r random access memory.
5 logic multiplexers MUX, the respectively the first MUX, the 2nd MUX, the 3rd MUX, the 4th MUX and the 5th MUX.
A described MUX is used for selecting Φ random access memory port, and described 2nd MUX and described 3rd MUX are used for selecting y
Random access memory port, described 4th MUX is used for exporting the real part of described r, and described 5th MUX is used for exporting the imaginary part of described r.
First DSP, the connected mode of the 2nd DSP and the 3rd DSP are cascade, postpone for obtaining minimal path.4th
DSP, the connected mode of the 5th DSP and the 6th DSP are cascade, postpone for obtaining minimal path.
In the present embodiment, described first register and the DSP in a described DSP group and corresponding random access memory phase
Even.
Described second register is connected with the DSP in described 2nd DSP group and corresponding random access memory.
First register and the second register are used for equilibrium criterion Path Latency and minimize path delay time.
In the present embodiment, a described DSP includes the 6th MUX, and described 2nd DSP includes the 7th MUX and the 8th MUX,
Described 3rd DSP includes the 9th MUX, and described 4th DSP includes the tenth MUX, and described 5th DSP includes the 11st MUX and the tenth
Two MUX, described 6th DSP includes the 13rd MUX.
Described 6th MUX, the 7th MUX, the tenth MUX and the 11st MUX, are respectively used to set the pre- adder of bypass.
Described 8th MUX and described 12nd MUX, is respectively used to first clock cycle choosing in every K clock cycle
Select the 2nd MUX and the 3rd MUX output and in remaining K-1 clock period selection 0.
Described 9th MUX and described 13rd MUX, is respectively used to first clock cycle choosing in every K clock cycle
Select 0, feed back in K-1 clock period selection.
Refer to Fig. 4, Fig. 4 shows a kind of configuration diagram of the r renovator that the application provides.Wherein, in Fig. 4,
ExpROM1 represents the first dual-ported memory, and DSP1 represents that a DSP, DSP2 represent that the 2nd DSP, DSP3 represent the 3rd DSP,
DSP4 represents that the 4th DSP, DSP5 represent that the 5th DSP, DSP6 represent that the 6th DSP, MUX1 represent that a MUX, MUX2 represent second
MUX, MUX3 represent that the 3rd MUX, MUX4 represent that the 4th MUX, MUX5 represent that the 5th MUX, MUX6 represent that the 6th MUX, MUX7 represent
7th MUX, MUX8 represent that the 8th MUX, MUX9 represent that the 9th MUX, MUX10 represent that the tenth MUX, MUX11 represent the 11st MUX,
MUX12 represents that the 12nd MUX, MUX13 represent the 13rd MUX.
In the present embodiment, all arithmetical operations all complete inside DSP.Because all arithmetical operations are all inside DSP
Complete, therefore the resource of r renovator can effectively be utilized.
Embodiment three
In the present embodiment thus it is shown that the concrete framework of comparator ＆ phase place renovator, comparator ＆ phase place renovator bag
Include：Second dual-ported memory, the 3rd dual-ported memory, 4 DSP, determining device, the 14th MUX, multiple 3rd register and
Multiple 4th registers.Wherein：
Second dual-ported memory, for exportingWithDescribed ΦkSend the angle of information for k-th user,
Described d is the step-length of travel(l)ing phase, and described j is imaginary unit, the Φ of described second dual-ported memorykInput port with described
The A port of Φ random access memory is connected, and described d is input to the d port of described second dual-ported memory.
3rd dual-ported memory, for exportingAnd ejd, the Φ of described 3rd dual-ported memorykInput port
It is connected with the A port of described Φ random access memory, described d is input to the d port of described 3rd dual-ported memory.
4 DSP, the respectively the 7th DSP, the 8th DSP, the 9th DSP and the tenth DSP, wherein said 7th DSP and the 8th
DSP forms the 3rd DSP group, and described 9th DSP and the tenth DSP forms the 4th DSP group, and described 3rd DSP group and the 4th DSP group are simultaneously
Row runs, and described 3rd DSP group is for calculating cp, described cpFor positive rotation, described 4th DSP group is for calculating cn, described cnFor
Negative rotation turns.
The A port of r random access memory is connected with the r port of described 7th DSP, the 8th DSP, the 9th DSP and the tenth DSP respectively
Connect.
Described 7th DSP, for exporting described cp.
Described 9th DSP, for exporting described cn.
Determining device, is connected with described 7th DSP and described 9th DSP, for judging c respectivelypAnd cnSign bit, in institute
State cpSign bit be 1 when, triggering the 14th MUX outputIn described cnSign bit when being 1, triggering is described
14th MUX output
Described 14th MUX is connected with described r renovator, will be described：WithIt is respectively written into described r renovatorPort andPort.
In the present embodiment, described 3rd register and the DSP in described 3rd DSP group and corresponding random access memory phase
Even.
Described 4th register is connected with the DSP in described 4th DSP group and corresponding random access memory.
Refer to Fig. 5, Fig. 5 shows a kind of configuration diagram of the comparator ＆ phase place renovator that the application provides.Its
In, in Fig. 5, expROM2 represents the second dual-ported memory, and expROM3 represents the 3rd dual-ported memory, and DSP7 represents the 7th
DSP, DSP8 represent that the 8th DSP, DSP9 represent that the 9th DSP, DSP10 represent that the tenth DSP, Checker represent determining device, MUX14
Represent the 14th MUX.
Example IV
In the present embodiment, show the concrete framework of the error calculator that the application provides, error calculator includes：The
Four dual-ported memories, 3 DSP and the 15th MUX.Wherein：
4th dual-ported memory, for exporting ejΦ.
3 DSP, the respectively the 11st DSP, the 12nd DSP and the 13rd DSP.
15th MUX.
Φ random access memory B port is connected with the A address port of the 4th dual-ported memory, described 4th dual-port storage
The A data-out port of device is connected with the 11st DSP and the 12nd DSP respectively, and the B port of r random access memory is respectively with the tenth
One DSP and the 12nd DSP is connected, and the B port of y random access memory is connected with the 11st DSP and the 12nd DSP respectively.
Described 13rd DSP, for exporting
In the present embodiment, described 11st DSP, the connected mode of described 12nd DSP and described 13rd DSP are level
Connection.
Refer to Fig. 6, Fig. 6 shows a kind of configuration diagram of the error calculator that the application provides.Wherein, in Fig. 6,
ExpROM4 represents the 4th dual-ported memory, and DSP11 represents that the 11st DSP, DSP12 represent that the 12nd DSP, DSP13 represent
13 DSP, MUX15 represent the 15th MUX.
In the above-described embodiments, the type of described DSP is specially DSP48E1.
Based on above-described embodiment and Fig. 1 to Fig. 6, because each multiple phase-shift keying signal detection subsystem is detected
Method identical, therefore to any one multiple phase-shift keying signal, the application only detects that the process that detected of subsystem is entered
Row explanation, specifically refers to table one：
Table one
Wherein, the state 1 in table one：Step-length indexes m, element index k, more new variables Flag, refresh counter it and rank
Segment counter stage is initialized M by controller respectivelyb, 1,0,0 and 1.
State 2 in table one：R renovator initializes residual vector r.By setting all 13 MUXs, r renovator works
In one of two patterns：Initialization vector r (state 2) or renewal vector r (state 5).In order to initialize r, Φ RAM is from B port
This operation execution that order is read K time.R RAM and y RAM is read by B port simultaneously.Every K time cycle reads
R RAM mono- column element, reads mono- element of yRAM.MUX1 is used for selecting Φ ram port.MUX2 and MUX3 is used for selecting y RAM
Port.MUX6, MUX7, MUX10 and MUX11 are used for setting the pre- adder of bypass.MUX8 and MUX12 is only in every K clock cycle
First clock period selection MUX2 and MUX3 output and in remaining K-1 clock period selection 0.MUX9 and MUX13 is
One clock period selection 0, feeds back in K-1 clock period selection.All these operations are all dirty in the management of controller
Waterline is carried out.DSP3 exports：
With DSP6 output
Wherein k=0,1 ... K-1.
First element of r can be obtained and r RAM is write into by A port after all K that add up.This process will weigh
Multiple K time in residual vector r all K elements calculated one time.The total waiting time of whole process is K2+ 8 cycles, including
RAM reads stand-by period, DSP stand-by period and controller stand-by period.But controller is assigned to phase in all reading addresses
Next state is gone to, r renovator is automatically performed initial work during the RAM answering.Step 2 needs K altogether2+ 4 clock cycle.
State 3 in table one：According to the numerical value of stage variable stage, controller updates digit counter m and step-length d.This
Step only needs 1 clock cycle.New step-length d writes into the d port of comparator ＆ phase place renovator.
State 4 in table one：Judge whether iterative operation is successful (it_succ=1).If iteration is successful,
State 5 updates result Φ.Comparator ＆ phase place renovator controls execution to compare the operation updating with result Φ.In conjunction with Fig. 5, in shape
State 4, DSP7 and DSP9 exports c respectivelypAnd cn.Final judgement part (i.e. determining device) judges cpAnd cnSign bit.When it detects
Go out positive it is meant that being successful iterative operation, judgement part is put 1 it_succ and exportedWith
The first time of new step-length d compares, and the value of Φ RAM reads from B port, and the value of r RAM reads from A port.Comparing
After device process etc. is to be delayed, controller phase place renovator starts to judge it_succ signal.Once first it_succ signal quilt
Detect, controller stops relatively and writesTo Φ RAMA port.Then start renewal process.First time ratio with new step-length
Relatively need 19 clock cycle.
State 5 in table one：WithNumerical value be respectively written into r renovatorWithPort simultaneously keeps, directly
Start to renewal process.R(k)With r from the B port parallel read-out of the B port of RRAM and r RAM.MUX1 is used for selectingDefeated
Enter.MUX2 and MUX3 come to select r input.MUX6, MUX7, MUX10 and MUX11 are used for selecting the output of pre- adder.MUX8 and
MUX12 selects MUX2 and MUX3.MUX4 and MUX5 selects DSP1 and DSP4 output；DSP3 and DSP6 is bypassed.
Therefore, DSP1 output
With DSP4 output
Wherein n=0,1 ... K-1.
Updated r element writes into r RAM by A port.The A port of r RAM be set to write preferential that is to say, that
The data being written into after two RAM delay periods will display.Numerical value in Φ RAM is synchronously read into r RAM simultaneously
A port.Therefore comparator is with updated residual vector r process.
If it find that next successfully detect in current renewal process, controller is after current renewal r and Φ terminates
Immediately begin to new renewal process.This renewal process is that iterative operation that continuously perform and each only needs K clock cycle.
Because comparator ＆ phase place renovator at most needs 18 cycle delays, the therefore next one successfully detects and can occur currently more
After new process.Such situation, has the difference of 1～18 clock cycle in two renewal processes.Without successfully changing
In generation, controller shifts to state 3.
State 6：Vectorial Φ is demodulated to be made and modulates.In a pipeline fashion, each element value in Φ passes through the B of Φ RAM
Port is read, and adds the side-play amount of a fixationBy low Mb-log2M position is zero, then passes through the A of Φ RAM
Port is written back into Φ RAM.This state only needs K clock cycle and time delay and other operating times overlap.If
At first stage (stage=1), controller updates Stage Counting device, and it goes to state 2；Otherwise it goes to state 7.
State 7 in table one：The mistake of cost function J (b) is calculated with special error calculator.DSP13 exports
It is equal to
Wherein k=0,1 ... K-1.So that DSP13 adds up, all of K value carrys out mistake in computation for the selection of controller control MUX15.This
Individual state and state 6 parallel running；The clock cycle of therefore this state can be disregarded.
Table one lists the clock periodicity required for each state.Required total clock depends primarily on successful iteration
Number and MbNumerical value.In first stage, it is contemplated that worst situation is to have N in only last positionuIndividual successfully change
Generation.This means to start (M mostb- 1) position does not comprise any successful iteration it is therefore desirable to (Mb- 1) (20+K) the individual clock cycle.Separately
A kind of outer worst condition can occur i.e. when calculating last position (m=1), if only having a successful iteration in K iteration.This
Sample needs (K+18) cycle make comparisons, update residual vector r and phase place Φk.Therefore, NuIndividual successful path needs Nu(K+18) individual
Clock cycle.In addition, state 1,2 and 6 needs K altogether2+ K+5 clock cycle.Therefore in worst condition, the stage 1 needs
(Mb-1)(K+20)+Nu(K+18)+K2+ K+5 cycle.In the stage 2, the iteration of at most needs Nu(K+18) individual clock week
Phase, the K separately plus required for state 2 and 62+ 4+K clock cycle.In a word, in worst case, multiple phase-shift keying signal
The most number of clock cycles required for process that detection subsystem is detected are (Mb-1)(K+20)+2Nu(K+18)+2K2+
2K+10.
In order to the hardware design of the detection process shown in table one and the application is described, carried out with Computerized Numerical Simulation experiment
Illustrate, such as Fig. 7 and Biao bis-, Fig. 7 show that the application provides AWGN (Additive White Gaussian Noise, plus
Property white Gaussian noise) under channel multiple phase-shift keying signal detecting system in N (N is spreading factor or reception antenna number) and
K (N=K) and Q=8, MbPerformance comparision figure with single antenna input and output in the case of=6.
As shown in fig. 7, with the increase of mimo system scale, substantially being changed using multiple phase-shift keying signal detecting system
It has been apt to detection performance.Work as N=K=50, using multiple phase-shift keying signal detecting system BER (bit error rate, than
Bit error) it is equal to 10-4When only with SISO (single input single output, single-input single-output system) performance bound
Limit difference 1dB.Work as N=K=100, using multiple phase-shift keying signal detecting system detection performance lines further to
SISO boundary (within 0.5dB).These results show for large-scale multi-antenna system, using the inspection of multiple phase-shift keying signal
Examining system can reach the ability close to SISO performance limit with less initial value quantity Q (Q=8).
Table two
Wherein, FF17591Bag, speed class 2.Have most RAM and DSP, but be not the fastest.RAM peak frequency
475MHz(2.105ns).DSP peak frequency 540MHz.
FF11562Bag, speed class 3.There is less RAM, DSP and Slice, but the fastest.RAM peak frequency 525MHz
(1.905ns).DSP peak frequency 600MHz.
Table two compares single phase place down and out options core and realizes in the hardware of different fpga chips.Data Representation area makes
With and system clock frequency.Implementation method used be based on the application provide multiple phase-shift keying signal detecting system simultaneously
Using QPSK modulation.
Each FPGA is realized, we have studied the hardware occupancy in the case of K=32 and K=64 and the amount of telling.Table two
Resources of chip required for display K=64 and K=32 is essentially the same, but K=64 needs more RAM.This is because it is all
Matrix and vector be stored in block RAM, with K increase matrix and the scale of vector also can increase it is therefore desirable to more
RAM.
Because single phase place down and out options core only takes up little fpga chip resource, declined by Q parallel phase place
The multi-phase detecting method core now with Q branch is examined in search.The result of phase place down and out options is by minimum erroneous values
Come to determine.In this design, such as K=64, using xc6vsx475t-2ff17591Chip, the occupancy volume of RAMB18E1 is
1.03%,
Therefore on a fpga chip, the number of Q at most can be set as 80.
It should be noted that each embodiment in this specification is all described by the way of going forward one by one, each embodiment weight
Point explanation is all difference with other embodiment, between each embodiment identical similar partly mutually referring to.
For device class embodiment, due to itself and embodiment of the method basic simlarity, so description is fairly simple, related part ginseng
See that the part of embodiment of the method illustrates.
Last in addition it is also necessary to explanation, herein, such as first and second or the like relational terms be used merely to by
One entity or operation are made a distinction with another entity or operation, and not necessarily require or imply these entities or operation
Between there is any this actual relation or order.And, term " inclusion ", "comprising" or its any other variant meaning
Covering comprising of nonexcludability, so that including a series of process of key elements, method, article or equipment not only include that
A little key elements, but also include other key elements being not expressly set out, or also include for this process, method, article or
The intrinsic key element of equipment.In the absence of more restrictions, the key element being limited by sentence "including a ...", does not arrange
Remove and also there is other identical element in the process including described key element, method, article or equipment.
For convenience of description, it is divided into various units to be respectively described with function when describing apparatus above.Certainly, implementing this
The function of each unit can be realized in same or multiple softwares and/or hardware during application.
As seen through the above description of the embodiments, those skilled in the art can be understood that the application can
Mode by software plus necessary general hardware platform to be realized.Based on such understanding, the technical scheme essence of the application
On in other words prior art is contributed partly can be embodied in the form of software product, this computer software product
Can be stored in storage medium, such as ROM/RAM, magnetic disc, CD etc., include some instructions use so that a computer equipment
(can be personal computer, server, or network equipment etc.) executes some of each embodiment of the application or embodiment
Partly described method.
Above multiple phase-shift keying signal detecting system provided herein is described in detail, herein should
With specific case, the principle of the application and embodiment are set forth, the explanation of above example is only intended to help reason
Solution the present processes and its core concept；Simultaneously for one of ordinary skill in the art, according to the thought of the application,
All will change in specific embodiment and range of application, in sum, this specification content should not be construed as to this Shen
Restriction please.
Claims (8)
1. a kind of multiple phase-shift keying signal detecting system, based on field programmable gate array it is characterised in that including：Q
Multiple phase-shift keying signal detects subsystem, and described Q multiple phase-shift keying signal detection subsystem parallel computation is same
The cost function value of individual user, and each multiple phase-shift keying signal detects that the initial value of subsystem is different, described Q be more than
Integer equal to 1；
Determiner, for determining that minimum cost function value corresponding transmission data signal in Q cost function value is multi-system
Phase shift keyed signal testing result；
Wherein, any one multiple phase-shift keying signal detection subsystem includes：R renovator, comparator ＆ phase place renovator,
Error calculator, controller and random access memory；
Described r renovator, for calculating vectorial r, described y=H according to formula r=y-R × expROM (Φ)hZ, described Φ are angle
Index vector, described expROM (Φ) is the exponential quantity of described Φ, described R=HhH, described h are conjugate transposition, and described H is letter
Road matrix-vector or Spread Spectrum Matrix vector, described z is received signal vector, and the initial value of described Φ is Φq, described ΦqIt is q
During individual leggy down and out options, bk, the initial angle set of k=1,2 ... K, described K represents K user, described bkUse for k-th
The transmission data signal at family, described q=1 ... Q；
Described comparator ＆ phase place renovator, for updating described Φ；
Described error calculator, for according to formulaCalculate described J (b), described J
B () is cost function value, describedIt is the mathematic sign taking real part, described b is that the respective transmission data signal of k user forms
Transmission data signal vector；
Described controller, for controlling the operation between described r renovator, comparator ＆ phase place renovator and error calculator；
Described random access memory, for storing described R, described y, described Φ and described r.
2. multiple phase-shift keying signal detecting system according to claim 1 is it is characterised in that described random access memory
Including：
R random access memory, for storing described R；
Y random access memory, for storing described y；
Φ random access memory, for storing described Φ；
R random access memory, for storing described r.
3. multiple phase-shift keying signal detecting system according to claim 2 is it is characterised in that described r renovator bag
Include：
First dual-ported memory, for exportingWithDescribedA output end for described first dual-ported memory
The exponential quantity of mouth output, describedExponential quantity for the B output port output of described first dual-ported memory；
6 DSP, the respectively the first DSP, the 2nd DSP, the 3rd DSP, the 4th DSP, the 5th DSP and the 6th DSP, described first
DSP, described 2nd DSP and described 3rd DSP are a DSP group, and described 4th DSP, the 5th DSP and the 6th DSP are the 2nd DSP
Group, a described DSP group and described 2nd DSP group parallel running, a described DSP group is for calculating the real part of described r, described
2nd DSP group is for calculating the imaginary part of described r；
Described 3rd DSP, for exporting the real part of described r, the real part of described r is
rkIt is k-th value of vectorial r, ΦnIt is n-th angle, n=0,1 ... K-1, Rk,nIt is the n-th train value of the row k of matrix R,It is to take
The mathematic sign of imaginary part；
Described 6th DSP, for exporting the imaginary part of described r, the imaginary part of described r is
A described DSP, described 2nd DSP, described 4th DSP and described 5th DSP all with described first dual-ported memory
Output port be connected；
Each DSP in a described DSP group each respectively with the B port of R random access memory, the B port of y random access memory and
The B port of r random access memory is connected, each B port, the y with R random access memory respectively of each DSP in described 2nd DSP group
The B port of random access memory is connected with the B port of r random access memory；
5 logic multiplexers MUX, the respectively the first MUX, the 2nd MUX, the 3rd MUX, the 4th MUX and the 5th MUX；
A described MUX is used for selecting Φ random access memory port, and described 2nd MUX and described 3rd MUX are used for selecting y random
Port memory, described 4th MUX is used for exporting the real part of described r, and described 5th MUX is used for exporting the imaginary part of described r；
Multiple first registers, described first register and the DSP in a described DSP group and corresponding random access memory phase
Even；
Multiple second registers, described second register and the DSP in described 2nd DSP group and corresponding random access memory phase
Even.
4. multiple phase-shift keying signal detecting system according to claim 3 is it is characterised in that a described DSP bag
Include the 6th MUX, described 2nd DSP includes the 7th MUX and the 8th MUX, and described 3rd DSP includes the 9th MUX, described 4th DSP
Including the tenth MUX, described 5th DSP includes the 11st MUX and the 12nd MUX, and described 6th DSP includes the 13rd MUX；
Described 6th MUX, the 7th MUX, the tenth MUX and the 11st MUX, are respectively used to set the pre- adder of bypass；
Described 8th MUX and described 12nd MUX, is respectively used to first clock period selection in every K clock cycle
Two MUX and the 3rd MUX export and in remaining K-1 clock period selection 0；
Described 9th MUX and described 13rd MUX, is respectively used to first clock period selection 0 in every K clock cycle,
Feed back in K-1 clock period selection.
5. multiple phase-shift keying signal detecting system according to claim 4 is it is characterised in that described comparator ＆ phase
Position renovator includes：
Second dual-ported memory, for exportingWithDescribed ΦkSend the angle of information for k-th user, described
D is the step-length of travel(l)ing phase, and described j is imaginary unit, the Φ of described second dual-ported memorykInput port and described Φ with
The A port of machine memory is connected, and described d is input to the d port of described second dual-ported memory；
3rd dual-ported memory, for exportingAnd ejd, the Φ of described 3rd dual-ported memorykInput port and institute
The A port stating Φ random access memory is connected, and described d is input to the d port of described 3rd dual-ported memory；
4 DSP, the respectively the 7th DSP, the 8th DSP, the 9th DSP and the tenth DSP, wherein said 7th DSP and the 8th DSP group
The 3rd DSP group, described 9th DSP and the tenth DSP is become to form the 4th DSP group, described 3rd DSP group and the parallel fortune of the 4th DSP group
OK, described 3rd DSP group is for calculating cp, described cpFor positive rotation, described 4th DSP group is for calculating cn, described cnFor negative rotation
Turn；
The A port of r random access memory is connected with the r port of described 7th DSP, the 8th DSP, the 9th DSP and the tenth DSP respectively；
Described 7th DSP, for exporting described cp；
Described 9th DSP, for exporting described cn；
Determining device, is connected with described 7th DSP and described 9th DSP, for judging c respectivelypAnd cnSign bit, in described cp
Sign bit be 1 when, triggering the 14th MUX outputIn described cnSign bit when being 1, triggering described the
14 MUX outputs
Described 14th MUX is connected with described r renovator, will be described：WithIt is respectively written into described r renovator
Port andPort；
Multiple 3rd registers, described 3rd register and the DSP in described 3rd DSP group and corresponding random access memory phase
Even；
Multiple 4th registers, described 4th register and the DSP in described 4th DSP group and corresponding random access memory phase
Even.
6. multiple phase-shift keying signal detecting system according to claim 5 is it is characterised in that described error calculator
Including：
4th dual-ported memory, for exporting ejΦ；
3 DSP, the respectively the 11st DSP, the 12nd DSP and the 13rd DSP；
15th MUX；
Wherein, Φ random access memory B port is connected with the A address port of the 4th dual-ported memory, and described 4th dual-port is deposited
The A data-out port of reservoir is connected with the 11st DSP and the 12nd DSP respectively, and the B port of r random access memory is respectively with
11 DSP and the 12nd DSP are connected, and the B port of y random access memory is connected with the 11st DSP and the 12nd DSP respectively；
Described 13rd DSP, for exporting
7. multiple phase-shift keying signal detecting system according to claim 6 it is characterised in that described 11st DSP,
The connected mode of described 12nd DSP and described 13rd DSP is cascade.
8. the multiple phase-shift keying signal detecting system according to claim 3-7 any one is it is characterised in that described
The type of DSP is specially DSP48E1.
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| CN1545283A (en) * | 2003-11-25 | 2004-11-10 | 复旦大学 | Software radio system for MPSK digital signal moddemod |
| CN101197639A (en) * | 2006-12-04 | 2008-06-11 | 华为技术有限公司 | Signal detection method and system, transmission device and receiving device |
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