CN103956990B - The digital filter of parallel processing - Google Patents

Abstract

Parallel processing digital wave filter, has N rank (N is even number), including: N/2 modular construction A: comprise 4 multipliers, two adders；N/2 modular construction B: comprise 4 multipliers, two adders；N+1 tap coefficient, is N+1 multiplier；Modular construction A as the first module only comprises 2 multipliers and 1 adder, and whole device only comprises 1 multiplier of 5N and 1 adder of 3N；The denominator of described modular construction A and modular construction B alternately cascade shaping filter transmission function, the parameter in described a series of tap coefficients and all modules is collectively forming the molecule of filter transfer function.

Description

The digital filter of parallel processing

Technical field

The invention belongs to digital processing field, be specifically related to the numeral filter of a kind of parallel processing Ripple device.

Technical background

Digital filter is one of most important ingredient in Digital Signal Processing, by extensively It is applied to voice, image procossing, digital communication, analysis of spectrum, pattern recognition, automatically controls Field.Reality is applied, does not require nothing more than digital filter configuration simple, limited wordlength is imitated Should possess the strongest robustness, because a digital filter designed needs by special Digital device realizes, and the digital device of these limited wordlengths is often substantially reduced wave filter Performance, it can be caused what is more to realize unsuccessfully.Therefore, study and design has been highly resistant to The most succinct digital filter of limit word length effect is always the study hotspot of scholars.

Since the forties, parallel processing technique is as application problem research and the product of industrial development Thing, has obtained development at full speed, and its application includes that the area of computer aided of VLSI circuit sets Meter, artificial intelligence, Aero-Space and defense strategy research etc..Parallel processing technique is mainly to calculate Method is core, and software and hardware is as a kind of structure connecting each other and mutually restricting of implementation tool Technology.Described parallel processing thought is that the efficiently realization of digital filter provides possibility.

For a N rank digital filter, normalized lattice type digital filter (A.H.Gray, Jr. and J.D Markel,“A normalized filter structure,”IEEE Trans.on Acoust., Speech, Signal Processing, vol.ASSP-23, pp.268-277, Jun., 1975.) containing only There is 5N+1 multiplier, and there is the strongest anti-finite word length effect ability.Described normalizing Although changing lattice digital filter is to have modular structure, but when processing in real time module it Between do not accomplish Parallel Implementation, this limit to a certain extent its application and development.

Summary of the invention

The present invention is the disadvantages mentioned above overcoming prior art, it is provided that a kind of have modular structure also Row processes digital filter.

Parallel processing digital wave filter of the present invention, it is characterised in that: there is N rank (N For even number), including:

N/2 modular construction A: comprise 4 multipliers, two adders；Often come one Pulse clock, the value in chronotron is as signal f_k+1Enter rear stage module；Previous stage comes Signal f_kThe signal b come with rear stage_k+1Respectively with parameter-sin φ_kWith cos φ_kIt is multiplied defeated Entering to first adder A1, the value obtained is deposited in described chronotron, for subsequent time Calculating is prepared；Meanwhile, the signal f that described previous stage comes_kThe letter come with described rear stage Number b_k+1Respectively with parameter cos φ_kWith sin φ_kIt is multiplied and is input to second adder A2, formed Signal b_kPrepare for previous stage module；

N/2 modular construction B: comprise 4 multipliers, two adders；Often come one Pulse clock, the signal f that previous stage comes_kThe signal value characterized with chronotron respectively with parameter -sinφ_kWith cos φ_kIt is multiplied and is input to first adder B1, the signal f of formation_k+₁For rear one Level module is prepared；Meanwhile, the signal f that described previous stage comes_kThe letter characterized with chronotron Number value respectively with parameter cos φ_kWith sin φ_kIt is multiplied and is input to second adder B2, formation Signal b_kPrepare for previous stage module；And the signal b that rear stage comes_k+1To in chronotron Value be updated, the calculating for subsequent time is prepared；

N+1 tap coefficient, is N+1 multiplier；

Modular construction A as first module only comprises 2 multipliers and 1 addition Device, whole device only comprises 5N-1 multiplier and 3N-1 adder；

The alternately cascade shaping filter transmission of described modular construction A and modular construction B The denominator of function, the parameter in described a series of tap coefficients and all modules is collectively forming filter The molecule of ripple device transmission function.The parallel principle of described wave filter shows:

During assuming that wave filter calculates, the time needed for a sub-addition and multiplication of doing is respectively T_aAnd T_m.Alternately cascade in view of described modules A and described module B, it is to avoid signal edge Forward direction branch road (or backward branch road) from first module directly to last module, simultaneously, Described alternately cascade defines the parallel computation of wave filter.It is characterized in that following two walks Rapid: 1) the chronotron output of the chronotron output of first module and second module respectively with The most adjacent parameter is multiplied, i.e.-sin φ₂、cosφ₂With cos φ₂、sinφ₂, and respectively Enter two adders, be output as step 2 accordingly) to prepare, this calculating process takies Time be T_a+T_m.In this time, 2k+1 module and the 2nd (k+1) individual module Calculation as described first module and second module (k=1,2 ..., N/2-1), And complete to calculate accordingly.2) according to the result of calculation of step 1), to prolonging in N number of module Time device carry out numerical value renewal: for first module, input signal u (n) and-sin φ₁It is multiplied Result adds backward output signal and the cos φ of second module₁The result being multiplied, the knot obtained Fruit updates chronotron；For second module, the output of forward signal and cos φ₃The knot being multiplied Fruit updates chronotron plus the result of the backward output signal of the 3rd module, the result obtained； The chronotron of 2k+1 module updates similar with first module；2nd (k+1) individual module Chronotron updates similar with second module.The renewal of described N number of chronotron is also to be parallel Process, all time-consuming T of the calculating between each two template_a+T_m。

Beneficial effects of the present invention is mainly manifested in:

1. the two generic module structures of the present invention alternate cascade, effectively cut off letter Number from input a step calculate output defect (compared to normalized lattice type filter Device) so that complete the operand of equivalent in clock pulses, it is achieved that locate parallel every time The purpose of reason, greatly increases the handling capacity of wave filter.

2. two generic module structures described in entirely define dividing of transmission function by cascade Mother, and meet the condition of input Balancing relization, i.e. reach controlled Lindsey Graham square Battle array is the purpose of unit battle array, greatly reduces the probability that filter status overflows.

3. two generic module structures described in are prone to VLSI and realize and reduce cost.

Accompanying drawing explanation

Fig. 1 is the structural representation of modules A of the present invention.

Fig. 2 is the structural representation of module B of the present invention.

Fig. 3 is the structural representation of the present invention 4 rank wave filter.

Fig. 4 is the structural representation of N rank of the present invention wave filter.

Detailed description of the invention

Referring to the drawings, the present invention is further illustrated:

As it is shown in figure 1, the modules A of the present invention comprises four multipliers, two adders and one Individual chronotron.Often carrying out a pulse clock, the value in chronotron is as signal f_k+1After entrance one Level module；The signal f that previous stage comes_kThe signal b come with rear stage_k+1Respectively with parameter -sinφ_kWith cos φ_kBe multiplied and be input to first adder A1, the value obtained be deposited into described in prolong Time device in, the calculating for subsequent time is prepared；Meanwhile, the signal f that described previous stage comes_k The signal b come with described rear stage_k+1Respectively with parameter cos φ_kWith sin φ_kIt is multiplied and is input to Second adder A2, the signal b of formation_kPrepare for previous stage module.

As in figure 2 it is shown, module B of the present invention comprises four multipliers, two adders and one Individual chronotron.Often carry out a pulse clock, the signal f that previous stage comes_kCharacterized with chronotron Signal value respectively with parameter-sin φ_kWith cos φ_kIt is multiplied and is input to first adder B1, shape The signal f become_k+₁Prepare for rear stage module；Meanwhile, the signal f that described previous stage comes_k The signal value characterized with chronotron respectively with parameter cos φ_kWith sin φ_kIt is multiplied and is input to second Adder B2, the signal b of formation_kPrepare for previous stage module；And the letter that rear stage comes Number b_k+1Being updated the value in chronotron, the calculating for subsequent time is prepared.

Based on two generic module structures shown in Fig. 1 and Fig. 2, Fig. 3 gives the present invention 4 rank The structural representation of wave filter.The parallel process of of the present invention wave filter is described in detail below. During assuming that wave filter calculates, the time needed for doing a sub-addition and multiplication is respectively T_aWith T_m.Alternately cascade in view of described modules A and described module B, it is to avoid signal is along forward direction Branch road (or backward branch road) from first module directly to last module, simultaneously, described Alternately cascade define the parallel computation of wave filter.It is characterized in that following two step: 1) First module chronotron output with the chronotron of second module export respectively with respective phase Adjacent parameter is multiplied, i.e.-sin φ₂、cosφ₂With cos φ₂、sinφ₂, and respectively enter two Individual adder, is output as step 2 accordingly) prepare, the time that this calculating process takies For T_a+T_m.Simultaneously, the calculating of the 3rd module and the 4th module with described first Module is the same with second module.2) according to the result of calculation of step 1), to four modules In chronotron carry out numerical value renewal: for first module, input signal u (n) and-sin φ₁ The result being multiplied adds backward output signal and the cos φ of second module₁The result being multiplied, The result arrived updates chronotron；For second module, the output of forward signal and cos φ₃ The result being multiplied updates plus the result of the backward output signal of the 3rd module, the result obtained Chronotron；The chronotron of the 3rd module updates similar with first module；4th module is prolonged Time device value directly updated by the output valve of its forward signal.The renewal of described four chronotron is Parallel processing, need time-consuming T_a+T_m。

Fig. 4 is that to characterize is the structural representation of N rank wave filter, the principle of its parallel processing Ibid.

The computational methods that the present invention relates to digital filter configuration parameter are given below.

As shown in Figure 4, the structural parameters of described digital filter include { sin φ_k,cosφ_kAnd {ξ_m}.Wherein, described { sin φ_k,cosφ_kCalculating can be found in document " A canonical representation of input-balanced realizations for discrete-time systems,” (S.P.Zhu,Y.Wang,G.Li and C.R.Wan,in Proc.of the2010IEEE International on Green Circuits and Systems-ICGCS2010,Jun.2010.)。 For convenience, the digital filter that document above is corresponding is defined as R₀={A₀,B₀,C₀, d}, Digital filter corresponding to the present invention is defined as R={A, B, C, d}.Theoretical according to system structure Understand, { ξ_m, it is the element that vector [C d] is corresponding, can be by similarity transformation by R₀Obtain. According to Fig. 4, as known { sin φ_k,cosφ_kOn the premise of }, arranged side by side by analyzing state variable Go out corresponding relation formula and i.e. can get A, B, then similitude transformation matrix T can be given by:

T=W₀W^-1

Wherein, W₀A is had respectively with W₀,B₀With A, B determine, meet

$\left\{\begin{array}{c}{W}_0=\left[\begin{array}{cccc}{B}_0& A_0{B}_0& \·\·\·& A_0^{N-1}{B}_0\end{array}\right]\\ W=\left[\begin{array}{cccc}B& \mathrm{AB}& \·\·\·& A^{N-1}B\end{array}\right]\end{array}\right.$

Therefore, it can be easy for obtaining C=C₀T。

Content described in this specification embodiment is only the row of the way of realization to inventive concept Lifting, protection scope of the present invention is not construed as being only limitted to the concrete shape that embodiment is stated Formula, protection scope of the present invention also and is caned according to present inventive concept in those skilled in the art The equivalent technologies means expected.

Claims (1)

1. parallel processing digital wave filter, it is characterised in that: there are N rank (N is even number), Including:

N/2 modular construction A: comprise 4 multipliers, two adders；Often come one Pulse clock, the value in chronotron is as signal f_k+1Enter rear stage module；Previous stage comes Signal f_kThe signal b come with rear stage_k+1Respectively with parameter-sin φ_kWith cos φ_kIt is multiplied defeated Entering to first adder A1, the value obtained is deposited in described chronotron, for the meter of subsequent time It is considered preparation；Meanwhile, the signal f that described previous stage comes_kThe signal come with described rear stage b_k+1Respectively with parameter cos φ_kWith sin φ_kIt is multiplied and is input to second adder A2, the letter of formation Number b_kPrepare for previous stage module；

N/2 modular construction B: comprise 4 multipliers, two adders；Often come one Pulse clock, the signal f that previous stage comes_kThe signal value characterized with chronotron respectively with parameter -sinφ_kWith cos φ_kIt is multiplied and is input to first adder B1, the signal f of formation_k+1For rear stage Module is prepared；Meanwhile, the signal f that described previous stage comes_kThe signal characterized with chronotron Value respectively with parameter cos φ_kWith sin φ_kIt is multiplied and is input to second adder B2, the signal of formation b_kPrepare for previous stage module；And the signal b that rear stage comes_k+1Value in chronotron is entered Row updates, and the calculating for subsequent time is prepared；

N+1 tap coefficient, is N+1 multiplier；

Modular construction A as first module only comprises 2 multipliers and 1 adder, Whole device only comprises 5N-1 multiplier and 3N-1 adder；

Described modular construction A and modular construction B alternately cascade shaping filter transmission letter The denominator of number, the parameter in described a series of tap coefficients and all modules is collectively forming filtering The molecule of device transmission function；

Corresponding coefficient ζ is multiplied by the output of every one-level_k(k=1,2 ..., N) it is added afterwards, add ζ₀With The product of u (n) obtains exporting y (n).