CN103956182B - Random access storage device unit structure, random access storage device and operation method of random access storage device - Google Patents
Random access storage device unit structure, random access storage device and operation method of random access storage device Download PDFInfo
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Abstract
The invention provides a random access storage device unit structure, a random access storage device and an operation method of the random access storage device. The random access storage device unit structure comprises an N-type door diode, a P-type diode pipe, an N-type transistor and a P-type transistor, wherein a source electrode of the N-type transistor is connected with internal device adjustable low voltage; the source electrode of the P-type transistor is connected with internal device adjustable power supply voltage; a drain electrode of the N-type transistor is connected with a grid electrode of the P-type transistor; the grid electrode of the N-type transistor is connected with the drain electrode of the P-type transistor; the drain electrode of the N-type door diode is connected with a bit line; the grid electrode of the N-type door diode is connected with a write word line; the source electrode of the N-type door diode is connected to a first node between the drain electrode of the N-type transistor and the grid electrode of the P-type transistor; the drain electrode of the P-type door diode is connected with a complementary bit line; the grid electrode of the P-type door diode is connected with a read word line; the source electrode of the P-type door diode is connected to a second node between the grid electrode of the N-type transistor and the drain electrode of the P-type transistor. The random access storage device unit structure is simple to control, high in integration level, stable and reliable.
Description
Technical field
The invention belongs to memory device technical field is and in particular to a kind of random access memory cell structure, random visit
Ask memorizer and its holding, writing, reading and method for refreshing bulk.
Background technology
Random access storage device (Random Access Memory, RAM) refers to can randomly, individually by instruction
Each memory element is conducted interviews, accesses substantially stationary and unrelated with memory unit address can the reading and writing of required time
Memorizer.MOS type memorizer can be divided into dynamic ram (Dynamic RAM, DRAM) and static RAM by information location mode again
(Static RAM, SRAM).
DRAM is dynamic random access memory, and due to its density and speed, DRAM is as most commonly seen Installed System Memory.
The memory cell of DRAM is capacitor, and its included electric charge can be revealed in time, leads to the loss of data .DRAM can only be by
Data keeps the very short time.In order to prevent this phenomenon from occurring it is necessary to refresh (Refresh) once every a period of time, if
Memory element is not refreshed, and the information of storage will be lost.DRAM refreshing frequency (Refresh Frequency) depends on system
Make Technology and the design of this body structure of memory cell.DRAM refreshing frequency will affect RAM memory service behaviour with
Power consumption.The shortcoming of DRAM is:With constantly reducing of integrated circuit fabrication process characteristic size, original DRAM structure storage
Tube grid electric leakage will significantly increase, and storage information will be lost quickly.The present invention adopts new RAM structure, can be effectively increased
Storage tube grid storage charge storage time, reduces refreshing frequency, thus reducing circuit dynamic power consumption, readwrite performance will be changed
Kind.
SRAM storage circuit is based on flip and flop generator, in stable condition, as long as not power down, information would not be lost.
Its advantage is not need to refresh, and control circuit is simple, but integrated level relatively low it is adaptable to not need the department of computer science of large storage capacity
System.The shortcoming of SRAM is：Integrated level is relatively low, and the DRAM internal memory of identical capacity can be designed as less volume, but SRAM
But need very big volume, and power consumption is larger.So SRAM memory will take a part of area on mainboard.
Content of the invention
It is contemplated that at least solving one of above-mentioned technical problem to a certain extent or providing at a kind of useful business
Industry selects.For this reason, it is an object of the invention to proposing a kind of simple, the reliable and stable random access memory cell knot of control
Structure, random access storage device and its operation operational approach.
The random access memory cell structure of first aspect present invention embodiment, including：N-type door pipe (NG1), p-type door
Pipe (PG1), N-type transistor (N1) and P-type transistor (P1), wherein, the source electrode of described N-type transistor (N1) and device inside can
Turn down voltage VSSI to be connected, the source electrode of described P-type transistor (P1) is connected with device inside regulated power supply voltage VDDI, described N
The drain electrode of transistor npn npn (N1) is connected with the grid of described P-type transistor (P1), the grid of described N-type transistor (N1) with described
The drain electrode of P-type transistor (P1) is connected, and the drain electrode of described N-type door pipe (NG1) is connected with bit line BL, described N-type door pipe (NG1)
Grid is connected with write wordline WWL, and the source electrode of described N-type door pipe (NG1) connects drain electrode and institute to described N-type transistor (N1)
State the primary nodal point (Q) between the grid of P-type transistor (P1), the drain electrode of described p-type door pipe (PG1) and paratope line BLn phase
Even, the grid of described p-type door pipe (PG1) is connected with reading wordline RWL, and the source electrode of described p-type door pipe (PG1) connects to described N
Secondary nodal point (Qn) between the grid of the drain electrode of transistor npn npn (N1) and described P-type transistor (P1).
In one embodiment of the invention, the threshold voltage absolute value of described N-type transistor (N1) is more than described N-type door
The threshold voltage absolute value of pipe (NG1), and, the threshold voltage absolute value of described P-type transistor (P1) is more than described p-type door pipe
(PG1) threshold voltage absolute value.
The random access storage device of second aspect present invention embodiment, including multiple aforesaid random access memory cells
Structure.
This random access storage device also has control circuit simply, and in stable condition, as long as not power down, information would not be lost
Lose, the advantages of low in energy consumption.The random access storage device integrated level of the present invention is of a relatively high, becomes SOC system storage IP on piece
The effective solution of core memory element is it is adaptable to jumbo computer system.
The holding operational approach of the random access storage device of third aspect present invention embodiment, is applied to aforesaid random visit
Ask memorizer, including：WWL maintains low level；RWL maintains high level；BL maintains low level；BLn maintains high level；VDDI maintains
Secondary high level；VSSI maintains time low level.
The write operation method of the random access storage device of fourth aspect present invention embodiment, is applied to aforesaid random visit
Ask memorizer, one of operation strategy can be chosen using the following two kinds：(1) all data that address is chosen with operation row are read
Operation；Then, action column is chosen for address, the data write storage unit being written into；For non-selected action column, will be first
The data storage of front reading re-writes memory element.(2) after carrying out address decoding, by row decoding gained row address signal and row
The column address signal of decoding gained carries out logical operationss, for choosing row to carry out write operation, and non-selected row, no operate.
In one embodiment of the invention, for the write operation choosing row, write using three sections, including：WWL is
One write phase is low level, is high level in the second write phase and the 3rd write phase；RWL is in the first write phase and the second write phase
It is high level for low level, in the 3rd write phase；During write " 1 ", BL is in the first write phase, the second write phase and the 3rd write phase
Maintain high level, or, during write " 0 ", BL maintains low level in the first write phase, the second write phase and the 3rd write phase；BLn
Maintain high level in the first write phase, the second write phase and the 3rd write phase；VDDI is in the first write phase, the second write phase and
Three write phases maintain time high level；Maintain time low level with VSSI in the first write phase, the second write phase and the 3rd write phase.
The read operation method of the random access storage device of fifth aspect present invention embodiment, is applied to aforesaid random visit
Ask memorizer, read using two sections, including：WWL maintains low level in the first read phase and the second read phase；RWL is in the first reading
Stage is high level, is low level in the second read phase；BL maintains low level in the first read phase and the second read phase；Read
When " 1 ", BLn is that high level, the second write phase are gradually decreased to low level from high level in the first read phase, or, read " 0 "
When, BLn maintains high level in the first read phase and the second read phase；VDDI maintains high electricity in the first read phase and the second read phase
Flat；VSSI maintains time low level in the first read phase and the second read phase.
The method for refreshing bulk of the random access storage device of sixth aspect present invention embodiment, is applied to aforesaid random visit
Ask memorizer, including：WWL maintains Vthn, described VthnVoltage for described N-type door pipe (NG1) and described N-type transistor (N1)
Absolute value the greater in threshold value；RWL maintains (high level-Vthp), described VthpIt is described p-type door pipe (PG1) and described p-type crystalline substance
The greater in the voltage threshold of body pipe (P1)；BL maintains low level；BLn maintains high level；VDDI maintains time high level；VSSI ties up
Hold time low level.
The holding of the random access storage device of the present invention, writing, reading and this four generic operations method that refreshes control simple, shape
State is stable, as long as not power down, information would not be lost, low in energy consumption.Integrated level is of a relatively high compared with SRAM, becomes SOC on piece
The effective solution of system storage IP kernel memory element is it is adaptable to Large Copacity computer system.
The additional aspect of the present invention and advantage will be set forth in part in the description, and partly will become from the following description
Obtain substantially, or recognized by the practice of the present invention.
Brief description
The above-mentioned and/or additional aspect of the present invention and advantage will become from reference to the description to embodiment for the accompanying drawings below
Substantially and easy to understand, wherein：
Fig. 1 is the schematic diagram of the random access memory cell structure of the embodiment of the present invention；
Fig. 2 is the holding time sequential routine figure of the random access memory cell structure of the embodiment of the present invention；
Fig. 3 is the write operation sequential chart of the random access memory cell structure of the embodiment of the present invention；
Fig. 4 is the read operation sequential chart of the random access memory cell structure of the embodiment of the present invention；
Fig. 5 is the refresh operation sequential chart of the random access memory cell structure of the embodiment of the present invention；
Fig. 6 is the integrated operation sequential chart of the random access memory cell structure of the embodiment of the present invention.
Specific embodiment
Embodiments of the invention are described below in detail, the example of described embodiment is shown in the drawings, wherein from start to finish
The element that same or similar label represents same or similar element or has same or like function.Below with reference to attached
The embodiment of figure description is exemplary it is intended to be used for explaining the present invention, and is not considered as limiting the invention.
1. random access storage device SSRAM cellular construction
The present invention proposes a kind of random access storage device (Shrunken static RAM) cellular construction, as Fig. 1 institute
Show, including：N-type door pipe (NG1), p-type door pipe (PG1), N-type transistor (N1) and P-type transistor (P1).Wherein：N-type transistor
(N1) source electrode is adjustable with device inside, and low-voltage VSSI is connected.The source electrode of P-type transistor (P1) and device inside regulated power supply
Voltage VDDI is connected.The drain electrode of N-type transistor (N1) is connected with the grid of P-type transistor (P1).The grid of N-type transistor (N1)
Drain electrode with P-type transistor (P1) is connected.The drain electrode of N-type door pipe (NG1) is connected with bit line BL.The grid of N-type door pipe (NG1) with
Write wordline WWL is connected.The source electrode of N-type door pipe (NG1) connects drain electrode and P-type transistor (P1) to N-type transistor (N1)
Primary nodal point (Q) between grid.The drain electrode of p-type door pipe (PG1) is connected with paratope line BLn.The grid of p-type door pipe (PG1)
It is connected with reading wordline RWL.The source electrode of p-type door pipe (PG1) connects drain electrode and P-type transistor (P1) to N-type transistor (N1)
Grid between secondary nodal point (Qn).
In the random access memory cell structure of this embodiment：N-type door pipe (NG1) is write data control switch, uses
In control whether write data.P-type door pipe (PG1) is to read data control switch, is used for controlling whether to read data.N-type is brilliant
Body pipe (N1) is data information memory pipe, and the stored amount of charge of grid capacitance represents institute's data storage information.P-type transistor
(P1) it is load pipe, for keeping the stored electric charge of N-type transistor grid capacitance.The SSRAM cellular construction of the present invention and DRAM
Compare and only need special refreshing on a small quantity, control circuit is simple, and in stable condition, as long as not power down, information would not be lost, power consumption
Low.Random access storage device SSRAM cellular construction integrated level compared with SRAM of the present invention is of a relatively high, becomes SOC system on piece
The effective solution of system memory I P core memory element is it is adaptable to jumbo computer system.
In one embodiment of the invention, the threshold voltage absolute value of N-type transistor (N1) is more than N-type door pipe (NG1)
Threshold voltage absolute value, and, the threshold voltage absolute value of P-type transistor (P1) be more than p-type door pipe (PG1) threshold voltage
Absolute value.Table 1 shows the parts selection situation in a specific embodiment.So arrange, device storage information can be improved
Stability.Reason in detail is expanded on further below.
Table 1 parts selection example of parameters
| Metal-oxide-semiconductor title | Metal-oxide-semiconductor type | Threshold voltage example |
| NG1 | Level threshold value NMOS | Vthn=0.41 |
| N1 | High threshold NMOS | Vthn=0.513 |
| P1 | High threshold PMOS | Vthp=-0.535 |
| PG1 | Level threshold value PMOS | Vthp=-0.438 |
2. random access storage device SSRAM
The invention also discloses a kind of random access storage device, it includes multiple random access storage device lists disclosed above
Meta structure.
Due to having similar structure, therefore this random access storage device also has control circuit simply, in stable condition, only
Otherwise power down, information would not be lost, the advantages of low in energy consumption.The SSRAM integrated level of the present invention is of a relatively high, becomes SOC on piece
The effective solution of system storage IP kernel memory element is it is adaptable to jumbo computer system.
3. the operational approach of random access storage device SSRAM
The operational approach of random access storage device SSRAM includes holding, writing, reading, refreshes four kinds.Concrete introduction is such as
Under.
3.1 random access storage device SSRAM keep operation
As shown in Fig. 2 for the random access storage device of the present invention, keeping operational approach to include：WWL maintains low level；
RWL maintains high level；BL maintains low level；BLn maintains high level；VDDI maintains time high level；VSSI maintains time low level.
When memory element is in holding " 0 " state：Q point storage information is " 0 ", when Qn point storage information is " 1 ", P1 and N1
Pipe is in off state.But the electric leakage due to P1 and N1 pipe, Q point voltage will slowly rise, Qn point voltage will slowly under
Fall.The unlatching of N1 pipe or the decline of Qn point voltage is led to lead to P1 pipe to be opened if Q point voltage rises, storage information is lost.For protecting
It is low for holding Q point voltage, takes P1 to be that high threshold PMOS reduces leakage current, and NG1 increases leakage current for level threshold value NMOS tube (to be protected
Hold state：VDDI is high level, and BL is grounded).For keeping Qn point voltage to be height, N1 is taken to be that high threshold NMOS tube reduces electric leakage
Stream, PG1 increases leakage current (hold mode for level threshold value NMOS tube：VSSI is high level, and BLn is charged to high level in advance).
When memory element is in holding one state：Q point storage information is " 1 ", when Qn point storage information is " 0 ", P1 and N1
Pipe is in conducting state.Memory element retention performance is good.
As seen from the above, this holding operational approach has the advantage that：
(1) improve SSRAM memory element stability：Upper analysis understands according to this, if Q point voltage rises leads to N1 pipe
VG-VSSI>Vthn, then N1 pipe unlatching, Qn point voltage is drop-down, and unit storage information is lost；P1 is led to manage if Qn point voltage declines
VG-VDDI<Vthp, then P1 pipe unlatching, Q point voltage pulls up, and unit storage information is lost.Stable for improving SSRAM memory element
Property, in hold mode, adjustment unit low and high level is VSSI=0.25v, VDDI=0.85v to the present invention.
(2) reduce SSRAM memory element quiescent dissipation：Improve the VSSI voltage of hold mode, the electric leakage of N1 pipe will be reduced
Stream；Reduce the VDDI voltage of hold mode, P1 tube leakage current will be reduced, for reducing SSRAM memory element quiescent dissipation, the present invention
In hold mode, adjustment unit low and high level is VSSI=0.25v, VDDI=0.85v.
3.2 random access storage device SSRAM write operations
Consider array size, simultaneously peration data width, the factor such as operating rate, propose two kinds of differences and choose operation
Strategy：
Choose operation strategy 1：First, all data that address is chosen with operation row carry out read operation.Then, for address
Choose action column, the data write storage unit being written into；For non-selected action column, by previously read data storage weight
New write storage unit.
Choose operation strategy 2：After carrying out address decoding, by the row ground of row decoding gained row address signal and column decoding gained
Location signal carries out logical operationss, for choosing row to carry out write operation, and non-selected row, no operate.
For the present invention random access storage device choose row, write operation method adopt three sections write, as Fig. 3 institute
Show, including：WWL is low level, is high level in the second write phase and the 3rd write phase in the first write phase；RWL writes first
Stage and the second write phase are low level, are high level in the 3rd write phase；During write " 1 ", BL in the first write phase, second write
Stage and the 3rd write phase maintain high level, or, during write " 0 ", BL writes rank in the first write phase, the second write phase and the 3rd
Section maintains low level；BLn maintains high level in the first write phase, the second write phase and the 3rd write phase；VDDI writes rank first
Section, the second write phase and the 3rd write phase maintain time high level；VSSI is in the first write phase, the second write phase and the 3rd write phase
Maintain time low level.
It should be noted that when memory element write " 0 ", P1 pipe is become an OFF state by conducting state, N1 pipe is by leading
Logical state becomes an OFF state, and Qn node write " 1 " time is longer.For reducing the write time, the present invention, in write operation, adopts
Write with three sections.When memory element write " 1 ", need to be opened N1 pipe by off state, need VG-VSSI>Vthn.Due to
The threshold value loss of NG1 pipe, Q point voltage can not completely write " 1 ", and N1 pipe is opened and had difficulties.The present invention, in write state, adjusts
Whole unit low and high level is VSSI=0v, VDDI=0.85v.
3.3 random access storage device SSRAM read operations
As shown in figure 4, for the random access storage device of the present invention, read operation method adopts two sections of readings, including：
WWL maintains low level in the first read phase and the second read phase；RWL is high level in the first read phase, in the second read phase is
Low level；BL maintains low level in the first read phase and the second read phase；When reading " 1 ", BLn is high electricity in the first read phase
Flat, the second write phase is gradually decreased to low level from high level, or, when reading " 0 ", BLn is in the first read phase and the second reading rank
Section maintains high level；VDDI maintains high level in the first read phase and the second read phase；VSSI is in the first read phase and the second reading
Stage maintains time low level.
It should be noted that when memory element reads information " 0 ", BLn does not discharge, and need not consider speed and power consumption.When
When memory element reads information " 1 ", BLn passes through N1 tube discharge, and N1 tube discharge speed determines reading speed.Therefore Q point voltage is higher,
Reading speed is faster.In reading state, adjustment unit low and high level is VSSI=0v, VDDI=1.2v to the present invention.
3.4 random access storage device SSRAM refresh operations
As shown in figure 5, for the random access memory cell structure of the present invention, method for refreshing bulk includes：WWL maintains
In Vthn, VthnFor absolute value the greater in the voltage threshold of N-type door pipe (NG1) and N-type transistor (N1)；RWL maintains (high electricity
Flat-Vthp), VthpFor the greater in the voltage threshold of p-type door pipe (PG1) and P-type transistor (P1)；BL maintains low level；BLn ties up
Hold high level；VDDI maintains time high level；VSSI maintains time low level.
Although it should be noted that the methods such as the design of multi thresholds unit, the dynamic adjustment of supply voltage that above employ increase
Memory element reliability, but for further reduce risk, need memory element is carried out with effectively overall refreshing.
To sum up four generic operation, can obtain the integrated operation sequential chart of SSRAM, as shown in Figure 6.As seen from the figure, the present invention
The operational approach of SSRAM control simple, in stable condition, as long as not power down, information would not be lost, low in energy consumption.With SRAM phase
More of a relatively high than integrated level, become the effective solution of SOC system storage IP kernel memory element on piece it is adaptable to Large Copacity
Computer system.
In the description of this specification, term " first ", " second " be only used for describe purpose, and it is not intended that instruction or
Hint relative importance or the implicit quantity indicating indicated technical characteristic.Thus, " first ", the spy of " second " are defined
Levy and can express or implicitly include one or more this feature.In describing the invention, " multiple " are meant that
Two or more, unless otherwise expressly limited specifically.
In the description of this specification, unless otherwise clearly defined and limited, term " installation ", " being connected ", " connection ",
Terms such as " fixations " should be interpreted broadly, for example, it may be being fixedly connected or being detachably connected, or is integrally connected；
Can be to be mechanically connected or electrically connect；Can be to be joined directly together it is also possible to be indirectly connected to by intermediary, permissible
It is the connection of two element internals.For the ordinary skill in the art, above-mentioned art can be understood as the case may be
Language concrete meaning in the present invention.
In the description of this specification, reference term " embodiment ", " some embodiments ", " example ", " specifically show
The description of example " or " some examples " etc. means specific features, structure, material or the spy describing with reference to this embodiment or example
Point is contained at least one embodiment or the example of the present invention.In this manual, to the schematic representation of above-mentioned term not
Necessarily refer to identical embodiment or example.And, the specific features of description, structure, material or feature can be any
One or more embodiments or example in combine in an appropriate manner.
Although embodiments of the invention have been shown and described above it is to be understood that above-described embodiment is example
Property it is impossible to be interpreted as limitation of the present invention, those of ordinary skill in the art is in the principle without departing from the present invention and objective
In the case of above-described embodiment can be changed within the scope of the invention, change, replace and modification.
Claims (9)
1. a kind of random access memory cell structure is it is characterised in that include：N-type door pipe (NG1), p-type door pipe (PG1), N
Transistor npn npn (N1) and P-type transistor (P1), wherein,
Source electrode low-voltage VSSI adjustable with device inside of described N-type transistor (N1) is connected, the source of described P-type transistor (P1)
Pole is connected with device inside regulated power supply voltage VDDI, the drain electrode of described N-type transistor (N1) and described P-type transistor (P1)
Grid is connected, and the grid of described N-type transistor (N1) is connected with the drain electrode of described P-type transistor (P1),
The drain electrode of described N-type door pipe (NG1) is connected with bit line BL, the grid of described N-type door pipe (NG1) and write wordline WWL phase
Even, the source electrode of described N-type door pipe (NG1) connects the grid of the drain electrode to described N-type transistor (N1) and described P-type transistor (P1)
Primary nodal point (Q) between pole,
The drain electrode of described p-type door pipe (PG1) is connected with paratope line BLn, the grid of described p-type door pipe (PG1) with read wordline
RWL is connected, and the source electrode of described p-type door pipe (PG1) connects drain electrode and described P-type transistor to described N-type transistor (N1)
(P1) secondary nodal point (Qn) between grid.
2. random access memory cell structure according to claim 1 is it is characterised in that described N-type transistor (N1)
Threshold voltage absolute value be more than the threshold voltage absolute value of described N-type door pipe (NG1), and, described P-type transistor (P1)
Threshold voltage absolute value is more than the threshold voltage absolute value of described p-type door pipe (PG1).
3. a kind of random access storage device is it is characterised in that include the random access storage device described in multiple claim 1 or 2
Cellular construction.
4. a kind of holding operational approach of random access storage device is it is characterised in that be applied to the random visit described in claim 3
Ask memorizer, including：
WWL maintains low level；RWL maintains high level；BL maintains low level；BLn maintains high level；VDDI maintains time high level；
VSSI maintains time low level.
5. a kind of write operation method of random access storage device is it is characterised in that be applied to the random visit described in claim 3
Ask memorizer, using choosing operation strategy as follows：All data that address is chosen with operation row carry out read operation；Then, for
Action column is chosen in address, the data write storage unit being written into；For non-selected action column, by previously read storage number
According to re-writing memory element.
6. a kind of write operation method of random access storage device is it is characterised in that be applied to the random visit described in claim 3
Ask memorizer, using choosing operation strategy as follows：After carrying out address decoding, by row decoding gained row address signal and column decoding institute
Column address signal carry out logical operationss, for choosing row to carry out write operation, and non-selected row, no operate.
7. the write operation method of the random access storage device as described in claim 5 or 6 is it is characterised in that for choosing row
Write operation, using three sections write, including：
WWL is low level, is high level in the second write phase and the 3rd write phase in the first write phase；
RWL is low level, is high level in the 3rd write phase in the first write phase and the second write phase；
During write " 1 ", BL maintains high level in the first write phase, the second write phase and the 3rd write phase, or, during write " 0 ",
BL maintains low level in the first write phase, the second write phase and the 3rd write phase；
BLn maintains high level in the first write phase, the second write phase and the 3rd write phase；
VDDI maintains time high level in the first write phase, the second write phase and the 3rd write phase；With
VSSI maintains time low level in the first write phase, the second write phase and the 3rd write phase.
8. a kind of read operation method of random access storage device is it is characterised in that be applied to the random visit described in claim 3
Ask memorizer, read using two sections, including：
WWL maintains low level in the first read phase and the second read phase；
RWL is high level in the first read phase, is low level in the second read phase；
BL maintains low level in the first read phase and the second read phase；
When reading " 1 ", BLn is that high level, the second write phase are gradually decreased to low level from high level in the first read phase, or,
When reading " 0 ", BLn maintains high level in the first read phase and the second read phase；
VDDI maintains high level in the first read phase and the second read phase；
VSSI maintains time low level in the first read phase and the second read phase.
9. a kind of method for refreshing bulk of random access storage device is it is characterised in that be applied to the random visit described in claim 3
Ask memorizer, including：
WWL maintains Vthn, described VthnFor in the voltage threshold of described N-type door pipe (NG1) and described N-type transistor (N1) definitely
Value the greater；
RWL maintains (high level-Vthp), described VthpVoltage for described p-type door pipe (PG1) and described P-type transistor (P1)
The greater in threshold value；
BL maintains low level；
BLn maintains high level；
VDDI maintains time high level；
VSSI maintains time low level.
Priority Applications (5)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410155104.XA CN103956182B (en) | 2014-04-17 | 2014-04-17 | Random access storage device unit structure, random access storage device and operation method of random access storage device |
| CN201410729870.2A CN104637530B (en) | 2014-04-17 | 2014-12-04 | A kind of redundancy structure random access storage device |
| PCT/CN2015/076891 WO2015158305A1 (en) | 2014-04-17 | 2015-04-17 | Cell structure of random access memory, random access memory and operation methods |
| US14/772,371 US9812190B2 (en) | 2014-04-17 | 2015-04-17 | Cell structure of 4T random access memory, random access memory and operation methods |
| US15/446,807 US9947390B2 (en) | 2014-04-17 | 2017-03-01 | Structure and methods of operating two identical 4T random access memories storing the same data |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410155104.XA CN103956182B (en) | 2014-04-17 | 2014-04-17 | Random access storage device unit structure, random access storage device and operation method of random access storage device |
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| Publication Number | Publication Date |
|---|---|
| CN103956182A CN103956182A (en) | 2014-07-30 |
| CN103956182B true CN103956182B (en) | 2017-02-15 |
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| CN102332299A (en) * | 2011-07-28 | 2012-01-25 | 上海宏力半导体制造有限公司 | SRAM (System Random Access Memory) unit |
| CN103632729A (en) * | 2012-08-27 | 2014-03-12 | 三星电子株式会社 | Semiconductor memory device and system having redundancy cells |
| CN103632715A (en) * | 2013-05-08 | 2014-03-12 | 中国科学院电子学研究所 | Two-module redundancy configuration memory unit circuit used in programmable logic device |
| CN103730468A (en) * | 2012-10-16 | 2014-04-16 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure, forming method of semiconductor structure, SRAM memory unit and SRAM memorizer |
| CN103730151A (en) * | 2012-10-12 | 2014-04-16 | 爱思开海力士有限公司 | Semiconductor memory device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102332299A (en) * | 2011-07-28 | 2012-01-25 | 上海宏力半导体制造有限公司 | SRAM (System Random Access Memory) unit |
| CN103632729A (en) * | 2012-08-27 | 2014-03-12 | 三星电子株式会社 | Semiconductor memory device and system having redundancy cells |
| CN103730151A (en) * | 2012-10-12 | 2014-04-16 | 爱思开海力士有限公司 | Semiconductor memory device |
| CN103730468A (en) * | 2012-10-16 | 2014-04-16 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure, forming method of semiconductor structure, SRAM memory unit and SRAM memorizer |
| CN103632715A (en) * | 2013-05-08 | 2014-03-12 | 中国科学院电子学研究所 | Two-module redundancy configuration memory unit circuit used in programmable logic device |
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