CN103955919B - A kind of SIFT feature vector gradient rectangular histogram multichannel more novel circuit - Google Patents

Abstract

The invention discloses a kind of SIFT feature vector gradient rectangular histogram multichannel more novel circuit, replace the rectangular histogram of 1 128 dimension 16 renewal using the set of histograms that 16 octuples four update, the rectangular histogram that each octuple four updates represents the subcharacter value vector of the NBO direction dimension of the same space position.Described circuit includes：First Tri linear interpolation module, the second Tri linear interpolation module, direction address arbitration modules, the first to the 16th four-way update arbitration modules, the first to the 16th octuple four-way updates Histogram module.The circuit hardware area overhead of the present invention only accounts for the 28% of the histogram circuit area overhead of tradition 128 dimension 16 renewal.In terms of hardware spending, this circuit is with the obvious advantage；And under the technique of SMIC0.18um, the maximum operating frequency of the present invention is 130MHz, the histogram circuit maximum operating frequency of tradition 128 dimension 16 renewal is 100MHz.

Description

A kind of SIFT feature vector gradient rectangular histogram multichannel more novel circuit

Technical field

The invention belongs to technical field of image processing, many more particularly, to a kind of SIFT feature vector gradient rectangular histogram Passage more novel circuit.

Background technology

SIFT (Scale-invariant Feature Transform, Scale invariant features transform) is by D.G.Lowe Develop and carry out perfect, and be widely used in a kind of operator in image registration field at present.This operator is to image characteristic point Neighborhood is described, and then calculates characteristic vector, and this feature vector is respectively provided with invariance to gray scale, yardstick and rotation, and to making an uproar Sound, visual angle and radiation conversion also have a certain degree of resistance.The characteristic vector of this high stability is conducive to joining of later stage Quasi- work.

SIFT operator is divided into four steps：Metric space extreme point detects；Characteristic point is accurately positioned；Fit characteristic point master Orientation angle；Calculate characteristic point characteristic vector.

The calculating of characteristic vector is that the Image neighborhood centered on key point is divided into NBP × NBP sub-regions, is in Pixel in same sub-regions participates in the statistical computation of the gradient orientation histogram of same NBO dimension.So, finally The SIFT feature vector obtaining is exactly the vector of NBP × NBP × NBO dimension.In original SIFT algorithm, NBP=4, NBO=8, this Sample one, each SIFT feature vector is 128 dimensions.And each pixel participating in characteristic vector calculating can be linear by three The computational methods of interpolation, contribute to characteristic vector.Tri linear interpolation computing is by the gradient magnitude of a pixel, according to Distance proportion distributes the multiple dimensions in 128 dimensional feature vectors, in most 8 dimensions.This 8 dimensions are horizontally oriented phase respectively The adjacent both direction in two adjacent vectors, two vertically adjacent vectors and direction.Fig. 1 describes empty in two dimension Between the value of middle pixel be inserted into the method in characteristic vector histogrammic respective straight square column.After coordinate axess in Fig. 1 are rotation And the coordinate axess being stretched；The region that box indicating pixel to be scanned is located；The point of 16 Lycoperdon polymorphum Vitt is located at respectively The center of the direction histogram sweep limitss of same group of NBO dimension；Stain is some pixel to be sampled, its coordinate be (nx, ny,nt).Can be determined that from its locus, this sampled point will be interpolated into a in two-dimensional space, this four NBO of b, c, d Dimension direction Histogram in figure.Interpolation dimension bx of horizontal direction, vertical direction and angle, by, bt are：

Bx=[nx-0.5]

By=[ny-0.5]

B θ=[n θ]

And rbx, rby, rbt are the relative distance of the direction histogram of the pixel and lower left being sampled:

Rbx=nx-bx

Rby=ny-by

Rbt=nt-bt

In order to improve the throughput of characteristic vector part calculating, each clock cycle is scanned to two pixels and counts Calculate.So, each clock cycle of histogram circuit at most have 16 dimensions Nogata post need update.And histogram circuit More new route is more, and address repeatability arbitrated logic is more complexity.The address of the simple histogram circuit of 128 dimension 16 renewal Repeated arbitrated logic complexity is high, if point multistage flowing water, to complete address arbitration, can cause the rectangular histogram number of complexity again According to read/write conflict.Meanwhile, complicated logic circuit can make the surge of hardware area expense again.In sum, traditional higher-dimension Not only area overhead is big more for the degree histogram circuit updating, and also extremely easily becomes the critical path of integral module design.

Content of the invention

The technical problem to be solved is to overcome existing SIFT feature vector 16 renewal channel histogram circuit Address repeatability arbitrated logic complexity high, the big problem of hardware area cost.There is provided a kind of hardware area less, and energy Work SIFT feature vector gradient rectangular histogram multichannel more novel circuit at higher frequencies.

SIFT feature vector gradient rectangular histogram multichannel more novel circuit is to be come using the set of histograms that 16 octuples four update Replace the rectangular histogram of 1 128 dimension 16 renewal.The rectangular histogram that each octuple four updates represents the NBO direction of the same space position The subcharacter value vector of dimension.SIFT feature vector gradient rectangular histogram multichannel more novel circuit includes：First Tri linear interpolation mould Block, the second Tri linear interpolation module, direction address arbitration modules, the first four-way update arbitration modules, the second four-way updates Arbitration modules, the 3rd four-way update arbitration modules, the 4th four-way updates arbitration modules, the 5th four-way updates arbitration mould Block, the 6th four-way update arbitration modules, the 7th four-way update arbitration modules, the 8th four-way update arbitration modules, the 9th Four-way updates arbitration modules, the tenth four-way updates arbitration modules, the 11st four-way updates arbitration modules, the 12nd four-way Road updates arbitration modules, the 13rd four-way updates arbitration modules, the 14th four-way updates arbitration modules, the 15th four-way Update arbitration modules, the 16th four-way updates arbitration modules, the first octuple four-way updates Histogram module, the second octuple four Passage updates Histogram module, the 3rd octuple four-way updates Histogram module, the 4th octuple four-way updates Histogram module, 5th octuple four-way updates Histogram module, the 6th octuple four-way updates Histogram module, the 7th octuple four-way updates Histogram module, the 8th octuple four-way update Histogram module, the 9th octuple four-way updates Histogram module, the tenth octuple Four-way updates Histogram module, the 11st octuple four-way updates Histogram module, the 12nd octuple four-way updates Nogata Module, the 13rd octuple four-way update Histogram module, the 14th octuple four-way update Histogram module, the 15th Dimension four-way updates Histogram module, the 16th octuple four-way updates Histogram module.

The first described Tri linear interpolation module, the second Tri linear interpolation inside modules function are according to pixel level side To determine the serial number of four set of histograms that this pixel participates in calculating to interpolation dimension bx, by of, vertical direction, and by 16 Corresponding four modules in individual arbitration modules enable signal (cen) and put one.Judge to participate in meter according to interpolation dimension bt of angle Direction address in four set of histograms calculated, and export this two address value add_bin0, add_bin1.One or three linearly inserts The address value of value output, the address value of the second Tri linear interpolation output, totally four address values and the first to the 16th four-way be more New arbitration modules are connected.According to relative distance rbx of pixel and the direction histogram of lower left, rby, rbt, and pixel Weighted value (mg) carry out Tri linear interpolation and be calculated 8 interpolation value.Four for add_bin0 in wherein direction address are inserted Value value is according to by d0_bin0, d1_bin0, d2_bin0, d3_bin0, d4_bin0, d5_bin0, d6_bin0, d7_bin0, d8_ This 16 passages of bin0, d9_bin0, d10_bin0, d11_bin0, d12_bin0, d13_bin0, d14_bin0, d15_bin0 In the output of 4 passages, and the sequence number of this four passages is identical with enable signal (cen) sequence number being set to.To wherein direction Address is four interpolation value of add_bin1 according to by d0_bin1, d1_bin1, d2_bin1, d-3_bin1, d4_bin1, d5_ bin1,d6_bin1,d7_bin1,d8_bin1,d9_bin1,d10_bin1,d11-_bin1,d12_bin1,d13_bin1, 4 passage outputs in this 16 passages of d14_bin1, d15_bin1, and the sequence number of this four passages is believed with the enable being set to Number (cen) sequence number is identical.

The built-in function of described direction address arbitration modules is to the address by the first Tri linear interpolation module output Add_bin0 [0], add_bin1 [0] and address add_bin0 [1], add_bin1 by the second Tri linear interpolation module output [1] repeatability between is arbitrated, and generates marking signal flag.

The built-in function that described first updates arbitration modules to the 16th four-way is by linearly inserting from the one or three The enable signal cen0 of value module output, to judge being first with the enable signal cen1 from the second Tri linear interpolation module output Whether 2 pixels processing contribute to the subcharacter histogram vector of this sequence number.Arbitrate the first Tri linear interpolation module defeated Address add_bin0 [1], add_ that the address add_bin0 [0] going out, add_bin1 [0] are exported with the second Tri linear interpolation module The repeatability of bin1 [1] this four group address.Therefore four-way updates arbitration modules output signal output useful signal vd0, vd1,vd2,vd3；Address signal addr0, addr1, addr2, addr3；Data signal dat0, dat1, dat2, dat3.This 12 Individual signal updates Histogram module with octuple four-way and is connected.

It is to complete histogrammic adding up that described first to the 16th octuple four-way updates Histogram module built-in function Work.Each octuple four-way updates the octuple subcharacter vector that Histogram module can export the same space coordinate.This 16 8 Dimensional vector forms 128 dimensional feature vectors { his0, his1, his2 ..., his127 } of SIFT.For example, the first octuple four-way Updating Histogram module output vector is { his0, his1, his2 ..., his7 }；16th octuple four-way more new histogram Module output vector is { his120, his121, his122 ..., his127 }.

The present invention has the advantage that compared with prior art：

1) the circuit hardware area overhead of the present invention only accounts for the histogram circuit area overhead of tradition 128 dimension 16 renewal 28%.In terms of hardware spending, this circuit is with the obvious advantage；

2) under the technique of SMIC 0.18um, the maximum operating frequency of the present invention is 130MHz, tradition 128 dimension 16 renewal Histogram circuit maximum operating frequency be 100MHz.

Brief description

Fig. 1 is pixel gradient value bilinear Interpolation Principle schematic diagram in prior art；

Fig. 2 is each submodule connection diagram of SIFT feature vector gradient rectangular histogram multichannel more novel circuit in the present invention；

Fig. 3 is Tri linear interpolation modular structure circuit diagram in the embodiment of the present invention；

Fig. 4 is direction address arbitration modules functional schematic in the embodiment of the present invention；

Fig. 5 is that in the embodiment of the present invention, four-way updates arbitration modules structural circuit figure.

Specific embodiment

In order that the objects, technical solutions and advantages of the present invention become more apparent, below in conjunction with drawings and Examples, right The present invention is further elaborated.It should be appreciated that specific embodiment described herein is only in order to explain the present invention, and It is not used in the restriction present invention.As long as additionally, involved technical characteristic in each embodiment of invention described below The conflict of not constituting each other just can be mutually combined.

Shown in Fig. 2, SIFT feature vector gradient rectangular histogram multichannel more novel circuit includes：First Tri linear interpolation module (201), the second Tri linear interpolation module (201), direction address arbitration modules (202), the first to the 16th four-way renewal are secondary Cut out module (203), the first to the 16th octuple four-way updates Histogram module (204).Fig. 2 is connection diagram, due to making The area of pictural surface is limited, only draws first (203 (1)) and the 16th (203 (16)) four-way updates arbitration modules；First (204 (1)) and the 16th (204 (16)) octuple four-way update Histogram module.

The output of first, second Tri linear interpolation module (201) enables signal connected mode：Cen0 and the first four-way are more New arbitration modules (203 (1)) are connected, and cen1 updates arbitration modules (203 (2)) with the second four-way and is connected, by that analogy, Cen15 updates arbitration modules (203 (16)) with the 16th four-way and is connected.The output of first, second Tri linear interpolation module is inserted Value data signal connected mode：D0_bin0 with d0_bin1 updates arbitration modules (203 (1)) with the first four-way and is connected, d1_ Bin0 with d1_bin1 updates arbitration modules (203 (2)) with the second four-way and is connected, by that analogy, d15_bin0 and d15_bin1 Update arbitration modules (203 (16)) with the 16th four-way to be connected.The OPADD signal of first, second Tri linear interpolation module Connected mode：Add_bin0 with add_bin1 updates arbitration modules (203) with 16 four-ways and is connected one by one.

The input signal of direction address arbitration modules (202) is the output ground from first, second Tri linear interpolation module Location, add_bin0 and add_bin1.Output identification signal flag updates arbitration modules (203) phase with the first to the 16th four-way Even.

The output signal that each four-way updates arbitration modules (203) can update Histogram module with an octuple four (204) it is connected, and the sequence number of this Histogram module (204) is identical with four-way renewal arbitration modules (203).That is, the first four-way Road is updated arbitration modules (203 (1)) and is connected with the first octuple four renewal Histogram module (204 (1)).

Shown in Fig. 3, Tri linear interpolation module (201) structural circuit figure.Bt signal two-stage is deposited and is carried out ' plus 1 ' and processes After deposit and respectively obtain both direction address add_bin0, add_bin1.Rbx, rby, rbt pass through three subtractions with weighted value mg Device, 20 multipliers complete Tri linear interpolation computing in one-level flowing water, are calculated 8 interpolation value：d0,d1,d2,d3,d4, d5,d6,d7.Bx, by pass through one multiplier of three adders and carry out after one-level deposits, and computing obtains the sky of sampling pixel points Between address parameter ind_sub：

Ind_sub=(by+3) × 5+bx+3

Sel module is a decoding logic, shown in its logical relation table 1

Table 1

Shown in Fig. 4, direction address arbitration modules (202) function compares two Tri linear interpolation modules (201) and exports The repeatability of direction address.Repeat under three kinds of shown in the diagram scenes of this four addresses.Scene 1, the one or three linearly inserts Value module (201 (1)) OPADD add0_bin0 and the second Tri linear interpolation module (201 (2)) OPADD add1_bin1 Repeat, now direction address arbitration modules (202) output identification signal flag value is ' 01 '；Scene 2, the first Tri linear interpolation mould Block (201 (1)) OPADD add0_bin1 and the second Tri linear interpolation module (201 (2)) OPADD add1_bin0 repeats, Now direction address arbitration modules (202) output identification signal flag value is ' 10 '；Scene 3, the first Tri linear interpolation module (201 (1)) OPADD add0_bin0, add0_bin1 and the second Tri linear interpolation module (201 (2)) OPADD add1_ Bin1, add1_bin1 repeat, and now direction address arbitration modules (202) output identification signal flag value is ' 00 '.Except secondary three Plant outside scene, the situation that direction address is repeated, direction address arbitration modules (202) output identification signal flag value will not occur For ' 11 '.

Shown in Fig. 5, four-way updates arbitration modules (203) by 21 four input MUX and 11 depositor groups Become.Enable the control signal that signal cen0, cen1 and marking signal flag are this 21 MUX.

When cen1 is equal to 1 and cen0 and is equal to 1, it is all invalid to represent two input data passages, all output signals (vd0, Vd1, vd2, vd3, dat0, dat1, dat2, dat3, add0, add1, add2, add3) it is all 0.

Cen1 is equal to 1 and when cen0 is equal to 0, only first input data passage be described effectively, therefore unlatching first, second Output data passage, vd0, vd1 will put one, vd2, vd3 set to 0；The value of the first output interpolated data (dat0) is d0_bin0, The value of the second output interpolated data (dat1) is d0_bin1, and the 3rd output interpolated data (dat2) exports interpolated data with the 4th (dat3) value is all 0；First OPADD (add0) is add0_bin0, and the second OPADD (add1) is add0_bin1, The value of the 3rd OPADD (add2) and the 4th OPADD (add3) is all 0.

Cen1 is equal to 0 and when cen0 is equal to 1, only Article 2 input data passage effectively, therefore opens first, second output Data channel, vd0, vd1 will put one, vd2, vd3 set to 0；The value of the first output interpolated data (dat0) is d1_bin0, second The value of output interpolated data (dat1) is d1_bin1, and the 3rd output interpolated data (dat2) exports interpolated data with the 4th (dat3) value is all 0；First OPADD (add0) is add1_bin0, and the second OPADD (add1) is add1_bin1, The value of the 3rd OPADD (add2) and the 4th OPADD (add3) is all 0.

Cen1 be equal to 0 and cen0 be equal to 0 when, illustrate first.Second input data passage is all effective, the interpolation now exporting Data signal and the address signal exporting are by marking signal control.When flag is equal to ' 11 ', it is the phenomenon not having address to repeat.Cause This opens first, second, third, fourth input data signal, vd0, vd1, d2, vd3 will put one；First output interpolation number Value according to (dat0) is d0_bin0, and the value of the second output interpolated data (dat1) is d0_bin1, the 3rd output interpolated data (dat2) it is d1_bin0, the value of the 4th output interpolated data (dat3) is d1_bin1；First OPADD (add0) is add0_ Bin0, the second OPADD (add1) is add0_bin1, and the 3rd OPADD (add2) is add1_bin0, the 4th OPADD (add3) value is all add1_bin1.When flag is equal to ' 10 ', input address add0_bin1 are repeated with add1_bin0.Therefore Open first, second, third input data signal, vd0, vd1, d2 will put one；The value of the first output interpolated data (dat0) For d0_bin0, the value of the second output interpolated data (dat1) is the value preset of d0_bin1 and d1_bin0, the 3rd output interpolated data (dat2) it is d1_bin1, the value of the 4th output interpolated data (dat3) is 0；First OPADD (add0) is add0_bin0, Second OPADD (add1) is add0_bin1, and the 3rd OPADD (add2) is add1_bin1, the 4th OPADD (add3) value is all 0.When flag is equal to ' 01 ', input address add0_bin0 are repeated with add1_bin1.Therefore open first, Second, third input data signal, vd0, vd1, d2 will put one；The value of the first output interpolated data (dat0) is d1_bin0, The value of the second output interpolated data (dat1) is the value preset of d0_bin0 and d1_bin1, and the 3rd output interpolated data (dat2) is D0_bin1, the value of the 4th output interpolated data (dat3) is 0；First OPADD (add0) is add1_bin0, the second output Address (add1) is add1_bin1, and the 3rd OPADD (add2) is add0_bin1, and the value of the 4th OPADD (add3) is all For 0.When flag is equal to ' 00 ', input address add0_bin0 and add1_bin0 repeat, input address add0_bin1 and add1_ Bin1 repeats.Therefore open first, second input data signal, vd0, vd1 will put one；First output interpolated data (dat0) Value be d0_bin0 and d1_bin0 value preset, second output interpolated data (dat1) value be d0_bin1 with d1_bin1's and Value, the 3rd output interpolated data (dat2) is 0, and the value of the 4th output interpolated data (dat3) is 0；First OPADD (add0) For add0_bin0, the second OPADD (add1) is add0_bin1, and the 3rd OPADD (add2) is 0, the 4th OPADD (add3) value is all 0.

Octuple four-way updates Histogram module (histogram_N8M4), due to the scale of dimension and monocycle renewal number All very littles, therefore can complete to read data, the cumulative, operation of write data within a clock cycle.Because not needing multilevel flow The operation of water, eliminates read/write address Conflicts management strategy.

As it will be easily appreciated by one skilled in the art that the foregoing is only presently preferred embodiments of the present invention, not in order to Limit the present invention, all any modification, equivalent and improvement made within the spirit and principles in the present invention etc., all should comprise Within protection scope of the present invention.

Claims (4)

1. a kind of SIFT feature vector gradient rectangular histogram multichannel more novel circuit is it is characterised in that include：First Tri linear interpolation Module, the second Tri linear interpolation module, direction address arbitration modules, the first four-way update arbitration modules, the second four-way more New arbitration modules, the 3rd four-way update arbitration modules, the 4th four-way updates arbitration modules, the 5th four-way updates arbitration mould Block, the 6th four-way update arbitration modules, the 7th four-way update arbitration modules, the 8th four-way update arbitration modules, the 9th Four-way updates arbitration modules, the tenth four-way updates arbitration modules, the 11st four-way updates arbitration modules, the 12nd four-way Road updates arbitration modules, the 13rd four-way updates arbitration modules, the 14th four-way updates arbitration modules, the 15th four-way Update arbitration modules, the 16th four-way updates arbitration modules, the first octuple four-way updates Histogram module, the second octuple four Passage updates Histogram module, the 3rd octuple four-way updates Histogram module, the 4th octuple four-way updates Histogram module, 5th octuple four-way updates Histogram module, the 6th octuple four-way updates Histogram module, the 7th octuple four-way updates Histogram module, the 8th octuple four-way update Histogram module, the 9th octuple four-way updates Histogram module, the tenth octuple Four-way updates Histogram module, the 11st octuple four-way updates Histogram module, the 12nd octuple four-way updates Nogata Module, the 13rd octuple four-way update Histogram module, the 14th octuple four-way update Histogram module, the 15th Dimension four-way updates Histogram module, the 16th octuple four-way updates Histogram module；Wherein：

Described first Tri linear interpolation module, the second Tri linear interpolation module, for according to pixel horizontal direction, vertical direction The serial number of four set of histograms that calculates to determine this pixel to participate in of interpolation dimension bx, by, and by 16 arbitration modules In corresponding four modules enable signal cen and put one；Judge four Nogatas participating in calculating according to interpolation dimension bt of angle Direction address in figure group, and export this two address value add_bin0, add_bin1；First Tri linear interpolation module output Two address values and two address values of the second Tri linear interpolation module output, totally four address values and the first to the 16th four-way Road updates arbitration modules and is connected；According to relative distance rbx of pixel and the direction histogram of lower left, rby, rbt, and picture The weighted value mg of vegetarian refreshments carries out Tri linear interpolation and is calculated 8 interpolation value, respectively d0, d1, d2, d3, d4, d5, d6, d7； Wherein d1, the direction address of tetra- interpolation value of d3, d5, d7 is add_bin0, the direction address of tetra- interpolation value of d0, d2, d4, d6 For add_bin1；By d1, the value of d3, d5, d7 is sent to d0_bin0, d1_bin0, d2_bin0, d3_bin0, d4_bin0, d- 5_bin0,d6_bin0,d7_bin0,d8_bin0,d9_bin0,d10_bin0,d11_bin0,d12_bin0,d-13_bin0, In corresponding passage in this 16 passages of d14_bin0, d15_bin0；By d0, the value of d2, d4, d6 is sent to d0_bin1, d1_ bin1,d2_bin1,d3_bin1,d4_bin1,d5_bin1,d6_bin1,d7_bin1,d8_bin1,d9_bin1,d10_ In corresponding passage in this 16 passages of bin1, d11_bin1, d12_bin1, d13_bin1, d14_bin1, d15_bin1；

Described direction address arbitration modules, for judge by first Tri linear interpolation module output address add_bin0 [0], Add_bin1 [0] and address add_bin0 [1], add_bin1 [1] by the second Tri linear interpolation module output, to this four ground The repeatability of location is arbitrated, and generates marking signal flag；

Described first updates arbitration modules to the 16th four-way, for according to making from the first Tri linear interpolation mould output Can signal cen0, to judge, with the enable signal cen1 from the second Tri linear interpolation module output, 2 pixels first processing Whether the subcharacter histogram vector of this serial number is contributed；Arbitrate the first Tri linear interpolation module OPADD add_bin0 [0], add_bin1 [0] and the second Tri linear interpolation module OPADD add_bin0 [1], the repeatability of add_bin1 [1]；Four Passage update arbitration modules output signal have output useful signal vd0, vd1, vd2, vd3, address signal addr0, addr1, Addr2, addr3, data signal dat0, dat1, dat2, dat3, this 12 signals update Histogram module with octuple four-way It is connected；

Described first updates Histogram module to the 16th octuple four-way, is used for completing histogrammic cumulative work, each Octuple four-way updates the octuple subcharacter vector that Histogram module is all used for exporting the same space coordinate, this 16 8 dimensional vectors 128 dimensional feature vectors { his0, his1, his2 ..., his127 } of composition SIFT.

2. circuit as claimed in claim 1 is it is characterised in that linearly insert in described first Tri linear interpolation module and the two or three In value module：Direction address add_bin0, add_bin1 are obtained by the interpolation dimension bt computing of angle：

$\begin{array}{c}\mathrm{add}\_\mathrm{bin}0=\mathrm{bt}\\ \mathrm{add}\_\mathrm{bin}1=\mathrm{bt}+1\end{array};$

Space address parameter ind_sub of sampling pixel points is obtained by horizontal direction, interpolation dimension bx of vertical direction and by computing Arrive：

Ind_sub=(by+3) × 5+bx+3；

Interpolation value d0, d1, d2, d3, d4, d5, d6, d7 are relative distance rbx of the direction histogram by pixel Yu lower left, Rby, rbt and mg, in the time of one-level flowing water, are obtained using 3 subtractors and 20 multiplier Tri linear interpolation；According to The value of space address parameter ind_sub, will enable 1 in signal cen0 to cen15, and 2 or 4 enable signal and put one； According to the value of space address parameter ind_sub, by interpolation value d1,1 in d3, d5, d7,2 or 4 are transferred to d0_ bin0,d1_bin0,d2_bin0,d3_bin0,d4_bin0,d5_bin0,d6_bin0,d7_bin0,d8_bin0,d9_bin0, Corresponding in this 16 data channel of d10_bin0, d11_bin0, d12_bin0, d13_bin0, d14_bin0, d15_bin0 1, in 2 or 4 data channel；According to the value of space address parameter ind_sub, by interpolation value d0,1 in d2, d4, d6 Individual, 2 or 4 are transferred to d0_bin1, d1_bin1, d2_bin1, d3_bin1, d4_bin1, d5_bin1, d6_bin1, d7_bin1,d8_bin1,d9_bin1,d10_bin1,d11_bin1,d12_bin1,d13_bin1,d14_bin1,d15_bin1 In this 16 data channel corresponding 1, in 2 or 4 data channel.

3. circuit as claimed in claim 1 or 2 is it is characterised in that described direction address arbitration modules are used for comparing two three The repeatability of the direction address of linear interpolation module output simultaneously output identification signal flag, wherein direction address duplicate packages contain three kinds Scene：Scene 1, when the first Tri linear interpolation module OPADD add_bin0 [0] and the second Tri linear interpolation module output ground Location add_bin1 [1] repeats, and now direction address arbitration modules output identification signal flag value is ' 01 '；Scene 2, the one or three line Property interpolating module OPADD add_bin1 [0] with second Tri linear interpolation module OPADD add_bin0 [1] repeat, now Direction address arbitration modules output identification signal flag value is ' 10 '；Scene 3, the address of the first Tri linear interpolation module output Add_bin0 [0], add_bin1 [0] the address add_bin0 [1], add_bin1 with the second Tri linear interpolation module output respectively [1] repeat, now direction address arbitration modules output identification signal flag value is ' 00 '；In addition to above-mentioned three kinds of scenes, will not There is the situation that direction address is repeated, direction address arbitration modules output identification signal flag value is ' 11 '.

4. circuit as claimed in claim 1 or 2 is it is characterised in that described four-way updates arbitration modules by 21 four inputs MUX and 11 depositor compositions, enabling signal cen0, cen1 and marking signal flag is this 21 four input multichannels The control signal of selector；

When cen1 is equal to 1 and cen0 and is equal to 1, it is all invalid to represent two input data passages, all output signals (vd0, vd1, Vd2, vd3, dat0, dat1, dat2, dat3, add0, add1, add2, add3) it is all 0；

Cen1 is equal to 1 and when cen0 is equal to 0, only first input data passage be described effectively, therefore opens first, second and export Data channel, vd0, vd1 will put 1, vd2, vd3 set to 0；The value of the first output interpolated data dat0 is d0_bin0, the second output The value of interpolated data dat1 is d0_bin1, and the 3rd output interpolated data dat2 with the value of the 4th output interpolated data dat3 is 0；First OPADD add0 be add0_bin0, the second OPADD add1 be add0_bin1, the 3rd OPADD add2 and The value of the 4th OPADD add3 is all 0；

Cen1 is equal to 0 and when cen0 is equal to 1, only Article 2 input data passage effectively, therefore opens first, second output data Passage, vd0, vd1 will put 1, vd2, vd3 set to 0；The value of the first output interpolated data dat0 is d1_bin0, the second output interpolation The value of data dat1 is d1_bin1, and the value of the 3rd output interpolated data dat2 and the 4th output interpolated data dat3 is all 0；The One OPADD add0 is add1_bin0, and the second OPADD add1 is add1_bin1, the 3rd OPADD add2 and the 4th The value of OPADD add3 is all 0；

Cen1 be equal to 0 and cen0 be equal to 0 when, illustrate that first, second input data passage is all effective, the interpolated data now exporting When signal controls flag to be equal to ' 11 ' with the address exporting by marking signal, it is the phenomenon not having address to repeat；Therefore open the First, second, third, Article 4 input data signal, vd0, vd1, d2, vd3 will put 1；First output interpolated data dat0's It is worth for d0_bin0, the value of the second output interpolated data dat1 is d0_bin1, the 3rd output interpolated data dat2 is d1_bin0, The value of the 4th output interpolated data dat3 is d1_bin1；First OPADD add0 is add0_bin0, the second OPADD Add1 is add0_bin1, and the 3rd OPADD add2 is add1_bin0, and the value of the 4th OPADD add3 is all add1_ bin1；When flag is equal to ' 10 ', input address add0_bin1 are repeated with add1_bin0；Therefore open first, second, third defeated Enter data signal, vd0, vd1, d2 will put 1；The value of the first output interpolated data dat0 is d0_bin0, the second output interpolation number According to dat1 value be d0_bin1 and d1_bin0 value preset, the 3rd output interpolated data dat2 is d1_bin1, the 4th output interpolation The value of data dat3 is 0；First OPADD add0 is add0_bin0, and the second OPADD add1 is add0_bin1, the 3rd OPADD add2 is add1_bin1, and the value of the 4th OPADD add3 is all 0；When flag is equal to ' 01 ', input address Add0_bin0 and add1_bin1 repeats；Therefore open first, second, third input data signal, will vd0, vd1, d2 put 1；The value of the first output interpolated data dat0 is d1_bin0, and the value of the second output interpolated data dat1 is d0_bin0 and d1_ The value preset of bin1, the 3rd output interpolated data dat2 is d0_bin1, and the value of the 4th output interpolated data dat3 is 0；First output Address add0 is add1_bin0, and the second OPADD add1 is add1_bin1, and the 3rd OPADD add2 is add0_bin1, The value of the 4th OPADD add3 is all 0；When flag is equal to ' 00 ', input address add0_bin0 are repeated with add1_bin0, defeated Enter address add0_bin1 and add1_bin1 to repeat；Therefore open first, second input data signal, vd0, vd1 will put 1； The value of the first output interpolated data dat0 is the value preset of d0_bin0 and d1_bin0, and the value of the second output interpolated data dat1 is The value preset of d0_bin1 and d1_bin1, the 3rd output interpolated data dat2 is 0, and the value of the 4th output interpolated data dat3 is 0；The One OPADD add0 is add0_bin0, and the second OPADD add1 is add0_bin1, and the 3rd OPADD add2 is 0, the The value of four OPADD add3 is all 0.