CN103947117B - The system and method for stable charging pump node voltage level - Google Patents

Abstract

A kind of method is included in tracking VT at the first circuit, and this first circuit coupled to the first drain node of the first power supply of electric charge pump.The method is additionally included in tracking VT at second circuit, and this second circuit coupled to the second drain node of the second source of electric charge pump.The method farther includes to stablize the first voltage of the first drain node and the second voltage of the second drain node in response to this VT.

Description

The system and method for stable charging pump node voltage level

I. field

The disclosure relates generally to stable charging pump node voltage level.

II. description of Related Art

Technological progress has caused calculating equipment more and more less and from strength to strength.Such as, there is currently various The Portable, personal of various kinds calculates equipment, sets including less, light weight and the wireless computing that is prone to be carried by user Standby, such as portable radiotelephone, personal digital assistant (PDA) and paging equipment.More specifically, Portable radiotelephone (such as cell phone and Internet protocol (IP) phone) can be passed by wireless network Reach voice-and-data packet.Additionally, many such radio telephones include being incorporated herein other kinds of Equipment.Such as, radio telephone may also include digital camera, DV, numeroscope and audio frequency File player.Equally, this type of radio telephone can process executable instruction, including can be used for accessing because of spy The software application of net, such as web browser application.Thus, these radio telephones can include significantly calculating Ability.

Circuits System in radio telephone and other electronic equipments can include the phaselocked loop generating output signal (PLL), the phase place of this output signal, frequency or both be " locked " to input signal (such as, Clock signal).Such as, phaselocked loop can include the voltage controlled oscillator (VCO) in response to electric charge pump.Phase place Detector can use " rising " and " decline " signal to control electric charge pump, and these signals make electric charge pump lead to Cross switching between charge path and discharge path in expectation tuning range, change the tune being supplied to VCO Humorous voltage.But, when designer reduce supply voltage with improve mobile device battery life time, electric charge pump Transistor may not have abundance headroom (that is, being likely not to have the degree of depth saturated).Consequently, it can happen " mismatch ", so that for generating the unlatching (on) of VT and closing (off) path mismatch, from And cause " electric charge is shared " on VT and injection effect.This mismatch can point out designer to increase to electricity The electric current of lotus pump or the tuning range of change VCO.But, these ways can increase power consumption or reduction The performance of mobile device.

III. summarize

The overall performance of PLL and reliability can be affected by the mismatch current in its electric charge pump.Such as, as Really current source and is later switched to pass through drain node to the first path offer electric current of electric charge pump by drain node Electric current, in the case of transistor the most in the charge pump does not has enough headroom, drain node is provided to the second path Voltage will change during handoff procedure.Relatively low supply voltage causes the headroom of the transistor in electric charge pump to subtract Few.Owing to the transistor headroom in electric charge pump reduces, the voltage of drain node can be aobvious during current path switches Write and change.The voltage change of this increase causes being supplied to the tuning of the voltage controlled oscillator (VCO) of PLL On voltage, enhanced charge is shared and is injected.And then, which increase charge pump mismatch electric current (such as, to The magnitude of current of the capacitor charging that VCO powers is relative to by the magnitude of current of this capacitor discharge).

Disclose the drain node voltage for tracking and stable charging pump (the electric charge pump in such as PLL) System and method.Follow the tracks of circuit and can follow the tracks of the tuning electricity of the voltage controlled oscillator (VCO) being supplied in PLL Pressure.VT can be tracked with at the grid following the tracks of the transistor that circuit is associated.During following the tracks of, When VT increases (and approaching the first supply voltage), follow the tracks of the N-shaped gold that circuit is associated with first Belonging to oxide semiconductor (NMOS) transistor will conducting.It addition, (and approach the when VT reduces Two supply voltages) time, follow the tracks of, with second, the p-type metal oxide semiconductor (PMOS) that circuit is associated Transistor will conducting.When following the tracks of the nmos pass transistor conducting that circuit is associated with first, VT Value by the voltage of the drain node of the tracked current source being partly associated with the stable PMOS with electric charge pump. When with second follow the tracks of circuit be associated PMOS transistor conducting time, the value of VT by tracked with surely The voltage of the drain node of the current source that the fixed NMOS part with electric charge pump is associated.During operation, often The voltage of individual corresponding drain node will be stablized (such as, the stable value at VT) during switching, Thus reduce the electric charge at the electric charge pump of PLL to share and injection problem.

In a specific embodiment, a kind of circuit includes coupleding to the first current source and coupleding to filling of capacitor Electricity current path.Charging current path includes the drain node of the first current source.This circuit also includes coupleding to Two current sources and coupled to the discharge current path of this capacitor.Discharge current path includes the second current source Drain node.This circuit farther includes to coupled to the first tracking circuit and coupling of the drain node of the first current source The second tracking circuit to the drain node of the second current source.First follows the tracks of Circuit responce comes in VT signal Optionally change to stablize the voltage level of the drain node of the first current source.Second follows the tracks of Circuit responce in tune Humorous voltage signal optionally changes to stablize the voltage level of the drain node of the second current source.

In another specific embodiment, a kind of circuit includes coupleding to the first current source and coupleding to capacitor Charging current path.Charging current path includes the drain node of the first current source.This circuit also includes coupleding to Second current source and coupled to the discharge current path of this capacitor.Discharge current path includes the second current source Drain node.This circuit farther includes for following the tracks of VT and for stablizing the leakage of the first current source The device of the drain node of node and the second current source.

In another specific embodiment, a kind of method is included in tracking VT at the first circuit, the first electricity Road coupled to the first drain node of the first power supply of electric charge pump.The method is additionally included at second circuit to follow the tracks of and adjusts Humorous voltage, second circuit coupled to the second drain node of the second source of electric charge pump.The method farther includes The first voltage and second voltage of the second drain node of the first drain node is stablized in response to VT.

The specific advantages provided by least one the disclosed embodiments is to reduce by being just applied to electric charge The supply voltage of pump reduces the ability of the charge pump mismatch electric current caused.Other aspects of the disclosure, advantage To be apparent from after having read whole application with feature, whole application includes following chapters and sections: accompanying drawing is briefly Bright, describe in detail and claim.

IV. Brief Description Of Drawings

Fig. 1 is the specific illustrative embodiment of the phaselocked loop of the electric charge pump including having voltage tracking circuit Block diagram；

Fig. 2 is the circuit diagram of the specific illustrative embodiment of the electric charge pump of Fig. 1 and voltage tracking circuit；

Fig. 3 is the node voltage level explaining orally stable charging pump circuit (circuit of such as Fig. 1 and Fig. 2) The flow chart of the specific embodiment of method；

Fig. 4 is that the radio communication following the tracks of circuit of the node voltage including can be used to stable charging pump sets Standby block diagram；And

Fig. 5 is that the electronics following the tracks of circuit of the node voltage manufacturing and including can be used to stable charging pump sets The data flow diagram of the specific illustrative embodiment of standby manufacture process.

V. describe in detail

With reference to Fig. 1, it is shown that the specific embodiment of phaselocked loop 100.Phaselocked loop 100 includes coupleding to voltage-controlled The electric charge pump 130 of agitator (VCO) 140.The output (Fvco) 150 of voltage controlled oscillator 140 is carried The input of supply electric charge pump 130, thus form feedback path.Electric charge pump 130 have PMOS part and NMOS part.Electric charge pump 130 can be configured to generate VT (Vtune) 116.VT (Vtune) 116 exported by electric charge pump 130 and be supplied to VCO140 via low-pass loop filter 117. Voltage controlled oscillator 140 is in response to the output of low pass filter 117.Voltage controlled oscillator 140 is by supply voltage (VDD) power and include the phase inverter 144,146 and 148 of transistor 142 and multiple series coupled.

Electric charge pump 130 has the first supply voltage (VDD) 101 and second source voltage (VSS) 103. Such as, the first supply voltage (VDD) 101 can be positive voltage, and second source voltage (VSS) 103 can be negative supply voltage value or ground connection.First current source 102 coupled to the first supply voltage (VDD) 101 and there is the first drain node (Vp) 108.Second current source 104 has the second drain node (Vn) 110 and coupled to second source voltage (VSS) 103.Electric charge pump 130 also includes voltage tracking circuit 113.Voltage tracking circuit 113 coupled to the first drain node (Vp) 108 and coupled to the second drain node (Vn)110.VT (Vtune) 116 is optionally traced into first by voltage tracking circuit 113 Drain node (Vp) 108 and the second drain node (Vn) 110 are with the voltage at stable drain node 108,110. Electric charge pump 130 includes multiple switch, it include the first switch (S1) 120, second switch (S2) 122, 3rd switch (S3) 124 and the 4th switch (S4) 126.Switch S1-S4120-126 in response to up (on Rise) or down (decline) signal.Such as, first switch (S1) 120 in response to up signal, and Second switch (S2) 122 is in response to down signal.3rd switch (S3) 124 in response to(upb) Input, and the 4th switch (S4) 126 in response to(downb) input.(upb) input with Up signal is contrary, andInput contrary with down signal.Output (the i.e. Vtune of electric charge pump 130 116) it is to provide from the node between the first switch (S1) 120 and second switch (S2) 122.

Charging current path is coupled to or includes the first current source 102 and includes the first current source 102 The first drain node (Vp) 108.Discharge current path is coupled to or includes the second current source 104. Discharge current path includes second drain node (Vn) 110 of the second current source 104.Charge path provides electricity Stream is charged with the capacitor (not shown in figure 1) to the output coupleding to electric charge pump 130.Electric discharge electricity Flow path makes this capacitor (not shown) can carry out release current via discharge path.

The operation of charge path and discharge path is in response to up and down signal.Such as, charge path is worked as Time effectively, for connection, down signal is disconnection to up signal.In this case, the first switch (S1) 120 close, and the 4th switch (S4) 126 also closes.Situation in the first switch (S1) 120 Guan Bi Under, electric current flow to capacitor to be charged from the first current source 102 via the output of electric charge pump 130.At electricity During decline (down) circulation of lotus pump 130, second switch (S2) 122 Guan Bi and the 3rd switch (S3) 124 Guan Bis.In the case of discharge path is activated, the electric charge from this capacitor flows through second switch (S2) 122 and leaked into second source voltage (VSS) 103 by the second current source 104.

In illustrative embodiment, when PLL100 is locked, " unlatching " path and " closedown " path To be alternately turned on during switching.As commentary, " open " path and include the first switch (S1) 120 With the 4th switch (S4) 126." close " path and include second switch (S2) 122 and the 3rd switch (S3) 124。

As commentary, when " unlatching " path is effective, the first switch (S1) 120 Guan Bi.First electricity Stream source 102 provides an electric current, and this electric current flows through this current charging path and the first switch (S1) 120 right The capacitor (not shown) of the output VT (Vtune) 116 coupleding to electric charge pump 130 is charged. When " unlatching " path is effective, " closedown " path becomes invalid and the 3rd switch (S3) 124 disconnection.

As commentary, when " closedown " path is effective, second switch (S2) 122 closes.Second electricity Stream source 104 provides an electric current, and this electric current is from the output VT (Vtune) coupleding to electric charge pump 130 The capacitor (not shown) of 116 flow to second via discharge current path by second switch (S2) 122 Supply voltage (VSS) 103.When " closedown " path is effective, " unlatching " path become invalid and 4th switch (S4) 126 disconnects.

As commentary, when " closedown " path is effective, the 3rd switch (S3) 124 Guan Bi.First electricity Stream source 102 provides an electric current, and this electric current flow to second source voltage (VSS) by the 3rd switch (S3) 124. When " closedown " path is effective, " unlatching " path becomes invalid and the first switch (S1) 120 disconnection.

As commentary, when " unlatching " path is effective, the 4th switch (S4) 126 Guan Bi.Second electricity Stream source 104 provides an electric current, and this electric current switchs (S4) from the first supply voltage (VDD) 101 by the 4th 126 flow to second source voltage (VSS) 103.When " unlatching " path is effective, " closedown " path becomes Disconnect for invalid and second switch (S2) 122.

When PLL100 is locked, if the transistor in electric charge pump 130 does not has enough headroom, then have Switching between " unlatching " path and " closedown " path of effect can change the first leakage of the first current source 102 Voltage on node (Vp) 108, and second drain node (Vn) 110 of the second current source 104 can be changed On voltage.Voltage tracking circuit 113 is in response to VT signal (Vtune) 116 and by the first electricity The voltage stabilization of first drain node (Vp) 108 in stream source 102 is being equivalent to or based on VT (Vtune) At the voltage of 116, and the voltage stabilization of second drain node (Vn) 110 of the second current source 104 is existed It is equivalent to or at voltage based on VT (Vtune) 116.Stably can pass through when VT is high Hereinafter operation occurs: apply tuning to the nmos pass transistor (not shown) of the first voltage tracking circuit Voltage (Vtune) 116, draws the electric current from this nmos pass transistor, and by this NMOS crystal The drain voltage of pipe is applied to the PMOS transistor (not shown) of the first voltage tracking circuit.Across NMOS The pressure drop (Vdrop) of transistor will be equivalent to (or being similar to) voltage gain across PMOS transistor (Vgain), thus the voltage of the first drain node 108 of the first current source 102 will be equal to (or almost etc. In) VT (Vtune) 116 deducts the pressure drop across nmos pass transistor plus across PMOS transistor Voltage gain (that is, Vtune Vdrop+Vgain=Vtune).Alternatively, stably can be at tuning electricity Pressure is for occurring by following operation time low: to the PMOS transistor (not shown) of the second voltage tracking circuit Apply VT (Vtune) 116, obtain electric current from this PMOS transistor, and by this PMOS The drain voltage of transistor is applied to the nmos pass transistor (not shown) of the second voltage tracking circuit.Across The voltage gain of PMOS transistor will be equivalent to (or being similar to) pressure drop across nmos pass transistor, from And the second drain node 110 of the second current source 104 will be equal to (or being no better than) VT (Vtune) 116 deduct pressure drop (that is, the Vtune across nmos pass transistor plus the voltage gain across PMOS transistor + Vgain Vdrop=Vtune).Result is, the switching phase between " unlatching " and " closedown " path Between, the voltage change at the first drain node (Vp) 108 and the voltage at the second drain node (Vn) 110 change Change can substantially reduce at the voltage level in response to VT signal (Vtune) 116 due to stable.

In response to VT signal (Vtune) 116, the first tracking circuit of voltage tracking circuit 113 is (not Illustrate) optionally change to stablize the first current source 102 the first drain node (Vp) 108 voltage electricity Flat.Similarly, in response to VT signal (Vtune) 116, the second of voltage tracking circuit 113 with Track circuit (not shown) is optionally modified to stablize second drain node (Vn) of the second current source 104 The voltage level of 110.

It will be appreciated that stablize voltage level and second drain node of the first drain node (Vp) 108 during switching (Vn) voltage level of 110 can reduce the electricity on the output VT (Vtune) 116 of electric charge pump 130 Lotus is shared and injection effect.During switching, minimizing electric charge is shared and injection effect can reduce mismatch current.That is, Rise the charge volume of capacitor that is associated with VT (Vtune) 116 during circulation can equal under The discharge capacity of the capacitor being associated with VT (Vtune) 116 during fall circulation, this can reduce noise Or the voltage range allowing PLL output 100 increases.

With reference to Fig. 2, it is shown that the specific embodiment of circuit 200.Circuit 200 includes the phaselocked loop 100 of Fig. 1 The specific implementation of electric charge pump 130.Circuit 200 has the first supply voltage (VDD) 201 and the second electricity Source voltage (VSS) 203.First supply voltage (VDD) 201 supply has the first drain node (Vp) First current source 202 of 208.Second current source 204 coupled to second source voltage (VSS) 203 and It coupled to the second drain node (Vn) 210.Charging current path 205 coupled to the first current source 202 and It coupled to representative capacitor 206.Charging current path 205 includes the first leaking joint of the first current source 202 Point (Vp) 208.Circuit 200 includes that discharge current path 207, discharge current path 207 coupled to Two current sources 204 and coupled to capacitor 206.Discharge current path 207 includes the second current source 204 The second drain node (Vn) 210.In a specific embodiment, charging current path 205 includes that first is brilliant Body pipe (T1) 220, and discharge current path 207 includes transistor seconds (T2) 222.The first transistor (T1) 220 and transistor seconds (T2) 222 can have substantially opposite characteristic.Such as, first crystal Pipe (T1) 220 can be PMOS transistor, and transistor seconds (T2) 222 can be NMOS Transistor, as shown in the figure.Alternatively, in complementary circuit, the first transistor (T1) 220 can be Nmos pass transistor, and transistor seconds (T2) 222 can be PMOS transistor.

Circuit 200 includes that the first tracking circuit 212 and second follows the tracks of circuit 214.First follows the tracks of circuit 212 It coupled to first drain node (Vp) 208 of the first current source 202.Second follows the tracks of circuit 214 coupled to the Second drain node (Vn) 210 of two current sources 204.First follows the tracks of circuit 212 in response to VT (Vtune) 216 and nmos pass transistor (Tn1) 234 and nmos pass transistor (Tn2) can be included 238.Nmos pass transistor (Tn1) 234 receives VT (Vtune) 216 at its grid.First Follow the tracks of circuit 212 and also include third transistor (T3) 230.Internal node (vcp) 242 is positioned at NMOS Between transistor (Tn1) 234 and nmos pass transistor (Tn2) 238.Internal node (vcp) 242 It coupled to the grid of third transistor (T3) 230.Third transistor (T3) 230 coupled to the first source 202 The first drain node (Vp) 208.Third transistor (T3) 230 is also coupled to transistor (T5) 224, Transistor (T5) 224 coupled to second source voltage (VSS) 203.First input following the tracks of circuit 212 (that is, to the input of transistor (Tn2) 238) via transistor (T7) 250 in response to the first power supply Voltage (VDD) 201.

Second follows the tracks of circuit 214 includes PMOS transistor (Tp1) 240 and PMOS transistor (Tp2) 236.The grid of transistor (Tp2) 236 receives VT (Vtune) 216.Second follows the tracks of circuit 214 In response to including coupleding to the PMOS transistor 246 of the first supply voltage (VDD) 201 and coupleding to the The Circuits System of the nmos pass transistor 248 of two supply voltages (VSS) 203, as commentary.Crystal The grid of pipe 248 coupled to the output of transistor (T7) 250.Therefore, transistor 248 receiving crystal pipe (T7) output of 250, and the nmos pass transistor (Tn2) 238 of the first voltage tracking circuit 212 The also output of receiving crystal pipe (T7) 250.Second follows the tracks of circuit 214 also includes the 4th transistor (T4) 232.4th transistor (T4) 232 coupled to second drain node (Vn) 210 of the second current source 204. 4th transistor (T4) 232 is also coupled to transistor (T6) 226, and transistor (T6) 226 coupled to First supply voltage (VDD) 201.

First follows the tracks of circuit 212 coupled to the of the first current source 202 by third transistor (T3) 230 One drain node (Vp) 208.Third transistor (T3) 230 and the first transistor (T1) 220 have base This similar characteristic.Such as, the first transistor (T1) 220 and third transistor (T3) 230 can be all PMOS transistor.Second follows the tracks of circuit 214 coupled to the second electric current by the 4th transistor (T4) 232 Second drain node (Vn) 210 in source 204.4th transistor (T4) 232 and transistor seconds (T2) 222 characteristics with basic simlarity.Such as, transistor seconds (T2) 222 and the 4th transistor (T4) 232 can be all nmos pass transistor.During operation, first and second follow the tracks of circuit 212,214 based on VT (Vtune) 216 equalizes the first current source 202 and corresponding drain node of the second current source 204 208 and 210.When VT (Vtune) 216 is close to the half of supply voltage, tracking circuit 212, 214 close or provide little electric current.Such as, it is about the first electricity when VT (Vtune) 216 During the half of source voltage (VDD) 201, (such as, when VSS is ground connection between VDD and VSS), Tracking circuit 212 and 214 does not affect the first or second drain node 208,210 and (such as, is not supplied with electricity Stream or voltage).

When VT (Vtune) 216 approaches the first supply voltage (VDD) 201, first follows the tracks of electricity VT (Vtune) 216 is traced into first drain node (Vp) of the first current source 202 by road 212 208 to stablize the voltage level of the first drain node (Vp) 208.Therefore, the first tracking circuit 212 is joined It is set to optionally change to stablize the first drain node (Vp) in response to VT signal (Vtune) 216 The voltage level of 208.Similarly, second source voltage (VSS) is approached when VT (Vtune) 216 When 203, second follows the tracks of circuit 214 traces into the second current source 204 by VT (Vtune) 216 Second drain node (Vn) 210 is to be modified, thus stablizes the voltage electricity of the second drain node (Vn) 210 Flat.Therefore, the second tracking circuit 214 in response to VT (Vtune) 216 and is optionally changed To stablize the voltage level of second drain node (Vn) 210 of the second current source 204.At a specific embodiment In, the voltage level of first drain node (Vp) 208 of the first current source 202 is by making third transistor (T3) 230 are maintained in saturated working area and stablize.Such as, during the charging cycle of capacitor 206, along with VT (Vtune) 216 increases, and first follows the tracks of circuit 212 can put third transistor (T3) 230 In saturation region, to stablize the voltage level of first drain node (Vp) 208 of the first current source 202.? During discharge cycles, when capacitor 206 is discharged by discharge current path, second follows the tracks of circuit 214 The of the second current source 204 can be stablized by being placed in saturated working area by the 4th transistor (T4) 232 Two drain node (Vn) 210.

Therefore, circuit 200 can include electric charge pump or can be the part of electric charge pump, and this electric charge pump is joined It is set to generate VT (Vtune) 216.Electric charge pump can both have the charged electrical coupleding to capacitor 206 Flow path 205 has again the discharge current path 207 coupleding to capacitor 206.Circuit 200 includes first With the second voltage tracking circuit 212,214, they select in response to VT signal (Vtune) 216 Change to selecting property with the voltage level of stably corresponding drain node 208,210.

During operation, by stablizing the first drain node (Vp) 208 and second electricity of the first current source 202 Second drain node (Vn) 210 in stream source 204, the first transistor (T1) 220 and transistor seconds (T2) 222 are maintained in saturated working area.When the first transistor (T1) 220 and transistor seconds (T2) 222 When being maintained in saturated working area, electric current can more easily flow through transistor, and this can equalize when " unlatching " Magnitude of current when path is effective, capacitor (206) being charged with when " closedown " path is effective from electricity The magnitude of current that container (206) discharges.

In illustrative embodiment, first follows the tracks of circuit 212 operation is used for following the tracks of VT signal (Vtune) 216 to stablize first drain node (Vp) 208 of the first current source 202.Such as, if adjusted Humorous voltage (Vtune) 216 is high, then the PMOS part of electric charge pump (includes the first transistor (T1) 220, the 5th transistor (T5) and the first drain node (Vp) 208) can have less headroom.? In this sight, first follows the tracks of circuit 212 stablizes the voltage in the first drain node (Vp) 208.

Such as, high tuning voltage (Vtune) 216 will be applied in the NMOS of the first tracking circuit 212 The grid of transistor (Tn1) 234 is to activate nmos pass transistor (Tn1) 234.Owing to showing as in Fig. 2 The drain-gate coupling gone out, nmos pass transistor (T7) 250 will be from the first supply voltage (VDD) 201 Draw electric current to second source voltage (VSS) 203.Nmos pass transistor (Tn2) 238 is to from NMOS The electric current of transistor (T7) 250 carries out mirror image, thus will draw from the image current of node (vcp) 242 Get second source voltage (VSS) 203.This makes the voltage level of node (vcp) 242 substantially adjust The value of humorous voltage (Vtune) 216 deducts the threshold value pressure drop being associated with nmos pass transistor (Tn1) 234. Similarly, the first drain node (Vp) 208 is made by the image current of nmos pass transistor (Tn2) 238 The voltage level values of the voltage level substantially node (vcp) 242 at place adds and third transistor (T3) The voltage gain that the threshold voltage of 230 is associated, third transistor (T3) 230 is PMOS transistor. Voltage-tracing VT (Vtune) 216 at first drain node (Vp) 208 and therefore tracking first Voltage at the drain electrode of transistor (T1) 220.By the voltage level by the first drain node (Vp) 208 The stable value at about VT (Vtune) 216, the first transistor (T1) 220 and third transistor (T3) will be in saturated working area both 230.Result is, on " unlatching " path and " closedown " road Between footpath during switching, mismatch current will reduce, this is because the first transistor (T1) 220 and the trimorphism Both body pipes (T3) 230 are saturated by the degree of depth.

In a specific embodiment, if VT (Vtune) 216 is high, then the NMOS of electric charge pump Partly (include transistor seconds (T2) the 222, the 6th transistor (T6) 226 and the second drain node (Vn) 210) more headroom will be had to be used for operating.This so to eliminate at VT (Vtune) 216 be high electricity The voltage of the second drain node (Vn) 210 is followed the tracks of with between " unlatching " path and " closedown " path during pressure The needs of mismatch current amount are reduced during switching.Such as, the PMOS of the second tracking circuit 214 is put on The high tuning voltage (Vtune) 216 of the grid of transistor (Tp2) 236 will make PMOS transistor (Tp2) 236 cut-offs.Therefore, the second nmos pass transistor (T4) following the tracks of circuit 214 can be used as switch, and Can not exist or exist little due to second follow the tracks of circuit 214 and cause to the second drain node (Vn) The impact of 210.

In an illustrative embodiment, second follows the tracks of circuit 214 operation for by VT signal (Vtune) 216 the second drain node (Vn) 210 tracing into the second current source 204.Such as, if adjusted Humorous voltage (Vtune) 216 is low, then the NMOS part of electric charge pump (includes transistor seconds (T2) 222, the 6th transistor (T6) 226 and the second drain node (Vn) 210) will have less headroom. In this sight, second follows the tracks of circuit 214 stablizes the voltage in the second drain node (Vn) 210.

Such as, low VT (Vtune) 216 will be applied in the PMOS of the second tracking circuit 214 The grid of transistor (Tp2) 236 is to activate PMOS transistor (Tp2) 236.Due to such as institute in Fig. 2 Show drain-gate coupling, PMOS transistor 246 source electrode from nmos pass transistor 248 is obtained to The electric current of the first supply voltage (VDD) 201.240 pairs of PMOS crystal of PMOS transistor (Tp1) The electric current of pipe 246 carries out mirror image, thus acquires the first supply voltage (VDD) from node (vcn) 244 The image current of 201.This makes the voltage level substantially VT (Vtune) of node (vcn) 244 The value of 216 is plus the voltage gain being associated with the threshold voltage of PMOS transistor (Tp2) 236. Similarly, the second drain node (Vn) 210 is made by the image current of PMOS transistor (Tp1) 240 The voltage level values of the voltage level substantially node (vcn) 244 at place deducts and the 4th transistor (T4) The threshold value pressure drop that 232 are associated, the 4th transistor (T4) 232 is nmos pass transistor.Second leakage Voltage at node (Vn) 210 is followed the tracks of now VT (Vtune) 216 and therefore follows the tracks of second Voltage at the source electrode of transistor (T2) 222.By the voltage by the second drain node (Vn) 210 Level equalization is the value of about VT (Vtune) 216, transistor seconds (T2) 222 and Both four transistors (T4) 232 will be in saturated working area.Result is, in " unlatching " path And during the switching " closed " between path, mismatch current will reduce, this is because transistor seconds (T2) 222 and the 4th is saturated by the degree of depth both transistor (T4) 232.

In a specific embodiment, if VT (Vtune) 216 is low, then the PMOS of electric charge pump Partly (include the first transistor (T1) the 220, the 5th transistor (T5) and the first drain node (Vp) 208) will have more headroom to be used for operating.This so eliminate and at VT (Vtune) 216 be The voltage of the first drain node (Vp) 208 is followed the tracks of with in " unlatching " path and " closedown " path during low-voltage Between switching during reduce mismatch current amount needs.Such as, the first tracking circuit 212 it is applied in The low VT (Vtune) 216 of the grid of nmos pass transistor (Tn1) 234 will make NMOS Transistor (Tn1) 234 ends.Therefore, the PMOS transistor (T3) of the first tracking circuit 212 230 can be used as switch, and can not there is or exist little leading due to the first tracking circuit 212 The impact on the first drain node (Vp) 208 caused.

In an illustrative embodiment, when VT (Vtune) 216 is close to the first supply voltage (VDD) 201 half (that is, intermediate value VT) time, follow the tracks of circuit 212,214 close.For this intermediate value VT (Vtune) 216, electric charge pump NMOS part and PMOS part both have more only Empty.In this sight, during the switching between " unlatching " path and " closedown " path, the first electricity Voltage in first drain node (Vp) 208 in stream source 202 and second drain node (Vn) of the second current source 204 Voltage very little for experience is changed by the voltage on 210.Therefore, in this part phase of charge/discharge cycle Between, for following the tracks of circuit 212,214, it is not necessary to stablize the first drain node (Vp) 208 and the second leakage The voltage level of node (Vn) 210.

Such as, intermediate value VT (Vtune) 216 will be applied in the NMOS of the first tracking circuit 212 The grid of transistor (Tn1) 234.Intermediate value VT (Vtune) 216 will make nmos pass transistor (Tn1) 234 cut-offs, and as response, the 3rd PMOS transistor (T3) 230 will act as switch.Intermediate value is adjusted Humorous voltage (Vtune) 216 level also will put on the PMOS transistor (Tp2) of the second tracking circuit 214 The grid of 236.Intermediate value VT (Vtune) 216 will make PMOS transistor (Tp2) 236 end, And as response, the 4th nmos pass transistor (T4) will act as switch.

It will be appreciated that the first tracking circuit 212 can prevent the voltage level of the first drain node (Vp) 208 from " opening Open " path effective time value and " closedown " path of being about VT (Vtune) 216 effective time the Change between the value of two supply voltages (VSS) 203.Will also be appreciated that, second follows the tracks of circuit 214 can prevent The voltage level of the second drain node (Vn) the 210 about VT signal when " closedown " path is effective (Vtune) 216 value and " unlatching " path effective time the first supply voltage (VDD) 201 between change Become.

It will be appreciated that stablize voltage level and second drain node of the first drain node (Vp) 208 during switching (Vn) voltage level of 210 can reduce electric charge pump electric charge share and injection effect.Will also be appreciated that, cutting During changing, minimizing electric charge is shared and is injected and can reduce mismatch current.That is, when " unlatching " path is effective to electricity The magnitude of current that container 206 is charged can be equal to putting capacitor 206 when " closedown " path is effective The magnitude of current of electricity, this can reduce the noise in PLL output.

Will also be appreciated that, the voltage level stablizing the first drain node (Vp) 208 can make the first transistor (T1) 220 and third transistor (T3) 230 in effective " unlatching " path and effectively " closedown " path it Between switching during be maintained in the saturated working area of the degree of depth.Additionally, it will be appreciated that stablize the second drain node (Vn) The voltage level of 210 can make transistor seconds (T2) 222 and the 4th transistor (T4) 232 effectively " open " and be maintained in the saturated working area of the degree of depth during switching between path and effective " closedown " path.

With reference to Fig. 3, it is shown that the specific embodiment of the method 300 of operation circuit.Such as, circuit can be The circuit 200 of PLL100 or Fig. 2 of Fig. 1.Method 300 is included in 310 at the first power supply of electric charge pump The first drain node at follow the tracks of VT signal.Such as, in fig. 2, the first voltage tracking circuit 212 VT signal can be followed the tracks of at first drain node (Vp) 208 of the first current source 202 of electric charge pump (Vtune)216.Method 300 further includes at 320 in the second drain node of the second source of electric charge pump Place follows the tracks of VT signal.Such as, in fig. 2, the second voltage tracking circuit 214 can be at electric charge pump VT signal (Vtune) 216 is followed the tracks of at second drain node (Vn) 210 of the second current source 204.

Method 300 further includes at 330 voltages stablizing the first drain node in response to VT signal And stablize the voltage of the second drain node.First drain node and the second drain node can be by making the first and second crystalline substances Body pipe is maintained in saturated working area to be stablized.Such as, in fig. 2, in response to VT signal (Vtune) The change of 216, the first voltage tracking circuit 212 can keep saturated by making third transistor (T3) 230 Stablize the first drain node (Vp) 208, and the second voltage tracking circuit 214 can be by making the 4th crystal Pipe (T4) 232 keeps saturated and stablizes secondary nodal point (Vn) 210.

Method 300 further includes at 340 and determines that whether VT signal is close to the one of power supply voltage signal Half.When VT signal is close to the half of power supply voltage signal, 350, do not follow the tracks of VT letter Number.Such as, in fig. 2, it is supply voltage (VDD) 201 when VT signal (Vtune) 216 Half or between the first supply voltage (VDD) 201 and second source voltage (VSS) 203 in During point, then the first and second tracking circuit 212,214 do not provide electric current, or respectively to first and second Drain node 208,210 provides little electric current.

When VT signal keeps off the half of power supply voltage signal, method 300 be back to 310 and Continue to follow the tracks of VT signal.Such as, in fig. 2, do not connect when VT signal (Vtune) 216 The half of nearly supply voltage (VDD) 201 or not at the first supply voltage (VDD) 201 and second source During midpoint between voltage (VSS) 203, then first or second follow the tracks of circuit 212,214 respectively to first Electric current is provided with the second drain node 208,210.

With reference to Fig. 4, depict the block diagram by it usually of the specific illustrative embodiment of Wireless Telecom Equipment It is denoted as 400.Equipment 400 includes the processor coupleding to memorizer 432, such as digital signal processor (DSP)410。

Fig. 4 also show the display controller 426 being coupled to processor 410 and display 428.Compile Code device/decoder (CODEC) 434 is also coupled to processor 410.Speaker 436 and microphone 438 can It is coupled to CODEC434.Fig. 4 also indicate wireless controller 440 can be coupled to processor 410 and Wireless antenna 442.In a specific embodiment, be arranged in wireless controller 440 and wireless antenna 442 it Between radio frequency (RF) interface 460 include the electricity with voltage tracking circuit that coupled to voltage controlled oscillator 466 Lotus pump 464.In an illustrative embodiment, the electric charge pump 464 with voltage tracking circuit can include Fig. 1 Electric charge pump 130 and voltage tracking circuit 113, or first voltage tracking circuit 212, second of Fig. 2 Voltage tracking circuit 214 and/or other assemblies one or more of circuit 200.With voltage tracking circuit Electric charge pump 464 can apply VT to voltage controlled oscillator 466, as with reference to the VT signal of Fig. 1 Described by the VT signal 216 of 116 and Fig. 2.In a specific embodiment, with voltage-tracing The electric charge pump 464 of circuit can perform the method 300 of Fig. 3.

In a specific embodiment, display 428 is coupled to show control via HSSI High-Speed Serial Interface 470 Device 426.HSSI High-Speed Serial Interface 470 includes the electric charge pump 474 with voltage tracking circuit and VCO Device (VCO) 476.In an illustrative embodiment, the electric charge pump 476 with voltage tracking circuit can wrap Include electric charge pump 130 and the voltage tracking circuit 113 of Fig. 1, or first voltage tracking circuit 212 of Fig. 2, Second voltage tracking circuit 214 and/or other assemblies one or more of circuit 200.With voltage-tracing The electric charge pump 474 of circuit can apply VT to voltage controlled oscillator 476, such as the VT with reference to Fig. 1 Described by the VT signal 216 of signal 116 and Fig. 2.In a specific embodiment, with voltage The electric charge pump 474 following the tracks of circuit can perform the method 300 of Fig. 3.

Memorizer 432 can be the tangible non-transient processor readable storage medium including executable instruction 456 Matter.Instruction 456 can be performed by processor 410.

In a specific embodiment, can be by processor 410, display controller 426, memorizer 432, CODEC 434 and wireless controller 440 be included in system in package or system-on-chip apparatus 422.Special one Determining in embodiment, input equipment 430 and power supply 444 are coupled to system-on-chip apparatus 422.Additionally, In one specific embodiment, as Fig. 4 explains orally, display 428, input equipment 430, speaker 436, Microphone 438, wireless antenna 442 and power supply 444 can be in the outsides of system-on-chip apparatus 422.But, aobvious Show in device 428, input equipment 430, speaker 436, microphone 438, wireless antenna 442 and power supply 444 Each can be coupled to the assembly of system-on-chip apparatus 422, such as interface or controller.Although at a high speed Serial line interface 470 is depicted as providing for the interface of display 428, but in other embodiments, at a high speed Serial line interface 470 can provide other assemblies one or more to system in package or system-on-chip apparatus 422 Interface.

Embodiment described by conjunction with, discloses and includes the electric charge pump with voltage tracking circuit and VCO The circuit of device.This circuit include for follow the tracks of VT and for stablize the first current source drain node and The device of the drain node of the second current source.Such as, it is used for following the tracks of VT and being used for stablizing the first electric current The device of the drain node in source and the drain node of the second current source can include the voltage tracking circuit 113 of Fig. 1, figure First voltage tracking circuit 212 of 2, second voltage tracking circuit 214 of Fig. 2, Fig. 4 with voltage with The electric charge pump 464 of track circuit or one part or one or more for following the tracks of VT and stablizing The drain node of one current source and other equipment, circuit or the module of the drain node of the second current source.

Above-disclosed equipment and functional being designed and configured are being stored on computer-readable medium In computer documents (such as, RTL, GDSII, GERBER etc.).Some or all these class files can It is provided to manufacture the manufacture treatment people of device based on this class file.The product that result produces includes partly leading Body wafer, it is then cut into semiconductor element and is packaged into semiconductor chip.These chips subsequently may be used With in a device, such as Set Top Box, music player, video player, amusement unit, navigator, Data cell that communication equipment, personal digital assistant (PDA), position are fixing and computer.Fig. 5 Depict the specific illustrative embodiment of electronic equipment manufacturing process 500.

Physical device information 502 is received at manufacture process 500 (such as at research computer 506). Physical device information 502 can include the design information representing at least one physical property of semiconductor device, should The electric charge pump 130 of semiconductor device such as Fig. 1 or its assembly, the voltage controlled oscillator 140 of Fig. 1 or its assembly, The voltage tracking circuit 113 of Fig. 1, the PLL100 of Fig. 1 or its assembly, the first voltage-tracing electricity of Fig. 2 Road 212 or its assembly, second voltage tracking circuit 214 of Fig. 2 or its assembly, the circuit 200 of Fig. 2 or Its assembly, the electric charge pump 464 with voltage tracking circuit of Fig. 4 or its assembly, the voltage controlled oscillator of Fig. 4 466 or its assembly or its any combination.Such as, physical device information 502 can include grinding via coupleding to Study carefully physical parameter, material behavior and the structural information of user interface 504 input of computer 506.Grind Study carefully computer 506 and include coupleding to the processor 508 of computer-readable medium (such as memorizer 510), The most one or more process cores.Memorizer 510 can store computer-readable instruction, its can be performed so that Physical device information 502 is converted into and follows file format and generate library file 512 by processor 508.

In a specific embodiment, library file 512 includes that at least one includes the number of converted design information According to file.Such as, library file 512 can include the storehouse of semiconductor device, and semiconductor device includes comprising Fig. 1 Electric charge pump 130 or its assembly, the voltage controlled oscillator 140 of Fig. 1 or its assembly, Fig. 1 voltage-tracing electricity Road 113, the PLL100 of Fig. 1 or its assembly, first voltage tracking circuit 212 of Fig. 2 or its assembly, Second voltage tracking circuit 214 of Fig. 2 or its assembly, the circuit 200 of Fig. 2 or its assembly, the band of Fig. 4 Have the electric charge pump 464 of voltage tracking circuit or its assembly, the voltage controlled oscillator 466 of Fig. 4 or its assembly or Its any combination of device, this storehouse is provided to be combined with electric design automation (EDA) instrument 520.

Library file 512 can be collaborative with eda tool 520 at 514 use that design a calculating machine, and design calculates Machine 514 includes the processor 516 coupleding to memorizer 518, the most one or more process cores.EDA work Tool 520 can be stored at memorizer 518 as processor executable, so that designing a calculating machine 514 User can the electric charge pump 130 that include Fig. 1 of design library file 512 or its assembly, the VCO of Fig. 1 Device 140 or its assembly, the voltage tracking circuit 113 of Fig. 1, the PLL100 of Fig. 1 or its assembly, Fig. 2 The first voltage tracking circuit 212 or its assembly, second voltage tracking circuit 214 of Fig. 2 or its assembly, The circuit 200 of Fig. 2 or its assembly, the electric charge pump 464 with voltage tracking circuit of Fig. 4 or its assembly, The voltage controlled oscillator 466 of Fig. 4 or its assembly or its any combination of circuit.Such as, 514 are designed a calculating machine User can via coupled to design a calculating machine 514 user interface 524 carry out input circuit design information 522. Circuit-design information 522 can include the design information representing at least one physical property of semiconductor device, should The electric charge pump 130 of semiconductor device such as Fig. 1 or its assembly, the voltage controlled oscillator 140 of Fig. 1 or its assembly, The voltage tracking circuit 113 of Fig. 1, the PLL100 of Fig. 1 or its assembly, the first voltage-tracing electricity of Fig. 2 Road 212 or its assembly, second voltage tracking circuit 214 of Fig. 2 or its assembly, the circuit 200 of Fig. 2 or Its assembly, the electric charge pump 464 with voltage tracking circuit of Fig. 4 or its assembly, the voltage controlled oscillator of Fig. 4 466 or its assembly or its any combination.In order to explain orally, circuit design property can include the mark of particular electrical circuit Know and with the relation of other elements in circuit design, location information, characteristic size information, interconnection information, Or represent other information of the physical property of semiconductor device.

Design a calculating machine and 514 can be configured to conversion designs information (including circuit-design information 522) to abide by Follow file format.In order to explain orally, this document formats and can include representing about circuit layout with hierarchical format Data base's binary file format of plane geometric shape, text mark and other information, such as figure figurate number According to system (GDSII) file format.Design a calculating machine and 514 can be configured to generate and include converted setting The data file of meter information, such as includes describing the electric charge pump 130 of Fig. 1 or its assembly, the voltage-controlled of Fig. 1 shakes Swing device 140 or its assembly, the voltage tracking circuit 113 of Fig. 1, the PLL100 of Fig. 1 or its assembly, figure First voltage tracking circuit 212 of 2 or its assembly, second voltage tracking circuit 214 of Fig. 2 or its assembly, The circuit 200 of Fig. 2 or its assembly, the electric charge pump 464 with voltage tracking circuit of Fig. 4 or its assembly, The voltage controlled oscillator 466 of Fig. 4 or its assembly or its any combination of information and also have other circuit or letter The GDSII file 526 of breath.In order to explain orally, data file can include corresponding with SOC(system on a chip) (SOC) Information, this SOC include the electric charge pump 130 of Fig. 1 or its assembly, the voltage controlled oscillator 140 of Fig. 1 or its Assembly, the voltage tracking circuit 113 of Fig. 1, the PLL100 of Fig. 1 or its assembly, first voltage of Fig. 2 Follow the tracks of circuit 212 or its assembly, second voltage tracking circuit 214 of Fig. 2 or its assembly, the circuit of Fig. 2 200 or its assembly, the electric charge pump 464 with voltage tracking circuit of Fig. 4 or its assembly, Fig. 4 voltage-controlled Agitator 466 or its assembly or its any combination, and also in this SOC, include the electronics electricity added Road and assembly.

GDSII file 526 can be received with according to the warp in GDSII file 526 at manufacture process 528 Transitional information manufacture the electric charge pump 130 of Fig. 1 or its assembly, the voltage controlled oscillator 140 of Fig. 1 or its assembly, The voltage tracking circuit 113 of Fig. 1, the PLL100 of Fig. 1 or its assembly, the first voltage-tracing electricity of Fig. 2 Road 212 or its assembly, second voltage tracking circuit 214 of Fig. 2 or its assembly, the circuit 200 of Fig. 2 or Its assembly, the electric charge pump 464 with voltage tracking circuit of Fig. 4 or its assembly, the voltage controlled oscillator of Fig. 4 466 or its assembly or its any combination.Such as, equipment Manufacture Process can include GDSII file 526 It is supplied to mask manufacturer 530 to create one or more masks, such as covering associated with photoetching process Mould, it is explained as representative mask 532.Mask 532 can be used for generating one during manufacture process Or multiple wafer 534, wafer 534 can be tested and be divided into tube core, such as representative tube core 536.Pipe Core 536 includes the circuit comprising device, and this device includes the electric charge pump 130 of Fig. 1 or its assembly, Fig. 1 Voltage controlled oscillator 140 or its assembly, the voltage tracking circuit 113 of Fig. 1, the PLL100 of Fig. 1 or its group Part, first voltage tracking circuit 212 of Fig. 2 or its assembly, second voltage tracking circuit 214 of Fig. 2 or Its assembly, the circuit 200 of Fig. 2 or its assembly, the electric charge pump 464 with voltage tracking circuit of Fig. 4 or Its assembly, the voltage controlled oscillator 466 of Fig. 4 or its assembly or its any combination.

Tube core 536 is provided to encapsulation process 538, and wherein tube core 536 is included into representative encapsulation 540 In.Such as, encapsulation 640 can include singulated dies 536 or multiple tube core, such as system in package (SiP) Arrange.Encapsulation 540 can be configured to follow one or more standard or specification, such as electronic device engineering connection Close committee (JEDEC) standard.

Information about encapsulation 540 can such as be distributed to respectively via the Component Gallery being stored at computer 546 Product designer.Computer 546 can include the processor 548 coupleding to memorizer 550, such as one or Multiple process cores.Printed circuit board (PCB) (PCB) instrument can be stored in storage as processor executable Device 550 is sentenced and is processed the PCB design information received from the user of computer 546 via user interface 544 542.PCB design information 542 can include encapsulating semiconductor device physical positioning information on circuit boards, This encapsulation semiconductor device is corresponding to including electric charge pump 130 or its assembly, the voltage controlled oscillator of Fig. 1 of Fig. 1 140 or its assembly, the voltage tracking circuit 113 of Fig. 1, the PLL100 of Fig. 1 or its assembly, Fig. 2 First voltage tracking circuit 212 or its assembly, second voltage tracking circuit 214 of Fig. 2 or its assembly, figure The circuit 200 of 2 or its assembly, the electric charge pump 464 with voltage tracking circuit of Fig. 4 or its assembly, figure The voltage controlled oscillator 466 of 4 or its assembly or its any combination of encapsulation 540.

Computer 546 can be configured to conversion PCB design information 542 to generate data file, such as carries Have include encapsulating semiconductor device physical positioning information on circuit boards and electrical connection (such as trace and Through hole) the GERBER file 552 of data of layout, wherein this encapsulation semiconductor device is corresponding to including The electric charge pump 130 of Fig. 1 or its assembly, the voltage controlled oscillator 140 of Fig. 1 or its assembly, Fig. 1 voltage with Track circuit 113, the PLL100 of Fig. 1 or its assembly, first voltage tracking circuit 212 of Fig. 2 or its group Part, second voltage tracking circuit 214 of Fig. 2 or its assembly, the circuit 200 of Fig. 2 or its assembly, Fig. 4 The electric charge pump 464 with voltage tracking circuit or its assembly, the voltage controlled oscillator 466 of Fig. 4 or its assembly, Or its any combination of encapsulation 540.In other embodiments, converted PCB design information generate Data file can have the form beyond GERBER form.

GERBER file 552 can be received and used to create PCB at plate assembling process 554, The representative PCB556 such as manufactured according to the design information of storage in GERBER file 552.Example As, GERBER file 552 can be uploaded to one or more machine to perform each of PCB production process Individual step.PCB556 can be filled with electronic building brick (including encapsulating 540) to form representative printed circuit Assembly (PCA) 658.

PCA558 can be received at manufacture course of products 560, and be integrated into one or more electronics and set In Bei, such as the first representative electronic device 562 and the second representative electronic device 564.As illustrative Indefiniteness example, first representative electronic device the 562, second representative electronic device 564 or this two Person is selected from including the group of the following: be wherein integrated with the electric charge pump 130 of Fig. 1 or its assembly, Fig. 1 Voltage controlled oscillator 140 or its assembly, the voltage tracking circuit 113 of Fig. 1, the PLL100 of Fig. 1 or its group Part, first voltage tracking circuit 212 of Fig. 2 or its assembly, second voltage tracking circuit 214 of Fig. 2 or Its assembly, the circuit 200 of Fig. 2 or its assembly, the electric charge pump 464 with voltage tracking circuit of Fig. 4 or Its assembly, the voltage controlled oscillator 466 of Fig. 4 or its assembly or its any combination of Set Top Box, music Device, video player, amusement unit, navigator, communication equipment, personal digital assistant (PDA), Data cell that position is fixing and computer.The non-limiting example explained orally as another, electronic equipment One or more in 562 and 564 can be remote unit (such as mobile phone, hand-held personal communication System (PCS) unit), portable data units (such as personal digital assistant, enable global positioning system The system equipment of (GPS), navigator), the fixing data cell (such as meter reading equipment) in position, Or store or retrieve data or any other equipment of computer instruction or its any combination.Although Fig. 5 solution Say the remote unit of the religious doctrine according to the disclosure, but the disclosure has been not limited to these unit explained orally.These public affairs The embodiment opened can be used in the active integrated circuit system including having memorizer and on-chip circuit system suitably In any equipment of system.

Electric charge pump 130 or its assembly, the voltage controlled oscillator 140 of Fig. 1 or its assembly, Fig. 1 including Fig. 1 Voltage tracking circuit 113, the PLL100 of Fig. 1 or its assembly, first voltage tracking circuit 212 of Fig. 2 Or second voltage tracking circuit 214 of its assembly, Fig. 2 or its assembly, the circuit 200 of Fig. 2 or its assembly, The electric charge pump 464 with voltage tracking circuit of Fig. 4 or its assembly, the voltage controlled oscillator 466 of Fig. 4 or its Assembly or its any combination of equipment can be manufactured, processed and brought in electronic equipment, such as illustrative Described in process 500.About Fig. 1-4 the disclosed embodiments one or more in terms of can be included At each processing stage, such as it is included in library file 512, GDSII file 526 and GERBER In file 552, and it is stored in the memorizer 510 of research computer 506, designs a calculating machine 514 Memorizer 518, the memorizer 550 of computer 546, in each stage (such as at plate assembling process 554 Place) other computers one or more of using or processor (not shown) memorizer at, and also quilt Bring in other physical embodiments one or more, such as mask 532, tube core 536, encapsulation 540, In PCA558, other products (such as prototype circuit or equipment (not shown)) or its any combination. Although depict each the representative production phase being designed into final products from physical device, but real at other Execute and example can use the less stage maybe can include additional phase.Similarly, process 500 can be by single entity Or performed by one or more entities in each stage of execution process 500.

Those skilled in the art will further appreciate that, the various solutions described in conjunction with presently disclosed embodiment The property said box, configuration, module, circuit and algorithm steps can be embodied as electronic hardware, be held by processor The computer software of row or combination of the two.Various illustrative components, frame, configuration, module, circuit, Vague generalization description has been made above with its functional form with step.This type of is functional is implemented as Hardware or processor executable depend on the design constraint specifically applying and being added to total system.Skill Art personnel can realize described functional by different way for every kind of application-specific, but this type of realizes certainly Plan is not to be read as causing a departure from the scope of the present disclosure.

The method described in conjunction with presently disclosed embodiment or each step of algorithm can directly use hardware, by Software module or a combination of both that processor performs realize.Software module can reside in random access memory Device (RAM), flash memory, read only memory (ROM), programmable read only memory (PROM), Erasable type programmable read only memory (EPROM), electrically erasable formula programmable read only memory (EEPROM), Depositor, hard disk, removable dish, compact disk read only memory (CD-ROM) or known in the art The non-transitory storage media of any other form.Exemplary storage medium is coupled to processor so that at this Reason device can be from this read information and to this storage medium write information.Alternatively, storage medium Processor can be integrated into.Processor and storage medium can reside in special IC (ASIC). ASIC can reside in calculating equipment or user terminal.In alternative, processor and storage medium can Reside in calculating equipment or user terminal as discrete assembly.

Before offer description to the disclosed embodiments be in order to make those skilled in the art all can make or Use the disclosed embodiments.Various amendments to these embodiments will be to those skilled in the art It will be apparent that and principle defined herein as can be applied to other embodiments without departing from the disclosure Scope.Therefore, the disclosure is not intended to be limited to embodiments shown herein, but should be awarded The widest possible range consistent with principle as defined by the accompanying claims and novel features.

Claims (19)

1. for a circuit for burning voltage level, including:

Coupleding to the first current source and coupled to the charging current path of capacitor, described charging current path is wrapped Include the first drain node of described first current source；

It coupled to the second current source and coupled to the discharge current path of described capacitor, described discharge current road Footpath includes the second drain node of described second current source；

First follows the tracks of circuit, and it coupled to described first drain node of described first current source；And

Second follows the tracks of circuit, and it coupled to described second drain node of described second current source,

Wherein said first follow the tracks of circuit based on VT, the first source voltage of described first current source, with And the relation between the second source voltage of described second current source optionally changes to stablize described first leakage First voltage level of node, and

Described second follows the tracks of circuit based on described VT, described first source voltage and described second source Relation between voltage optionally changes to stablize the voltage level of described second drain node.

2. circuit as claimed in claim 1, it is characterised in that stablize the first of described first drain node Voltage level includes making transistor be maintained in saturated working area.

3. circuit as claimed in claim 1, it is characterised in that farther include in response to described tuning The controlled oscillator of voltage.

4. circuit as claimed in claim 3, it is characterised in that farther include to be configured to generate institute State the electric charge pump of VT.

5. circuit as claimed in claim 1, it is characterised in that described charging current path is wrapped further Include the first transistor and described discharge current path farther includes transistor seconds, wherein said first crystal Pipe and described transistor seconds have contrary characteristic.

6. circuit as claimed in claim 5, it is characterised in that described first follows the tracks of circuit by the 3rd Transistor coupled to described first drain node of described first current source, wherein said third transistor and described The first transistor has similar characteristic.

7. circuit as claimed in claim 5, it is characterised in that described second follows the tracks of circuit by the 4th Transistor coupled to described second drain node of described second current source, wherein said 4th transistor and described Transistor seconds has similar characteristic.

8. circuit as claimed in claim 1, it is characterised in that farther include wherein to be integrated with described First follows the tracks of circuit and described second follows the tracks of the equipment of circuit, and described equipment is selected from the group including the following: Set Top Box, music player, video player, amusement unit, navigator, communication equipment, individual number Data cell that word assistant (PDA), position are fixing and computer.

9. circuit as claimed in claim 1, it is characterised in that described first follows the tracks of Circuit responce in institute State VT and be substantially equal to the half of the difference between described first source voltage and described second source voltage And close, and described first tracking Circuit responce is not substantially equal to described difference in described VT Half and change to stablize described first voltage level.

10. circuit as claimed in claim 9, it is characterised in that described first follows the tracks of circuit with described VT equalizes the first voltage level of described first drain node, and described second follows the tracks of circuit institute State VT to equalize the second voltage level of described second drain node.

11. circuit as claimed in claim 9, it is characterised in that when described VT is close to described During the half of the first source voltage, described first follows the tracks of circuit and described second follows the tracks of circuit and closes.

12. circuit as claimed in claim 1, it is characterised in that farther include in response to described tune The controlled oscillator of humorous voltage, wherein said charging current path also includes the first transistor and described electric discharge electricity Flow path also includes transistor seconds, and wherein said the first transistor and described transistor seconds have phase Anti-characteristic.

13. circuit as claimed in claim 12, it is characterised in that described first follows the tracks of circuit by the Three transistors coupled to described first drain node of described first current source, and described second follows the tracks of circuit by the Four transistors coupled to described second drain node of described second current source, wherein said third transistor and institute State the first transistor and there is similar characteristic, and described 4th transistor and described transistor seconds have phase As characteristic.

14. circuit as claimed in claim 12, it is characterised in that stablize the institute of described first current source State described second drain node of the first drain node and described second current source include making described the first transistor and Described transistor seconds is maintained in saturated working area.

15. circuit as claimed in claim 1, it is characterised in that fill described in also including wherein being integrated with Electricity current path and the equipment of described discharge current path, described equipment is selected from the group including the following: machine Top box, music player, video player, amusement unit, navigator, communication equipment, individual digital Data cell that assistant (PDA), position are fixing and computer.

16. 1 kinds of methods for burning voltage level, including:

Following the tracks of VT at the first circuit, described first circuit coupled to the of the first power supply of electric charge pump One drain node, wherein described first power supply and capacitor, and described charged electrical are coupled in charging current path Flow path includes the first drain node of described first power supply；

Following the tracks of described VT at second circuit, described second circuit coupled to the second of described electric charge pump Second drain node of power supply, wherein discharge current path is coupled to described second source and described capacitor, and And described discharge current path includes the second drain node of described second source；

Based on described VT, the first source voltage of described first power supply and described second source Relation between two source voltages stablizes the first voltage of described first drain node；And

Come based on the relation between described VT, described first source voltage and described second source voltage Stablize the second voltage of described second drain node.

17. methods as claimed in claim 16, it is characterised in that stablize the of described first drain node One voltage includes that the first transistor making to coupled to described first circuit of described first drain node is maintained at full With in working area, and the second voltage wherein stablizing described second drain node includes making to coupled to described second The transistor seconds of the described second circuit of drain node is maintained in saturation region.

18. methods as claimed in claim 16, it is characterised in that farther include when described tuning electricity Described VT is not followed the tracks of when crimping the half of the most described first source voltage.

19. methods as claimed in claim 16, it is characterised in that described first circuit and described second Circuit is integrated in equipment, and described equipment is selected from including the group of the following: Set Top Box, music player, Video player, amusement unit, navigator, communication equipment, personal digital assistant (PDA), position Fixing data cell and computer.