CN103944539B - Level shifter and high voltage logic circuits - Google Patents
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Abstract
The present invention describes with having the level shifter and high voltage logic circuits implemented by the MOS transistor of low breakdown voltage for the voltage swing of input signal and output signal.In exemplary design, level shifter (102) comprises drive circuit (110) and latch (140).Described drive circuit receives the input signal (V with first voltage rangeinp、Vinn), and the driving signal (V with the second voltage range is provideddrp、Vdrn).Described first voltage range and described second voltage range can contain positive voltage and negative voltage, or the positive voltage of different range.Described latch receives described driving signal, and provides the output signal (V with described second voltage rangeoutp、Voutn).Described drive circuit can produce the control signal (V with full voltage range based on described input signalctrip、Vctrin), and described control signal can be next based on and produce described driving signal.Described level shifter may be used to implement high voltage logic circuits.
Description
Divisional application
Present patent application is filing date on July 22nd, 2010, Application No. 201080032880.0, Yi Jifa
The divisional application of the application for a patent for invention case of bright entitled " level shifter and high voltage logic circuits ".
Claim of priority according to 35U.S.C. § 119
Present application for patent advocates entitled " level shifter control method filed in 22 days July in 2009
(LEVEL-SHIFTER CONTROL METHODOLOGY) " No. 61/227,730 U.S. Provisional Application case
Priority, described application case conveyed to its assignee, and is expressly incorporated herein by reference.
Technical field
The present invention relates generally to electronic installation, and more particularly to level shifter and logic circuit.
Background technology
Level shifter has a digital input signals of first voltage range and offer has and is different from the first voltage for receiving
The circuit of the digital output signal of the second voltage range of scope.Logic circuit is for receiving one or more numeral inputs
Signal, performs specific logical function and provides the electricity of one or more digital output signals described digital input signals
Road.Digital signal one in arbitrary given time has multiple (generally, two) possible logical value.For example,
Digital signal can have the high-voltage level for logic high or for logic low low voltage level (such as,
Zero volt (0V)).
Level shifter or logic circuit can be implemented to obtain by metal-oxide semiconductor (MOS) (MOS) transistor little
Size and low power dissipation.MOS transistor possibly cannot dispose full voltage range, and described full voltage range can contain first
Voltage range and the second voltage range.For example, full voltage range can exceed the breakdown voltage of MOS transistor.
Level shifter and logic may be implemented by needs by having the MOS transistor of the breakdown voltage less than full voltage range
Circuit.
Summary of the invention
Accompanying drawing explanation
Figure 1A and 1B shows two exemplary design of level shifter.
Fig. 2 shows the level shifter that the MOS transistor by operating is implemented with full voltage range.
Fig. 3 and 4 shows the demonstration of the level shifter implemented by the MOS transistor of the voltage range operation to reduce
Property design.
Fig. 5 shows the exemplary design of the level shifter for positive voltage scope.
Fig. 6 shows the exemplary design of high voltage logic circuits.
Fig. 7 shows the exemplary design of radio communication device.
Fig. 8 shows the exemplary design of the process for performing level shift.
Fig. 9 shows the exemplary design of the process for producing signal.
Detailed description of the invention
Word " exemplary " is in this article in order to mean " serving as example, example or explanation ".Described herein as
Arbitrary design of " exemplary " is not necessarily to be construed as more preferred than other design or favourable.
Level shifter and high voltage logic that MOS transistor by having certain breakdown voltage described herein is implemented are electric
Road, described breakdown voltage is likely less than the full voltage range of numeral input and output signal.Level shifter and high voltage are patrolled
Volume circuit can be used for various application, such as, for the interface circuit between digital circuit and analog circuit, for connecting or
Control circuit of roof-cut resistence etc..
Figure 1A shows the block diagram of the exemplary design of level shifter 100.In this exemplary design, level shifter
100 comprise the drive circuit 110 being coupled to latch 140.Drive circuit 110 receives and includes having the first voltage
The differential digital input signal of Vinp and the Vinn signal of scope.Drive circuit 110 provides and includes having the second voltage
The differential digital of Vdrp and the Vdrn signal of scope drives signal, and described second voltage range is different from described first voltage
Scope.Latch 140 receives described Differential Driving signal, and provides the Voutp including having described second voltage range
Differential digital output signal with Voutn signal.Drive circuit 110 and latch 140 can as described below as implement.
Figure 1B shows the block diagram of the exemplary design of level shifter 102.In this exemplary design, level shifter
102 comprise the control signal generator 120 of whole series coupled, latch driver 130 and latch 140.Control letter
Number generator 120 and the part that latch driver 130 is the drive circuit 110 in Figure 1A.
Control signal generator 120 receives and includes that the differential digital with Vinp and the Vinn signal of first voltage range is defeated
Enter signal.Control signal generator 120 provides the differential number including having Vctrlp and the Vctrln signal of full voltage range
Word control signal.Latch driver 130 receives described differential control signal, and offer includes having the second voltage range
Vdrp and Vdrn signal differential digital drive signal.Latch 140 receives described Differential Driving signal, and provides
Differential digital output signal including Voutp and the Voutn signal with the second voltage range.Control signal generator 120
With latch driver 130 can as described below as implement.
In figs. 1 a and 1b, first voltage range can contain the voltage range of Vinp and Vinn signal.Second voltage model
Enclose the voltage range that can contain Voutp and Voutn signal.Full voltage range can contain first voltage range and the second voltage
Both scopes.In exemplary design, first voltage range is the most overlapping with the second voltage range.For example, the first electricity
Pressure scope can contain circuit ground (0V) and arrive positive voltage (Vdd), and the second voltage range can contain 0V to negative electricity
Source voltage (Vss), and full voltage range can contain Vss to Vdd.As another example, first voltage range can contain
0V to first positive voltage (Vdd1), the second voltage range can contain Vdd1 to second positive voltage (Vdd2),
And full voltage range can contain 0V to Vdd2, wherein Vdd2 is more than Vdd1.In another exemplary design, first
Voltage range can the most overlapping second voltage range.
Fig. 2 shows the schematic diagram of the circuit 104 of the MOS transistor enforcement by operating with full voltage range.Circuit 104
Comprise the drive circuit 110a being coupled to latch 140a.Drive circuit 110a comprises two P-channel MOS
(PMOS) transistor 222 and 224, described transistor can provide the Vdrp with the voltage range from Vss to Vhigh
With Vdrn signal, wherein Vhigh can be equal to Vdd or circuit ground (0V).PMOS transistor 222 makes its source electrode
It is coupled to Vhigh so that it is grid receives Vinp signal, and makes its offer Vdrp signal that drains.PMOS transistor 224
Its source electrode is made to be coupled to Vhigh so that it is grid receives Vinn signal, and makes its offer Vdrn signal that drains.
Latch 140a comprises the phase inverter 150 and 160 that pair of cross is coupled.Phase inverter 150 comprises with stacking
N-channel MOS (NMOS) transistor 152 of configuration coupling and PMOS transistor 154.Nmos pass transistor 152
Make its source electrode be coupled to Vss so that it is grid is coupled to the grid of PMOS transistor 154, and make it drain to be coupled to
The drain electrode of PMOS transistor 154.The source electrode of PMOS transistor 154 is coupled to Vhigh.MOS transistor 152 He
The grid of 154 forms the input of phase inverter 150, and it receives Vdrp signal.The drain electrode of MOS transistor 152 and 154
Forming the output of phase inverter 150, it provides Voutp signal.Phase inverter 160 comprises with the NMOS of stack arrangement coupling
Transistor 162 and PMOS transistor 164.Nmos pass transistor 162 makes its source electrode be coupled to Vss so that it is grid coupling
Close the grid of PMOS transistor 164, and make it drain to be coupled to the drain electrode of PMOS transistor 164.PMOS
The source electrode of transistor 164 is coupled to Vhigh.The grid of MOS transistor 162 and 164 forms the input of phase inverter 160,
It receives Vdrn signal.The drain electrode of MOS transistor 162 and 164 forms the output of phase inverter 160, and it provides Voutn
Signal.The output of phase inverter 160 is coupled in the input of phase inverter 150, and phase inverter is coupled in the output of phase inverter 150
The input of 160.
Latch 140a operation is as follows.When Vdrp signal is in logic high (such as, Vhigh), NMOS
Transistor 152 is connected, and PMOS transistor 154 is cut off, and Voutp signal is in logic low (such as, Vss).
Vdrn signal is in logic low, and nmos pass transistor 162 cuts off, and PMOS transistor 164 is connected, and Voutn
Signal is in logic high.On the contrary, when Vdrp signal is in logic low, nmos pass transistor 152 cuts off,
PMOS transistor 154 is connected, and Voutp signal is in logic high.Vdrn signal is in logic high, NMOS
Transistor 162 is connected, and PMOS transistor 164 is cut off, and Voutn signal is in logic low.Phase inverter 150
With 160 as can during steady statue the feedback circuit of logical value storage and operate.Vdrp and Vdrn signal can be by new
Logical value is written in latch 140a.
Drive circuit 110a receives Vinp and Vinn signal, and produces Vdrp and Vdrn signal.When Vinp signal
It is in logic low (such as, Vss) and time Vinn signal is in logic high (such as, Vhigh), PMOS
Transistor 222 is connected, and Vdrp signal is in logic high, and PMOS transistor 224 is cut off, and at Vdrn signal
In logic low.On the contrary, when Vinp signal is in logic high and Vinn signal is in logic low, PMOS
Transistor 222 cuts off, and Vdrp signal is in logic low, and PMOS transistor 224 is connected, and at Vdrn signal
In logic high.Vinp and Vinn signal should be less than or equal to Vhigh-| Vthp |, in order to connects PMOS transistor
222 and 224, wherein Vthp is the threshold voltage of PMOS transistor 222 and 224.Vinp and Vinn signal should be big
In or equal to Vhigh, in order to cut off PMOS transistor 222 and 224.Input voltage range should with output voltage range
Overlap approximates the voltage of the threshold voltage of PMOS transistor 222 and 224.
In exemplary design shown in fig. 2, PMOS transistor 222 and 224 is at the voltage model of Vss to Vhigh
Operate between enclosing, and there is the breakdown voltage more than this voltage range.May need complete with have less than Vss to Vdd
The MOS transistor of the breakdown voltage of voltage range implements PMOS transistor 222 and 224.For example, PMOS
Transistor 222 and 224 can with there is less breakdown voltage and source electrode is coupled to circuit ground rather than the PMOS of Vdd is brilliant
Body pipe is implemented.Vinp and Vinn signal (it can have the voltage range of 0V to Vdd) can cut off this then
A little PMOS transistor, but will not be able to connect PMOS transistor.Or, PMOS transistor 222 and 224 can be by
There is less breakdown voltage and drain electrode is coupled to the nmos pass transistor of circuit ground and is substituted.Vinp and Vinn signal continues
And these nmos pass transistors can be connected, but will not be able to cut off nmos pass transistor.
In one aspect, level shifter can comprise drive circuit, and described drive circuit can receive has the first voltage
The input signal of scope generation have the driving signal of the second voltage range.Described drive circuit can be by with the first electricity
The MOS transistor that pressure scope or the second voltage range (rather than full voltage range) operate is implemented, and hits to avoid exceeding
Wear voltage.
Fig. 3 shows the signal of the level shifter 106 of the MOS transistor enforcement by operating with non-overlapping voltages scope
Figure.Level shifter 106 comprises the drive circuit 110b being coupled to latch 140a, and it is the driver in Figure 1A
Circuit 110 and the exemplary design of latch 140.Latch 140a comprises and couples as described above for described by Fig. 2
Two phase inverters 150 and 160.
In exemplary design shown in figure 3, drive circuit 110b comprises four phase inverters 312,314,316
With 318 and two nmos pass transistors 322 and 324.Phase inverter 312 receives Vinp signal, and exports in first
Between signal Vintp.Phase inverter 314 makes it input and is coupled to circuit ground, and makes it export offer the first control signal
Vctrlp.Phase inverter 314 receives its higher supply voltage from Vintp signal, and receives its relatively low supply from Vdrp signal
Voltage.Nmos pass transistor 322 makes it drain and is coupled to circuit ground so that it is grid receives from phase inverter 314
Vctrlp signal, and make its source electrode provide Vdrp signal.Phase inverter 316 receives Vinn signal, and exports in the middle of second
Signal Vintn.Phase inverter 318 makes it input and is coupled to circuit ground, and makes it export offer the second control signal Vctrln.
Phase inverter 318 receives its higher supply voltage from Vintn signal, and receives its lower supply voltage from Vdrn signal.
Nmos pass transistor 324 makes it drain and is coupled to circuit ground so that it is the Vctrln that grid receives from phase inverter 318 believes
Number, and make its source electrode provide Vdrn signal.
Phase inverter 312,314,316 and 318 can be the part of the control signal generator 120 in Figure 1B.NMOS
Transistor 322 and 324 can be the part of the latch driver 130 in Figure 1B.Phase inverter 312 and 316 is first
Operate between voltage range, and receive the Vdd for higher supply voltage and the circuit ground for lower supply voltage.
Phase inverter 314 and 318 operates between first voltage range or the second voltage range at arbitrary given time.Depend on
The logical value of Vinp signal, phase inverter 314 can operate between first voltage range and phase inverter 318 can be at the second voltage
Operate between scope, or phase inverter 314 can operate between the second voltage range and phase inverter 318 can be at the first voltage model
Operate between enclosing.
Fig. 4 shows the schematic diagram of level shifter 106, the wherein each in phase inverter 312,314,316 and 318
It is to be implemented by a pair MOS transistor.Specifically, phase inverter 312 is by between circuit ground and Vdd
Nmos pass transistor 412 and the PMOS transistor 414 of operation are implemented.Phase inverter 314 is by Vintp signal
And nmos pass transistor 422 and the PMOS transistor 424 of operation are implemented between Vdrp signal.Phase inverter 316 is
Implemented by nmos pass transistor 432 and the PMOS transistor 434 of operation between circuit ground and Vdd.Instead
Phase device 318 is by the nmos pass transistor 442 and PMOS crystal of operation between Vintn signal and Vdrn signal
Pipe 444 is implemented.
Fig. 4 also shows that Vdd=1.8V, Vss=-2V, Vinp signal is in logic high and Vinn signal is in and patrols
Collect low level situation.Level shifter 106 operates as follows.The logic low (0V) of Vinn signal is by phase inverter
The output of 316 is set as 1.8V.PMOS transistor 444 in phase inverter 318 observe the 0V at its grid and its
1.8V at source electrode, PMOS transistor 444 is connected and the output of phase inverter 318 is increased to 1.8V.NMOS is brilliant
Body pipe 324 makes it drain and is coupled to 0V, is connected by the 1.8V at its grid, and provides 0V on Vdrn signal.
In latch 140a, nmos pass transistor 162 is connected and PMOS transistor 164 is by the 0V on Vdrn signal
And cut off.Nmos pass transistor 162 is offer-2V on Voutn signal.In reciprocal side, the logic high of Vinp signal
The output of phase inverter 312 is set as 0V by level (1.8V).Nmos pass transistor 422 in phase inverter 314 is observed
0V at its grid and-2V on the Vdrp signal at its source electrode, nmos pass transistor 422 is connected and by anti-phase
-2V is moved in the output of device 314 to.Vdrp signal is connected owing to the nmos pass transistor 162 in latch 140a and is located
In-2V.The grid of nmos pass transistor 322 and source electrode connected by the nmos pass transistor 422 in phase inverter 314 and
Short circuit.In latch 140a, nmos pass transistor 152 cuts off, and PMOS transistor 154 is by Vdrp signal
On-2V and connect.PMOS transistor 154 provides 0V on Voutp signal.
During steady statue, the MOS transistor in latch 106 observes that the maximum drain of 2V is to source voltage.
During the low level of Vinp signal changes to high level transformation or high level to low level, short due to voltage spikes may be respectively
Nmos pass transistor 422 and 442 in phase inverter 314 and 318 and occur.This due to voltage spikes up to Vdd-Vss,
Or the 3.8V in the example shown in Fig. 4.This due to voltage spikes can alleviate in the following manner: (i) is in phase inverter 314
Nmos pass transistor 322 source electrode and the source electrode of nmos pass transistor 422 between add resistor；And (ii) exists
Resistor is added between source electrode and the source electrode of nmos pass transistor 442 of the nmos pass transistor 324 in phase inverter 318.
Nmos pass transistor 422 and 442 in phase inverter 314 and 318 can be designed to ensure that electricity with suitable size respectively
The appropriate operation of translational shifting device 106.Nmos pass transistor 422 cuts off nmos pass transistor 322, and NMOS crystal
Pipe 442 cuts off nmos pass transistor 324.If the on-state of nmos pass transistor 422 and 442 is too strong, then NMOS
Transistor 322 and 324 may easily pull out from its dissengaged positions (wherein source electrode is entangled in grid).NMOS
The size of transistor 422 and 442 can be chosen so that its on-state will not be too strong, so that nmos pass transistor
322 and 324 can pull out from dissengaged positions relatively easily.
Fig. 5 shows the schematic diagram of level shifter 108, and wherein input and output signal has positive voltage scope.Level moves
Position device 108 receives the differential input letter of Vinp and the Vinn signal including having the first voltage range of 0V to Vdd1
Number.Level shifter 108 provides Voutp and the Voutn signal including having second voltage range of Vdd1 to Vdd2
Differential output signal, wherein Vdd2 > Vdd1.
Level shifter 108 comprises the drive circuit 110c being coupled to latch 140c, and it is the driver in Figure 1A
Another exemplary design of circuit 110 and latch 140.Drive circuit 110c comprise four phase inverters 512,514,
516 and 518 and two PMOS transistor 522 and 524.Phase inverter 512 receives Vinp signal and exports in first
Between signal Vintp.Phase inverter 514 makes it input and is coupled to Vdd1, and makes it export offer the first control signal Vctrlp.
Phase inverter 514 receives its higher supply voltage from Vdrp signal, and receives its lower supply voltage from Vintp signal.
PMOS transistor 522 makes it drain and is coupled to Vdd1 so that it is grid receives the Vctrlp signal from phase inverter 514,
And make its source electrode provide Vdrp signal.Phase inverter 516 receives Vinn signal, and exports the second M signal Vintn.
Phase inverter 518 makes it input and is coupled to Vdd1, and makes it export offer the second control signal Vctrln.Phase inverter 518
Receive its higher supply voltage from Vdrn signal, and receive its lower supply voltage from Vintn signal.PMOS transistor
524 make it drain is coupled to Vdd1, makes its grid receive from the Vctrln signal of phase inverter 518, and makes its source electrode
Vdrn signal is provided.
Phase inverter 512,514,516 and 518 can be the part of the control signal generator 120 in Figure 1B.PMOS
Transistor 522 and 524 can be the part of the latch driver 130 in Figure 1B.Phase inverter 512 and 516 is first
Operate between voltage range, and receive the Vdd for higher supply voltage and the 0V for lower supply voltage.Anti-phase
Device 514 and 518 operates between first voltage range or the second voltage range at arbitrary given time.Depend on Vinp
The logical value of signal, phase inverter 514 can operate between first voltage range, and phase inverter 518 can be at the second voltage model
Operate between enclosing, or phase inverter 514 can operate between the second voltage range, and phase inverter 518 can be at the first voltage model
Operate between enclosing.
Latch 140c comprises two phase inverters 550 and 560, and it passes through nmos pass transistor 552 and 562 and PMOS
Transistor 554 and 564 is implemented, and nmos pass transistor 552 and 562 and PMOS transistor 554 and 564 are with class
The nmos pass transistor 152 being similar in Fig. 2 and 162 and the mode of PMOS transistor 154 and 164 (except it supplies
Electrical connection is outer) coupling.PMOS transistor 554 and 564 makes its source electrode be coupled to Vdd2, and nmos pass transistor 552
Its source electrode is made to be coupled to Vdd1 with 562.Drive circuit 110c and latch 140c with the drive circuit in Fig. 3
Mode complementary for 110b and latch 140a operates.
Level shifter described herein may be used to implement high voltage logic circuits.High voltage logic circuits is for disposing
There is numeral input and/or the output of the voltage range bigger than the breakdown voltage of the MOS transistor in order to implement logic circuit
The logic circuit of signal.
Fig. 6 shows the schematic diagram of the exemplary design of high voltage logic circuits 600, and high voltage logic circuits 600 may energy
Enough implement any logic function.Logic circuit 600 receives K input letter of the first voltage range with 0V to Vdd
Number (Vin1 to VinK), wherein K can be 1 or bigger.K input signal is implemented to patrol by logic circuit 600
Collect function, and output signal Vout with the full voltage range from Vss to Vdd is provided.Full voltage range contains first
Voltage range and the second voltage range from 0V to Vss.
In exemplary design shown in figure 6, logic circuit 600 comprises level shifter 610, first and processes circuit
620a, the second process circuit 620b and output circuit 650.Level shifter 610 operates between full voltage range.The
One processes circuit 620a is included between first voltage range the logic circuit 630a and delay circuit 640a of operation.Second
Process circuit 620b and be included between the second voltage range the logic circuit 630b and delay circuit 640b of operation.Output electricity
Road 650 operates between first voltage range or the second voltage range at arbitrary given time.
Level shifter 610 receives K the input signal with first voltage range, and offer has the second voltage range
K through the signal (Vshifted1 to VshiftedK) of level shift.Level shifter 610 can be by the K in Fig. 3
Individual level shifter 106 is implemented, one level shifter 106 of each input signal.Each level shifter 106 can
Receive the corresponding input signal with first voltage range, and the correspondence with the second voltage range can be provided through level shift
Signal.
Processing in circuit 620a first, logic circuit 630a receives K the input signal with first voltage range,
Described K input signal is implemented wanted logic function, and provides its output to arrive delay circuit 640a.Logic circuit 630a
Can be implemented by phase inverter, gate and/or other logic module.Delay circuit 640a is to from logic circuit 630a
Output signal operation, and provide there is the first M signal Vtop of first voltage range.Delay circuit 640a can lead to
The even number of inverters crossing series coupled is implemented.These phase inverters can be implemented by the MOS transistor of suitable dimension
To obtain the postponing of Vtop signal, the transformation of low level to high level and high level to low level transformation, in order to avoid
Due to voltage spikes in output circuit 650 during switching.
Processing in circuit 620b second, logic circuit 630b receives has K of the second voltage range through level shift
Signal, described K is implemented wanted logic function through the signal of level shift, and provides its output to arrive delay circuit
640b.Logic circuit 630b can pass through phase inverter, gate and/or other logic module to be similar to logic circuit 630a
Mode implement.Output signal from logic circuit 630b is operated by delay circuit 640b, and offer has second
Second M signal Vbot of voltage range.Delay circuit 640b can implement by the even number of inverters of series coupled.
These phase inverters can be implemented to obtain postponing and to change of Vbot signal by the MOS transistor of suitable dimension,
So as the due to voltage spikes in output circuit 650 during avoiding switching.Also can omit delay circuit 640a and 640b.?
Under this situation, institute can be reached by selecting suitable dimension MOS transistor in logic circuit 630a and 630b
Postpone and change.
In exemplary design shown in figure 6, it is brilliant that output circuit 650 comprises nmos pass transistor 652 and PMOS
Body pipe 654.Nmos pass transistor 652 makes its grid be coupled to circuit ground so that it is source electrode receives from delay circuit 640b
Vbot signal, and make its offer Vout signal that drains.PMOS transistor 654 makes its grid be coupled to circuit ground,
Make its source electrode receive from the Vtop signal of delay circuit 640a, and make it drain to be coupled to nmos pass transistor 652
Drain electrode.
As shown in Figure 6, output circuit 650 is to be implemented by phase inverter, and described phase inverter makes it input and is connected to electricity
Road ground connection, and it is higher and lower supply voltage is provided by Vtop and Vbot signal respectively.Vtop and Vbot signal has
There is identical logical values, but there is different voltage ranges.Exporting for logic high, Vtop signal is in Vdd, and
Vbot signal is in 0V.In this situation, nmos pass transistor 652 cuts off, and PMOS transistor 654 is connected, and
Vout signal is set to Vdd.Exporting conversely, for logic low, Vtop signal is in 0V, and Vbot letter
Number it is in Vss.In this situation, nmos pass transistor 652 is connected, and PMOS transistor 654 is cut off, and Vout
Signal is set to Vss.Vout signal thus there is full voltage range, even if MOS transistor 652 and 654 is in office
One given time only observes that first voltage range or the second voltage range are the most such.
Although not showing in Fig. 6, but another level shifter can be used for top path, and can receive and have the first voltage model
K the input signal enclosed and offer have K the signal through level shift of tertiary voltage scope.First processes circuit
Logic circuit 630a and delay circuit 640a in 620a can operate then between tertiary voltage scope.Output circuit 650
Can operate between the second voltage range or tertiary voltage scope at arbitrary given time.
First voltage range and the second voltage range can be each less than the MOS transistors in order to implement logic circuit 600
Breakdown voltage.Full voltage range can be more than the breakdown voltage of the MOS transistor in order to implement output circuit 650.But,
These MOS transistors only observe first voltage range or the second voltage range at arbitrary given time, though Vout letter
Full voltage range number can be made to swing the most such.
Level shifter described herein and high voltage logic circuits can be used for various electronic installation, such as radio communication
Device, cellular phone, personal digital assistant (PDA), handheld type devices, radio modem, meter on knee
Calculation machine, wireless phone, radio receiver, blue-tooth device, consumer electronics etc..Level shifter is described below
And/or the use that high voltage logic circuits is in radio communication device (it can be cellular phone or other device a certain).
Fig. 7 shows the block diagram of the exemplary design of radio communication device 700.In this exemplary design, wireless device 700
Comprise numerical portion 710 and transceiver 720.Transceiver 720 comprises transmitter 730 and the receptor supporting two-way communication
740。
In numerical portion 710, processor/controller 712 can perform the various functions for wireless device 700, such as,
Process positive transmission or the data of reception.Memorizer 714 can store the program code for processor/controller 712 and data.
Level shifter and/or high voltage logic circuits 716 can (such as) from processor/controller 712 and/or other circuit block
Receive input signal, and output signal can be produced.Numerical portion 710 also can comprise other module, processor, memorizer
Deng.
In a transmission path, numerical portion 710 can process (such as, encode and modulate) data waiting for transmission, and provides
Output baseband signal is to transmitter 730.In transmitter 730, upconverter circuit 732 can process and (such as, put
Greatly, filtering and up-conversion) described output baseband signal the signal through up-conversion is provided.Power amplifier (PA)
Module 734 can amplify the signal through up-conversion to obtain wanted output power levels, and provides output radio frequency (RF) letter
Number, described output radio frequency (RF) signal can be delivered via switch/duplexer 736 and transmit via antenna 738.
In RX path, antenna 738 can receive the RF signal transmitted by base station and/or other transmitter platform, and can carry
For the RF signal received, described received RF signal can be delivered via switch/duplexer 736 and provide and connect
Receive device 740.In receptor 740, front-end module 742 can process the RF that (such as, amplify and filter) is received
Signal, and amplified RF signal is provided.Frequency down-converter circuit 744 can process further (such as, frequency reducing conversion,
Filtering and amplify) amplified RF signal and provide input baseband signal to numerical portion 710.Numerical portion 710 can
Process the data that (such as, digitized, demodulation) input baseband signal is transmitted with recovery further.
Level shifter and/or high voltage logic circuits 750 can receive the input signal from numerical portion 710, and can produce
Life turns for upconverter circuit 732, PA module 734, switch/duplexer 736, front-end module 742 and/or frequency reducing
The output signal of converter circuit 744.For example, level shifter and/or high voltage logic circuits 750 can produce and be used for
The control signal of other circuit unit in switch and/or PA module 734 and switch/duplexer 736.
In exemplary design, equipment (such as, integrated circuit, electronic unit, wireless device etc.) can comprise level and move
Position device, described level shifter includes the drive circuit being coupled to latch, such as, as shown in Figure 1A.Drive
Device circuit can receive the input signal with first voltage range, and can provide to have and be different from the second of first voltage range
The driving signal of voltage range.Latch can receive described driving signal, and provides the output letter with the second voltage range
Number.In exemplary design, drive circuit can include the control signal generator being coupled to latch driver, such as,
As shown in fig. 1b.Control signal generator can receive input signal, and provide and have more than first voltage range and the
The control signal of three/full voltage range of each in two voltage ranges.Latch driver can receive described control to be believed
Number and driving signal is provided.Described input signal can be the differential wave including Vinp and Vinn signal.Described driving is believed
Number can be another differential wave including Vdrp and Vdrn signal.
In exemplary design, drive circuit can include four phase inverters and two MOS transistors, such as, such as Fig. 3
Or shown in 5.First phase inverter (such as, the phase inverter 312 in Fig. 3) can receive Vinp signal, and provides first
M signal Vintp.Second phase inverter (such as, phase inverter 314) can be coupled to the first phase inverter, and can receive described
First M signal also provides the first control signal Vctrlp.First MOS transistor (such as, nmos pass transistor 322)
Can be coupled to described second phase inverter, and the first control signal can be received and Vdrp signal is provided.3rd phase inverter (example
As, phase inverter 316) Vinn signal can be received, and the second M signal Vintn is provided.4th phase inverter is (such as,
Phase inverter 318) can be coupled to the 3rd phase inverter, and the second M signal can be received and the second control signal Vctrln is provided.
Second MOS transistor (such as, nmos pass transistor 324) can be coupled to described 4th phase inverter, and can receive institute
State the second control signal and Vdrn signal is provided.
In exemplary design, the first phase inverter and the 3rd phase inverter can operate between each comfortable first voltage range.Second
Phase inverter and the 4th phase inverter can each depend on the logical value of input signal and at first voltage range or the second voltage model
Operate between enclosing.Vintp signal and Vdrp signal can be received by the second phase inverter as supply voltage.4th phase inverter can
Vintn signal and Vdrn signal are received as supply voltage.When input signal has the first logical value, second is anti-phase
Device can operate between first voltage range, and can provide the first voltage (such as, Vdd) to Vctrlp signal.Work as input
When signal has the second logical value, the second phase inverter can operate between the second voltage range, and can carry to Vctrlp signal
For the second voltage (such as, Vss).Tertiary voltage scope can be defined by the first voltage and the second voltage.
In exemplary design, the first MOS transistor and the second MOS transistor can be nmos pass transistor, described
Nmos pass transistor makes it drain and is coupled to the high voltage of the second voltage range, and make respectively its source electrode provide Vdrp and
Vdrn signal, (such as) as shown in Figure 3.In another exemplary design, the first MOS transistor and the 2nd MOS
Transistor can be PMOS transistor, and described PMOS transistor makes it drain and is coupled to the low-voltage of the second voltage range,
And make respectively its source electrode provide Vdrp and Vdrn signal, (such as) as shown in Figure 5.
In exemplary design, first voltage range can be the most overlapping with the second voltage range.First voltage range just can contain
The scope of voltage, and the second voltage range can contain the scope of negative voltage.Or, first voltage range can contain positive voltage
The first scope, and the second voltage range can contain second scope of positive voltage of the first scope being different from positive voltage.Drive
Dynamic device circuit and latch can by have can more than each in first voltage range and the second voltage range but be less than
The MOS transistor of the breakdown voltage of tertiary voltage scope is implemented.
Fig. 8 shows the exemplary design of the process 800 for performing level shift.Can receive and there is first voltage range
Input signal (frame 812).The driving signal (frame 814) with the second voltage range can be produced based on input signal.
Described second voltage range may differ from described first voltage range.Described driving signal can be latched and to obtain, there is the second electricity
The output signal (frame 816) of pressure scope.
In the exemplary design of frame 814, the control letter with three/full voltage range can be produced based on input signal
Number.Tertiary voltage scope can be more than each in first voltage range and the second voltage range.Can be next based on controlling letter
Number and produce driving signal.
Input signal can be the differential wave including Vinp and Vinn signal, and driving signal can be to include Vdrp and Vdrn
Another differential wave of signal.In the exemplary design of frame 814, can be based on Vinp signal (such as, by
One phase inverter) produce the first M signal.Can be based on described first M signal (such as, by the second phase inverter)
Produce the first control signal.(such as, by the first MOS transistor) can produce based on described first control signal
Vdrp signal.Can (such as, by the 3rd phase inverter) produces the second M signal based on Vinn signal.Can be based on
Described second M signal and (such as, by the 4th phase inverter) produces the second control signal.Can be based on described second control
Signal processed and (such as, by the second MOS transistor) produce Vdrn signal.
In another exemplary design, equipment (such as, integrated circuit, electronic unit, wireless device etc.) can comprise height
Voltage logic circuit, described high voltage logic circuits includes level shifter, the first and second circuit and output circuit,
(such as) as shown in Figure 6.Level shifter can receive at least one input signal with first voltage range, and
At least one with the second voltage range can be provided through the signal of level shift.Described first circuit can logic-based function
Process at least one input signal described, and first M signal with first voltage range can be provided.Described second
Circuit can process based on described logic function described at least one through the signal of level shift, and can provide there is the second electricity
Second M signal of pressure scope.Output circuit can receive described first M signal and the second M signal, and can provide
There is the output letter of the tertiary voltage scope more than each in described first voltage range and described second voltage range
Number.
In exemplary design, level shifter can include at least one the driver electricity being coupled at least one latch
Road, such as, for drive circuit and the set of latch of each input signal.At least one drive circuit described
At least one input signal can be received, and at least one with the second voltage range can be provided to drive signal.Described at least
One latch can receive at least one driving signal described, and at least one can be provided through the signal of level shift.First
Circuit can include that (i) is in order to receive at least one input described at least one input signal described logic-based function treatment
First logic circuit of signal, and the first delay of the target delay and transformation that (ii) is in order to obtain the first M signal
Circuit.Second circuit can include (i) in order to receive described at least one at the signal logic-based function of level shift
Described in reason, at least one is through the second logic circuit of the signal of level shift, and (ii) is in order to obtain the second M signal
Target delay and the second delay circuit of transformation.Described first circuit and/or described second circuit also can get rid of deferred telegram
Road.Output circuit can include PMOS transistor and nmos pass transistor, described transistor can as shown in Figure 6 as coupling
Close.
Fig. 9 shows the exemplary design of the process 900 for producing the signal with bigger voltage swing.Can level shift
There is at least one input signal of first voltage range there is at least one of the second voltage range move through level to obtain
The signal (frame 912) of position.Logic-based function can process at least one input signal described, to obtain, there is the first voltage
First M signal (frame 914) of scope.Can based on described in described logical function treatment at least one through the letter of level shift
Number to obtain, there is second M signal (frame 916) of the second voltage range.In the middle of can be based on the first M signal and second
Signal produces the output signal (frame 918) with three/full voltage range.Described tertiary voltage scope can be more than described the
Each in one voltage range and described second voltage range.
Level shifter described herein and high voltage logic circuits may be implemented in IC, analog IC, RF IC (RFIC),
On mixed frequency signal IC, special IC (ASIC), printed circuit board (PCB) (PCB), electronic installation etc..Level shifter
Also such as complementary metal oxide semiconductors (CMOS) (CMOS), NMOS, PMOS, double can be passed through with high voltage logic circuits
The various IC such as pole junction transistors (BJT), bipolar CMOS (BiCMOS), SiGe (SiGe), GaAs (GaAs)
Technology manufactures.
The equipment implementing level shifter described herein and/or high voltage logic circuits can be that self-contained unit can be maybe
The part of larger device.Device can be that (i) independent IC, (ii) can comprise the memorizer for storing data and/or instruction
The set of one or more IC of IC, (iii) such as RF receptor (RFR) or RF transmitter/receptor (RTR)
Can be embedded in other device Deng ASIC, (v) such as RFIC, (iv) such as mobile station modems (MSM)
Module, (vi) receptor, cellular phone, wireless device, mobile phone or mobile unit, (vii) etc..
In one or more exemplary design, described function can use hardware, software, firmware or it is any
Combination is implemented.If implemented with software, then can be using described function as one or more instructions or code
It is stored on computer-readable media or transmits via computer-readable media.Computer-readable media comprises computer and deposits
Storage media and communication medium, communication medium comprises and promotes computer program any matchmaker to the transmission at another at
Body.Storage media can be can be by any useable medium of computer access.Unrestricted as an example, this computer-readable
Media comprise the steps that RAM, ROM, EEPROM, CD-ROM or other disk storage, disk memory or its
Its magnetic storage device, or may be used to carrying or storage in instruction or the wanted program code of data structure form and can be by counting
Other media any of calculation machine access.And, any connection be properly be referred to as computer-readable media.For example,
If use coaxial cable, fiber optic cables, twisted-pair feeder, numeral subscriber's line (DSL) or wireless technology (such as infrared ray,
Radio and microwave) and from website, server or other remote source software, then coaxial cable, fiber optic cables,
Twisted-pair feeder, DSL or wireless technology (such as infrared ray, radio and microwave) are contained in the definition of media.As herein
Used in, disk and CD comprise compact disk (CD), laser disk, CD, digital image and sound optical disk (DVD),
Floppy disk and Blu-ray Disc, wherein disk generally reproduces data in the way of magnetic, and CD is by laser in an optical manner
Reproduce data.The combination of above-mentioned each thing also should be included in the range of computer-readable media.
Being previously described so that any those skilled in the art can manufacture or use the present invention of the present invention is provided.To this
The various amendments of invention are to it will be apparent to those skilled in the art that and in the situation without departing from the scope of the present invention
Under, generic principles defined herein is applicable to other variant.Therefore, the present invention is not intended to be limited to described herein
Example and design, and the widest scope consistent with principles disclosed herein and novel feature should be met.
Claims (6)
1. an electronic equipment, comprising:
Level shifter, it is in order to receive at least one input signal with first voltage range and to carry
For there is at least one of the second voltage range through the signal of level shift；
First circuit, it processes at least one input signal described in order to logic-based function and provides
There is the first M signal of described first voltage range；
Second circuit, its in order to based on described logic function process described at least one through level shift
Signal and provide there is the second M signal of described second voltage range；And
Output circuit, it is in order to receive described first M signal and described second M signal and to provide
There is the tertiary voltage more than each in described first voltage range and described second voltage range
The output signal of scope,
Wherein said output circuit includes
P-channel metal-oxide-semiconductor PMOS transistor, it is in order to receive institute at source electrode
State the first M signal and described output signal is provided at drain electrode, and
N-channel metal-oxide semiconductor (MOS) nmos pass transistor, it is coupled to described PMOS
Transistor and in order at source electrode receive described second M signal and at drain electrode provide described defeated
Go out signal.
Electronic equipment the most according to claim 1, described level shifter includes
At least one drive circuit, it has in order to receive at least one input signal described offer
At least one of described second voltage range drives signal, and
At least one latch, it is coupled at least one drive circuit described and described in order to receive
Described at least one driving signal offer, at least one is through the signal of level shift.
Electronic equipment the most according to claim 1, described first circuit and described second circuit each wrap
Include to receive at least one input signal described or described at least one through level shift signal also
Based on described logic function process at least one input signal described or described at least one through level
The logic circuit of the signal of displacement.
Electronic equipment the most according to claim 1, described first circuit or described second circuit wrap respectively
Include to obtain described first M signal or the target delay of described second M signal and transformation
Delay circuit.
5. for the method performing level shift, comprising:
Level shift has at least one input signal of first voltage range and has the second electricity to obtain
At least one of pressure scope is through the signal of level shift；
Logic-based function processes at least one input signal described and has described first electricity to obtain
First M signal of pressure scope；
Based on described logic function process described at least one through the signal of level shift to obtain tool
There is the second M signal of described second voltage range；And
Produce based on described first M signal and described second M signal there is tertiary voltage model
The output signal enclosed, described tertiary voltage scope is more than described first voltage range and described second electricity
Each in pressure scope,
Wherein produce and there is the output signal of tertiary voltage scope include:
Receive in described first at P-channel metal-oxide-semiconductor PMOS transistor source electrode
Between signal and at drain electrode provide described output signal, and
It is being coupled to the N-channel metal-oxide semiconductor (MOS) NMOS of described PMOS transistor
Receive described second M signal at transistor source and described output signal is provided at drain electrode.
Method the most according to claim 5, at least one input signal described in described level shift includes:
Produce based at least one input signal described there is at least the one of described second voltage range
Individual driving signal, and
Latch described at least one drive signal with obtain described at least one through the signal of level shift.
Applications Claiming Priority (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US22773009P | 2009-07-22 | 2009-07-22 | |
| US61/227,730 | 2009-07-22 | ||
| US12/633,675 | 2009-12-08 | ||
| US12/633,675 US8283964B2 (en) | 2009-07-22 | 2009-12-08 | Level shifters and high voltage logic circuits |
Related Parent Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201080032880.0A Division CN102474242B (en) | 2009-07-22 | 2010-07-22 | Level shifters and high voltage logic circuits |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103944539A CN103944539A (en) | 2014-07-23 |
| CN103944539B true CN103944539B (en) | 2016-11-30 |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5894227A (en) * | 1996-03-15 | 1999-04-13 | Translogic Technology, Inc. | Level restoration circuit for pass logic devices |
| US5945865A (en) * | 1997-01-10 | 1999-08-31 | Microchip Technology Incorporated | Full-swing high voltage data latch |
| CN1734942A (en) * | 2004-08-09 | 2006-02-15 | 三星电子株式会社 | Level shifter with low-leakage current |
| CN101371441A (en) * | 2006-01-12 | 2009-02-18 | 高通股份有限公司 | Digital output driver and input buffer using thin-oxide field effect transistors |
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5894227A (en) * | 1996-03-15 | 1999-04-13 | Translogic Technology, Inc. | Level restoration circuit for pass logic devices |
| US5945865A (en) * | 1997-01-10 | 1999-08-31 | Microchip Technology Incorporated | Full-swing high voltage data latch |
| CN1734942A (en) * | 2004-08-09 | 2006-02-15 | 三星电子株式会社 | Level shifter with low-leakage current |
| CN101371441A (en) * | 2006-01-12 | 2009-02-18 | 高通股份有限公司 | Digital output driver and input buffer using thin-oxide field effect transistors |
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