CN103929059B - Manipulator including current limitation scheme - Google Patents

Abstract

A kind of manipulator, is configured to control to flow through while input voltage is converted into output voltage the switching of the electric current of the inducer of transducer according to current limitation scheme, and it includes current limitation generator and comparator network.Current limitation generator is configured to input voltage based on boost converter or output voltage, the inductance of inducer, clock signal and predetermined maximum output current provide the most tiltedly time-dependent current cut-off current.Comparator network is configured to the current sense value of the electric current by instruction is flow through described inducer and compares with the smaller compensated in error amount and described periodicity oblique time-dependent current cut-off current and the switching of the electric current that provides switch controlling signal to control to flow through inducer.Transducer can be configured to the peak current Schema control transducer under boosting or decompression mode.

Description

Manipulator including current limitation scheme

Cross-Reference to Related Applications

This application claims the U.S. Provisional Application S/N.61/753,081 that submits on January 16th, 2013 with And the U.S. Provisional Application S/N.61/774 that on March 7th, 2013 submits to, the rights and interests of 453, these applications Full content incorporated herein by reference for the intentional and purpose of institute.

Accompanying drawing is sketched

The benefit of the present invention, feature and excellent will be better understood when with reference to following description and accompanying drawing Point, in the accompanying drawings:

Fig. 1 is the simplified block diagram of the electronic equipment being furnished with power system realized according to an embodiment, This power system has bust-boost converter, and this bust-boost converter has and comprises current limitation side The manipulator of case；

Fig. 2 is the simplification schematic block of the bust-boost converter of the Fig. 1 according to an embodiment realization Figure；

Fig. 3 is the figure being in boost mode during the lower state being shown in and having relatively low output loading The sequential chart of the operation of the transducer of 1；

Fig. 4 is the PWMB pulse control signal for boost operations pattern for forming Fig. 2 The simplified block diagram of a part of manipulator of Fig. 1；

Fig. 5 is to illustrate the transducer that the staged of response output loading increases the Fig. 1 under boost mode The sequential chart of operation, and there is wherein VI_VCL be maintained at the fixing or limited current state of constant level；

Fig. 6 is the rate conversion net that can be used to form instruction output voltage with the voltage of input voltage ratio The schematic diagram of network；

Fig. 7 is the sequential chart of the operation of the rate conversion circuit illustrating Fig. 6；

Fig. 8 is the crest-crest ripple of the inducer that can be used to form the transducer that Fig. 2 is flow through in instruction The schematic diagram of the ripple switching network of the voltage of electric current；

Fig. 9 is for forming the valley current electricity of instruction valley current current limliting level according to an exemplary embodiment The simplified block diagram of the valley current current limited generator of Fig. 4 of stream voltage；

Figure 10 is that the valley current limit voltage drawing the given switching circulation for clock is relative to the time The sequential chart of circulation；

Figure 11 be illustrate in response to output loading staged increase Fig. 2 transducer operation with And the valley current limit voltage substantially asserted by the valley current current limited generator of Fig. 4 in accordance with equation (11) Sequential chart；

Figure 12 be illustrate be configured to peak current Schema control transducer and simultaneously response output loading with The operation of the transducer of Fig. 2 that the staged increase of constant current cut-off current operates in buck mode Sequential chart；

Figure 13 is to illustrate to comprise ramp signal and can be used to overcome and be configured to peak current Schema control Transducer also operates the fixed current current limliting level issue of transducer of Fig. 2 in buck mode simultaneously The sequential chart of one of current limitation voltage circulation；

Figure 14 is to illustrate to comprise ramp signal and can be used to overcome and be configured to Controlled in Current Mode and Based and turn Parallel operation also operates the fixed current current limliting level issue of transducer of Fig. 2 under boost mode simultaneously The sequential chart of one circulation of current limitation voltage；

Figure 15 is to illustrate to be configured to peak current Schema control transducer and in response in buck mode Substantially follow equation (12) or under boost mode, substantially follow equation (13) there is current limitation level The staged of output loading increase the transducer of Fig. 2 under decompression mode or boost mode of operation The sequential chart of operation；And

Figure 16 is that the manipulator replacing Fig. 2 to be configured to peak current Schema control transducer to Fig. 2 The reduced pressure operation pattern of transducer and boost operations pattern form PWMA and PWMB pulse The simplified block diagram of a part for the manipulator of control signal.

Detailed description of the invention

The peak current of the inducer flowing through transducer can be carried out current limliting to avoid the saturated of inducer.Peak Current limitation scheme is generally used for step-down controller, and this step-down controller produces from higher input voltage One adjusted output voltage.Owing to electric current is limited in predetermined maximum level, peak current current limliting side Case can substantially avoid inducer saturated, and wherein this maximum level is size Selection based on inducer. Valley current current limliting scheme is typically for boost converter, and this boost converter is by the level of input voltage Boost to produce higher adjusted output voltage.Valley current current limliting scheme only uses inductor current Paddy cut-off current controls to realize pulsewidth modulation (PWM).But, the peak current of valley current current limliting scheme is not It is the most controlled.Actual peak current in valley current current limliting scheme depends on valley current current limliting and electric current Ripple.Some application using the state of fixing valley current current limliting such as to load ladder can be made Becoming the ON time that inductor current is long, this causes the biggest peak current.Can after big crest Can follow relatively short crest, and big/little peak pattern several circulations repeatable, thus cause Subharmonic oscillation.

Valley current current limliting scheme may need bigger inducer saturated to avoid during bigger peak value. Big inducer is the most desired, because therefore it the most greatly and consume the circuit space of preciousness. It addition, bigger inducer more consumes cost.Maximum load current can be limited in required by subharmonic oscillation Below target level.In buck-boost configures, unusual current limitation operation can cause blood pressure lowering and liter False mode transition between press operation, thus causes instability and/or operates improperly.

Obtaining stable operation under substantially invariable peak current current limliting level and this current limitation state is Desired, this is particularly advantageous for using the transducer of valley current current limliting scheme.More stable Operation avoid too much peak, this can reduce the size of inducer, thus reduces its size and cost. More stable operation reduces or even essentially eliminates subharmonic oscillation, and this permission obtains the output required Current level.More stable operation decreases between the buck and boost modes in buck-boost configuration False triggering.

Under some state of reduced pressure operation pattern and boost operations pattern, for peak current pattern Control transducer and there is also similar problem.Wish to reduce subharmonic oscillation, thus obtain the defeated of requirement Go out current level.More stable operation decrease buck-boost configuration in buck and boost modes it Between false triggering.

Fig. 1 is the letter of the electronic equipment 100 being furnished with power system 101 realized according to an embodiment Changing block diagram, this power system 101 has bust-boost converter 102, this bust-boost converter 102 There is the manipulator 103 comprising current limitation scheme.The present invention is illustrated as using bust-boost converter 102, although also contemplating for boost converter or step-down controller.Electric power system 101 is produced as electronics dress One or more supply voltages of the other system device offer power of 100 are provided.Such as, as it can be seen, Transducer 102 produces output voltage VO.

In the embodiment shown, electronic installation 100 includes processor 107 and peripheral system 109, place Reason device 107 and peripheral system 109 all couple to receive self-contained electric system 101 via bus 105 One or more supply voltages, bus 105 includes any combination of power and/or signal conductor.Bus 105 can distribute output voltage VO or its version.In the embodiment shown, peripheral system 109 can include System storage 111 is (such as, including RAM and ROM type equipment and Memory Controller etc. Any combination) and any combination of input/output (I/O) system 113, this input/output 113 Can include system controller etc., such as graphics controller, interrupt control unit, keyboard and mouse controller, System memory devices controller (such as, for the controller etc. of hard disk drive) etc..Shown system System is the most exemplary, because it will be understood by those skilled in the art that many processor systems and support Device can be integrated in processor chips.

Electronic equipment 100 can be any kind of computer or calculating equipment, such as computer system (such as, notebook, desk computer, netbook computer, tablet PC etc.), Media tablet device (iPad, the Kindle etc. of Amazon Company's production that such as, Apple produces Deng), communication equipment (such as, cell phone, smart phone etc.), other kinds of electronics dress Put (such as, media player, recording equipment etc.).Electric power system 101 can be configured to include Battery (rechargeable or non-rechargeable) and/or can be configured to work together with exchanging (AC) adapter etc..

Fig. 2 is the simplified block diagram of the bust-boost converter 102 realized according to an embodiment. Input voltage VIN is provided to first current terminal of electrical switch Q1, and this electrical switch Q1 has It coupled to be formed the second current terminal of the node 205 of the first switching voltage SWA.Electrical switch Q2 Have and coupled to the first current terminal of node 205 and coupled to source voltage reference node (such as (GND) the second current terminal).The voltage level of GND can be any suitable voltage level, example As positive and negative and zero.Output voltage VO is formed at first current terminal of electrical switch Q3, this electronics Switch Q3 has the second current terminal coupleding to form the node 207 of second switch voltage SWB. Electrical switch Q4 has and coupled to the first current terminal of node 207 and coupled to the second of GND Current terminal.The output inductor 209 with inductance LO is coupling between node 205,207.

First switch driver 201 has the reception input of the first pwm signal PWMA, coupling To Q1 gate terminal first output and coupled to Q2 gate terminal second output.First switch Driver 201 illustratively includes noninverting buffer amplifier 202 in simplified form, and this is noninverting slow Rush amplifier 202 and there is the input receiving PWMA and the output coupleding to Q1 grid, and include This inverter buffer amplifier 204 of inverter buffer amplifier 204 have receive PWMA input with And it coupled to the output of Q2 grid.Second switch driver 203 has reception the second pwm signal The input of PWMB, it coupled to the first output of the gate terminal of Q3 and coupled to the gate terminal of Q4 Second output.Second switch driver 203 illustratively includes noninverting Hyblid Buffer Amplifier the most in simplified form This noninverting buffer amplifier 208 of device 206 has the input of reception PWMB and coupled to Q3 The output of grid, and include that this inverter buffer amplifier 208 of inverter buffer amplifier 208 has and connect Receive the input of PWMB and coupled to the output of Q4 grid.

Bust-boost converter 102 includes manipulator 103, and this manipulator receives one or more sensings Signal S also forms PWMA and PWMB signal with control signal conversion.S signal can include such as Input voltage VIN, output signal VO or its version (such as via potentiometer etc.) and instruction blood pressure lowering- Any one or more signals of one or more current levels in boost converter 102.At one In embodiment, the electric current ISEN of the current terminal flowing through Q1 sensed by manipulator 103 or obtain with Relevant voltage VISEN (Fig. 3) indicating it is provided.Output current IO is illustrated as flowing from node 207 To the output node producing VO.

In one embodiment, manipulator 103 (directly or indirectly) monitors VIN and VO and in fall Switch between press operation pattern and boost operations pattern.VO can be adjusted to predetermined voltage level and VIN can be unjustified voltage level, and this unjustified voltage level is from higher than VO's Adjust voltage to change to higher than in the voltage range adjusting voltage of VO.As non-restrictive example, can Thering is provided the VIN, VIN can be from 1V to 5V from battery etc., and VO be adjusted to 3.3V.When VIN is low When VO, manipulator 103 operates transducer 102 with more higher electricity than VIN under boost mode VO is adjusted under voltage level.When VIN is higher than VO, manipulator 103 operates in buck mode and turns Parallel operation 102 is to adjust VO under the voltage level lower than VIN.Although being not described further, so And manipulator 103 may be configured such that when VIN with VO is roughly the same with smooth manner at blood pressure lowering and liter Transition between die pressing type, to avoid vibration or the notable low-frequency disturbance of VO or to deviate from.

In one embodiment, when being in decompression mode, PWMB is asserted by manipulator 103 Fixing low value is to turn on Q3 and to end Q4, and thus the actual funeral of node 207 coupled to VO.In fall Under die pressing type, manipulator 103 triggers (toggle) PWMA repeatedly to adjust V0.Work as PWMA For time high, Q1 is switched on and Q2 is cut off, so that VIN coupled to node 205 to increase inducer Electric current in 209.At PWM end points, such as when ISEN reaches maximum level or in response to clock Signal or other control condition, for the second stage of circulation, Q1 be cut off then Q2 switched on Reduce the electric current in inducer 209.Manipulator 103 monitors one or more operating parameter and with at warp The mode adjusting VO in the voltage range adjusted triggers PWMA, repeatedly such as those skilled in that art Understand.

In one embodiment, when being in boost mode, PWMA is asserted by manipulator 103 Fixing high level is to turn on Q1 and to end Q2, and thus the actual funeral of node 205 coupled to VIN.Rising Under die pressing type, manipulator 103 triggers PWMB repeatedly to adjust VO.When PWMB is high, Q4 is switched on and Q3 is cut off, so that node 207 coupled to GND to increase in inducer 209 Electric current.At PWM end points, such as when ISEN reaches maximum level or in response to clock signal or Other control condition, for the second stage of circulation, it is switched on to reduce electricity that Q4 is cut off then Q3 Electric current in sensor 209.Manipulator 103 monitors one or more operating parameter and with adjusted The mode adjusting VO in voltage range triggers PWMB repeatedly, as those skilled in that art understand.

Each in driver 201,203 illustrates in simplified form and can include the support electricity added Road is to realize suitable operation.Such as, driver 201,203 can include that adjunct circuit is to guarantee one Time only one electrical switch turns on, thus avoids VIN or VO of swinging earth.Additionally, high side Driver 202,206 can include boostrap circuit or charge pump circuit so that respectively at VIN and VO rail The grid of Q1 and Q3 is driven on road.Electrical switch Q1-Q4 is each illustrated as technology in this area N-channel metal-oxide semiconductor (MOS), field-effect transistor (MOSFET) known to personnel.But also may be used Use other type of electronic switching device, the most other type of FET etc. and other type of crystalline substance Body pipe, such as bipolar junction transistor (BJT) or igbt (IGBT) etc..

Fig. 3 is to be in turning of boost mode during the limit being shown in and having relatively low output loading The sequential chart of the operation of parallel operation 102.In the embodiment shown, transducer 102 is operated in clock signal Under CLK, this clock signal clk has constant switch periods T of band_SWFixed frequency level.CLK Signal is used as the timing signal of transducer 102, as further described herein.CLK can It is provided to manipulator 103 from external source (not shown), can be produced by manipulator 103 based on external clock, Or produce from inside.V_ISENIt is the voltage of the level of the electric current ISEN flowing through Q1 that instruction senses. V_COMPIt is the compensation voltage at the output of the error amplifier 401 being described further below.CLK、 V_ISEN、V_COMP, SWA, PWMB and SWB signal or voltage level be to describe relative to the time 's.At boost mode, PWMA keeps high, and thus Q1 is held on, and this makes SWA keep coupling In VIN.When PWMB is high, Q4 turns on and flows through the electric current such as V of inducer 209_ISENOn Increase as indicated by rising.SWB is pulled low to GND, and PWMB is high.

At very first time t1, the pulse on CLK makes manipulator 103 drag down PWMB, so that Q4 End and make Q3 turn on.Node 207 is coupled to VO for this so that SWB rises to the voltage of VO Level (after transition declines).Owing to VO is in more higher voltage level than VIN, therefore flow through electricity The electric current of sensor 209, such as V_ISENAs instruction, reduce with substantially invariable speed.Work as V_ISEN V is dropped at time t2_COMPVoltage level time, PWMB is switched to height by manipulator 103 again, So that V_ISENStart again to rise and to make SWB return to low.Grasp while load keeps relative stability Repeat by this way.

Fig. 4 is the modulation for forming the PWMB pulse control signal for boost operations pattern The simplified block diagram of a part for device 103.Output voltage VO or feedback signal VFB indicated as it The input of error amplifier 401 it is provided to by compensating circuit.Potentiometer etc. can be used to produce VFB To provide the sign level of VO.Compensate circuit diagram and be shown as impedance block Z1, Z2 (error amplifier 401 Feedback), these impedance blocks can include the combination in any of passive device, such as resistor and capacitor it Class.Reference voltage V REF is provided to another input of error amplifier 401, this error amplifier 401 produce compensation voltage V at its output_COMP.VREF represents requirement or adjusted VO electricity Voltage level or scope.V_COMPTypically represent VO and object run voltage level or the error level of scope Or the amount of deviating from.

V_COMPIt is provided to small voltage and selects an input of (LVS) device 403, this LVS device Part 403 receives valley current limit voltage V at its another input side_{I_VCL}And provide paddy electricity at its outlet side Stream limit voltage V_{I_VAL}.Valley current limit voltage V_{I_VCL}Instruction valley current current limliting level I_VCL。LVS Device 403 is at V_COMPAnd V_{I_VCL}Between make one's options and by V_{I_VAL}Assert with at its input side The V provided_COMPAnd V_{I_VCL}In a less identical voltage level.So, V is worked as_COMP＜ (or ≤)V_{I_VCL}Time, V_{I_VAL}Have and V_COMPIdentical voltage level, and work as V_{I_VCL}＜ (or≤) V_COMP Time, V_{I_VAL}Have and V_{I_VCL}Identical voltage level.Valley current current limited generator 407 produces and carries For V_{I_VCL}Voltage.

V_{I_VAL}And V_ISENIt is provided to the corresponding input of comparator network 405, this comparator network 405 also receive CLK and mode signal MD.MD is the signal of instruction buck or boost pattern.Ratio Relatively device network 405 operates with by V_{I_VAL}With V_ISENRelatively to pass through every time during boost operations pattern Assert CLK to determine when PWMB and be asserted as height when PWMB is asserted as low.Work as MD During instruction reduced pressure operation pattern, PWMB signal is kept asserting by comparator network 405 as previously mentioned For low.

Fig. 5 is that the staged illustrating response output loading increases the transducer 102 under boost mode The sequential chart of operation, and there is wherein V_{I_VCL}It is maintained at the fixing or limited current state of constant level.CLK Signal and V_ISEN、V_COMPAnd V_{I_VAL}Voltage is together with voltage V_{I_VCL (fixes)}Describe relative to the time, Wherein V_{I_VCL (fixes)}Voltage represents the V being in fixed level_{I_VCL}Signal.SWA, PWMB and SWB Signal has been not shown, but with the same way operation described before.Until time t5 (t1-t5), operate base Originally the step shown in Fig. 3, simultaneously V it are similar to_COMPLess than V_{I_VCL (fixes)}.Within this time, V_{I_VAL} Have and V_COMPIdentical voltage level.

As it can be seen, from the beginning of whenabouts t5, use load ladder at outlet side, this makes under VO Fall also responsively makes V_COMPRise.Although V_COMPKeep below V_{I_VCL (fixes)}, V_{I_VAL}With V_COMP Rise.Next pulse generation and V at time t6, CLK_ISENStart to become (ramp to declivity down).Along with V_ISENBecome to declivity, V_COMPRise above V_{I_VCL (fixes)}And V_{I_VAL}Stop Only rise and remain confined to V on the contrary_{I_VCL (fixes)}Same voltage level.V_ISENDrop to V_COMP Under, this does not cause PWMB switching until V_ISENArrival is fixed on V_{I_VCL (fixes)}V_{I_VAL}After Till one time t7.PWMB is at time t7 switching and V_ISENStart upward change and continue up Tiltedly straightening next pulse of time t8.Since V_ISENStart in the cycle relatively quickly to go up Rising, it continues to rise the relatively long time, and this caused before it declines again relatively high at time t8 V_ISENPeak level.PWMB is made again to switch in time t8, CLK pulse, thus V_ISENTurn over Turn an also road direction declivity and fade to the V of time t9_{I_VCL (fixes)}Voltage level.V_ISENThe long rise time Fall time afterwards causes at peak current relatively large for time t8.

When VISEN finally drops to V at time t9_{I_VAL}Time, it starts the most tiltedly to become.? After time t9, next CLK pulse relatively quickly occurs at time t10, and this causes at time t10 Relatively short V_ISENPeak.V_ISENUpset also becomes to declivity and arrives VI_VAL at time t11, this After time t10 relatively fast, thus V_ISENUpset to rise to another in latter time t12 high again Peak level.It is kept above V at VCOMP_{I_VCL (fixes)}While operate and repeat by this way, this leads Cause V_ISENA succession of the highest and low-down peak alternately.

Relatively large current peak and the pattern at the most high/low peak with the electric current flowing through inducer 209 Owing to many reasons is the most desired.This phenomenon is in the field of business to be referred to as subharmonic oscillation and occurs in paddy Current controlled current mode converter is less than under the dutycycle of 50%.The probability at big peak needs relatively Big inducer avoids the saturated of inducer.Big inducer is the most desired, because it is physically Relatively greatly and therefore consume the circuit space of preciousness.It addition, bigger inducer more consumes cost.Each high/ Low peak to and repeat pattern cause subharmonic oscillation, subharmonic oscillation can will can reach Large load current decreases below required level.In buck-boost configures, unusual current limitation behaviour Work can cause the false pattern transition between blood pressure lowering and boost operations, thus causes instability and/or improperly Operation.

The most desirably obtain under current limitation state substantially invariable peak current current limliting level and Stable operation.Current sensing signal can be added to or from V by utilizing_COMPSignal is derived The more stable operation that the compensation ramp signal of (as known in the art) obtains avoids subharmonic Vibration and the most too much peak, thus allow to reduce the size of inducer 209, thus drop further Low cost.More stable operation avoids subharmonic oscillation, thus allows higher output current level. More stable operation avoids the false triggering between the buck and boost modes in buck-boost configuration.

For boost converter, including operation bust-boost converter 102 under boost mode, flat All input current ISEN are (by V_ISENInstruction) and output current IO between relational dependence in PWM believe The dutycycle of number (such as PWMB), according to following equations (1):

IO=ISEN ((1-D) (1)

Average current input ISEN under boost mode can be confirmed as the peak current of inducer 209 I_PEAK(I_Peak) deduct the peak-to-peak ripple electric current of the ripple current flowing through inducer 209 (being caused by switch) I_{P-P_RIPPLE}(I_{P-P_ ripple}) half, according to following equations (2):

ISEN=I_{PE A K}-0.5·I_{P-P_R IPPL E} (2)

Therefore, output electric current I0 can be rewritten, as following by equation (2) is brought into equation (1) Equation (3) shown in:

IO=(I_PEAK-0.5·I_{P-P_RIPPLE})·(1-D) (3)

In order to obtain overcurrent protection, output current IO should be limited in predetermined maximum IO_MAX.In order to output electric current is limited in IO_MAX, the peak current I of inducer 209_PEAKLimited At maximum peak current level I_PEAKM, I_PEAKMDetermine according to equation below (4):

$I_{PEAKM}=\frac{{\mathrm{IO}}_{MAX}}{(1-D)}+0.5\·I_{P-P\_RIPPLE}---\left(4\right)$

For boost converter, including operation bust-boost converter 102 under boost mode, account for Empty can determine according to equation below (5) than, relation between input voltage VIN and output voltage VO:

$1-D=\frac{VIN}{VO}---\left(5\right)$

Therefore, based on equation (4), the peak current current limliting level I of (5)_PEAKMCan be according to equation below (6) Determine:

$I_{PEAKM}=\frac{VO}{VIN}\·{\mathrm{IO}}_{MAX}+0.5\·I_{P-P\_RIPPLE}---\left(6\right)$

Fig. 6 is the voltage V that can be used to form instruction VO/VIN ratio_VO/VINRate conversion network 600 Schematic diagram；Input voltage VIN controls current source 601, and this current source 601 will be proportional to VIN Electric current be supplied to node 602, this node 602 coupled to negative (or anti-phase) input of comparator 603. Node 602 forms ramp voltage V_RAMP.Capacitor CR is coupling between node 602 and GND. Single-pole single-throw(SPST (SPST) switchs 605 to be had the terminal being coupling between node 603 and GND and controls at it Input processed receives clock signal clk.The output voltage VO (K VO) revised by yield value " K " is carried Just (noninverting) input of supply comparator 603.It is noted that K VO can be to represent VO voltage level Feedback voltage V FB.Comparator 603 output is provided to the signal D1 of first end of resistor R1, The other end of resistor R1 coupled to node 604.Capacitor C1 be coupling in node 604 and GND it Between.Node 604 forms voltage V_VO/VIN, this voltage V_VO/VINThe ratio of instruction VO/VIN.

Fig. 7 is the sequential chart of the operation illustrating rate conversion circuit 600.When CLK is paramount by pulse Time, switch 605 closes at once, and capacitor CR is discharged by it, thus by ramp voltage V_RAMP(V_Slope) drag down (such as to GND).When switching 605 disconnection, capacitor CR is filled by current source 601 Electricity, thus V_RAMPBased on input voltage VIN with a upward change of speed.When CLK produces next arteries and veins When rushing, ramp voltage V_RAMPAgain be reset to low and operate repeat by this way, i.e. V_RAMP Tiltedly becoming between GND and crest value G VIN, wherein " G " is yield value.Whenever V_RAMPIt is reset to Time low, D1 is asserted as height by comparator 603.When VRAMP arrives the voltage level of K VO, D1 is asserted as low for remaining circulation by comparator 603.D1 be therefore have with VO/VIN it Signal than proportional dutycycle.R1 and C1 together forms resistance-capacitance (RC) wave filter, and it is right The value of D1 is averaging to form the voltage V of instruction ratio VO/VIN_VO/VIN。

For boost converter, including operation bust-boost converter 102 under boost mode, electricity The peak-to-peak ripple electric current I of sensor 209_{P-P_RIPPLE}Can determine according to following equations (7):

$I_{P-P\_RIPPLE}=\frac{D\·VIN}{LO}\·T_{SW}---\left(7\right)$

Wherein D is dutycycle and T_SWBeing the switch periods of PWMB, wherein LO is inducer 209 Inductance.

Fig. 8 is to can be used to form instruction to follow the I of equation (7)_{P-P_RIPPLE}Voltage V_{I_P-P_RIPPLE}'s The schematic diagram of ripple switching network 800；Input voltage VIN is provided to the input of amplifier 801, This amplifier 801 has the yield value 1/LO that the inverse of the inductance LO with inducer LO is equal.Put The output of big device 801 is provided to the VIN/LO of a switch terminal of spst switch S1 to instruction Voltage make and asserting, another switch terminal of spst switch S1 coupled to node 802 having and connects Receive the control input of PWMB.PWMB is reversed and is provided to another SPST by inverter 803 The control input of switch S2, a switch terminal of this spst switch S2 coupled to node 802 and Another switch terminal coupled to GND.Node 802 produces duty cycle signals D2, this duty cycle signals D2 is provided to one end of resistor R2, and the other end of resistor R2 coupled to node 804.Electric capacity Device C2 is coupling between node 804 and GND.The voltage of R2 and C2 together shape paired node 802 The RC wave filter being averaging.

Function value D T based on PWMB from effect by S1 and S2 that PWMB controls_SW Repeatedly trigger value VIN/LO from amplifier 801, form dutycycle letter with result based on equation (7) Number D2.The voltage of D2 is averaging and thus forms voltage V 804 by RC wave filter_{I_P-P_RIPPLE} (V_{I_P-P_ ripple}), this voltage V_{I_P-P_RIPPLE}The electric current I of equation (7) is followed in instruction_{P-P_RIPPLE}。

Fig. 9 is according to for forming V_{I_VCL}The valley current current limited generator of the exemplary embodiment of voltage The simplified block diagram of 407.In this case, V_{I_VCL}Voltage is not fixing, but alterable is to repair The operation of positively-modulated device 103, thus obtain substantially invariable peak current current limliting level and at current limitation Operation stable under state.Valley current current limited generator 407 includes peak current switching network 901 and paddy Current timing switching network 903.

Peak current switching network 901 forms voltage V_{I_PEAKM}, this voltage V_{I_PEAKM}The instruction side of following The peak current current limliting level I of journey (6)_PEAKM.Peak current switching network 901 receives by rate conversion network 600 V formed_VO/VIN, and additionally reception has indicating predetermined maximum IO_MAXThe voltage of level V_{IO_MAX}.In one embodiment, peak current switching network 901 is by these values and suitable yield value Combine to obtain the I following equation (6)_PEAKMThe Part I of value.As it can be seen, combiner 910 (example Such as multiplier) by V_VO/VINAnd V_{IO_MAX}It is multiplied.Although not shown, result can include suitable gain Value.Voltage V_{I_P-P_RIPPLE}Being also supplied to the input of peak current switching network 901, it will V_{I_P-P_RIPPLE}It is multiplied by a suitable yield value (such as GP) to obtain the I following equation (6)_PEAKM? Two parts.As it can be seen, another combiner 912 is by V_{I_P-P_RIPPLE}(wherein GP can wrap to be multiplied by GP Include 0.5 factor shown in equation (6)).Two values are added together to by peak current switching network 901 Its outlet side provides V_{I_PEAKM}Voltage, this V_{I_PEAKM}Voltage instruction peak current current limliting level I_PEAKM。 As it can be seen, another combiner 914 (such as adder) output of combiner 910,912 is added with VI_PEAKM voltage is formed at its outlet side.

Valley current timing switching network 903 receives V_{I_PEAKM}Voltage, voltage VIN/LO are (such as from putting The output of big device or its a certain version) and CLK signal to form valley current current limliting electricity at its outlet side Pressure V_{I_VCL}.As previously described, valley current limit voltage V_{I_VCL}It is provided to LVS device 403 To form valley voltage V_{I_VAL}, this valley voltage V_{I_VAL}There is V_COMPAnd V_{I_VCL}In smaller value Voltage level.

For boost converter, including operation bust-boost converter 102 under boost mode, electricity Sensor electric current is (by V_ISENRepresenting) upwards switching rate di/dt during Q4 switch conduction depends on defeated Entering the inductance LO of voltage VIN and inducer 209, this follows equation below (8):

$\frac{di}{dt}=\frac{VIN}{LO}---\left(8\right)$

Have determined that valley current current limliting level I_VCLShould switching rate based on inductor current be adjusted And by maximum peak current level I_PEAKMLimit.Therefore, equation below (9) can be followed and determine paddy electricity Ductility limit stream level I_VCL:

$I_{VCL}=I_{PEAKM}-\frac{di}{dt}{t}_{ON}---\left(9\right)$

Wherein " tON " can be considered the ON time between the pulse of CLK signal.Value tON can be by really It is set to the clk cycle T adjusted by the time " t "_SW, it is passed to T from 0 at each clk cycle_SW Or t_ON=T_SW-t.In this case, t_ONIt is that each circulation to CLK is from T_SWTiltedly fade to 0 Periodic ramp signal.So, based on equation (8), (9) and replace t_ON, can be according to equation below (10) valley current current limliting level IVCL is determined:

$I_{VCL}=I_{PEAKM}-\frac{VIN}{LO}(T_{SW}-t)---\left(10\right)$

For each cycle of CLK from 0 to T_SWTime t.Those skilled in that art are by this Waveform takes the version compensating ramp signal of the current limitation operation causing stable (without subharmonic) as. As previously mentioned, maximum peak current level I_PEAKMBy V_{I_PEAKM}Voltage indicates, this V_{I_PEAKM} Voltage is provided by peak current switching network 901.Therefore, equation (10) can be rewritten into equation below (11):

$V_{I\_VCL}=V_{I\_PEAKM}-\frac{VIN}{LO}(T_{SW}-t)G_R---\left(11\right)$

Wherein GR is suitable resistive yield value.Valley current timing switching network 903 receives V_{I_PEAKM} Voltage, voltage V_IN/LOAnd CLK signal forms valley current limit to follow equation (11) at its outlet side Stream voltage V_{I_VCL}。

In a shown embodiment, such as CLK is provided to timing block 916, this timing block 916 produce and the item G in equation (11)_R(T_SW-t) corresponding ramp signal.The output of timing block 916 will Ramp signal is supplied to the input of combiner 918 (such as multiplier), and multiplier 918 is multiplied by G_R It is provided to one of another combiner 920 (such as adder) input to obtain with being multiplied by VIN/LO The Section 2 of equation (11).V_{I_PEAKM}Voltage is provided to another input of combiner 920, this combination Device 920 is from V_{I_PEAKM}In deduct the output of combiner 918 to provide V at its outlet side_{I_VCL}。

Figure 10 is to draw V_{I_VCL}Circulation relative to from 0 to T_SWThe sequential chart of time t.When When pulse occurs in CLK, time t is reset to 0 so that V_{I_VCL}With minimum value MIN=V_{I_PEAKM}- (VIN·T_SW·G_R)/LO starts each circulation.T is towards T over time_SWDuring passage, Section 2 diminishes And V_{I_VCL}Towards V_{I_PEAKM}Tiltedly become.Work as t=T_SWTime, Section 2 is zero, and V_{I_VCL}Become It is substantially equal to V_{I_PEAKM}Voltage.Next pulse of CLK is by V_{I_VCL}Reset back MIN and operate weight Multiple.It is noted that MIN can not be fixed value, it can be along with V on the contrary_{I_PEAKM}Voltage and adjust and The change of VIN and change.

Figure 11 is the sequential chart similar to Fig. 5, and it illustrates that the staged in response to output loading increases The operation of transducer 102 and substantially assert by valley current current limited generator 407 in accordance with equation (11) V_{I_VCL}.CLK signal and V_{I_VCL}、V_ISEN、V_COMPAnd V_{I_VAL}Voltage is to paint relative to the time Go out.V_{I_VCL}It is illustrated as, between CLK circulates, there is the repetitive pattern being similar to shown in Figure 10, Rather than fixed waveform (such as V as shown in Figure 5_{I_VCL}(fixing)).At V_COMPKeep below V_{I_VCL} While, operate until time t5 is similar, wherein V_{I_VAL}Follow the tracks of V_COMP.Work as V_COMP When increasing in response to the load ladder at time t5, V_{I_VAL}Continue to follow the tracks of V_COMP, until it Whenabouts t6 and V_{I_VCL}Till Xiang Jiaoing.At time t6, the pulse of CLK signal makes V_{I_VCL}Multiple Position is the lowest, V simultaneously_COMPContinue to rise.Thus, V_{I_VAL}Switching is to follow the tracks of V_{I_VCL}And at V_{I_VCL} Less than V_COMPShi Jixu do so.For the cycles left of diagram, V_{I_VAL}Maintain V_{I_VCL}Repeatedly Tiltedly time variant voltage.

At time t6, in response to the pulse of CLK, V_ISENStart in the way of same as shown in Figure 5 Become to declivity.But, in this case, at V_{I_VAL}After starting upward change after time t6, At time t7, V_ISENWith V_{I_VAL}Intersect.V_ISENUntil time t8 cycles left substantially with Track V_{I_VAL}, wherein V_ISENAnd V_{I_VAL}Both reach V_{I_PEAKM}Essentially identical peak level, this electricity Put down and be illustrated as less than V_COMP.At time t8, V_{I_VAL}Reset returns to V_{I_VCL}Minima and open subsequently Begin the most tiltedly to become, and V_ISENThen start to become to declivity.V_ISENAt time t9 and V_{I_VAL}Intersect And change back to about V time t10 is the most upward subsequently_{I_PEAKM}.Operation repeats by this way, V simultaneously_{I_VAL}Remain less than V_COMP。

It should be noted that the peak current level flowing through inducer 209 is limited in about as shown in figure 11 I_PEAKM, this level is less than passing through V_{I_VCL}Fixed value or V as shown in Figure 5_{I_VCL}(fixing) obtains Peak value.I_PEAKMBe based on as previously mentioned to output current limitation predetermined value, thus inducer 209 can be the least physical size and relatively low cost realize, simultaneously still can obtain the defeated of requirement Going out electric current, that avoids in operating process is saturated simultaneously.Additionally, obtain the peak current current limliting of relative constancy Level, thus operation is stable and does not has subharmonic oscillation.Stable operation avoid blood pressure lowering-liter The false triggering being press-fitted between the buck and boost modes in putting.

Current limitation scheme described herein is equally applicable to any kind of peak current Schema control and turns Parallel operation, including the step-down controller, boost converter and the buck-boost that use crest stream mode to control Transducer.In peak current Schema control, power switch turns in each clock pulses and works as peak current Arrive error amplifier output V_COMPOr instruction inductor current limit value I_LIMIT(I_{Current limliting}) peak current Limit voltage V_{I_LIMIT}Time be cut off.Shown dutycycle by the transducer of peak current Schema control to be higher than The subharmonic oscillation of 50%.This can by compensation ramp signal is added to current sense waveform (or from VCOMP or derive from current limitation threshold voltage) avoid.As previously mentioned, by paddy electricity Under the background of the boost converter of flow control, the subharmonic oscillation in current limitation is the most desired.So And, compensate the application on slope, despite being beneficial to eliminate sub-harmonic oscillation, compare required peak point current meeting Reduce peak point current.Needing to produce the peak current cut-off current being corrected, this causes including compensation slope The transducer controlled by peak current in be in the substantially invariable stable peaks current limit of design load.

Figure 12 be illustrate be configured to peak current Schema control transducer and simultaneously response output loading with Constant current cut-off current V_{I_LIMIT (fixes)}The transducer 102 that works in buck mode of staged increase The sequential chart of operation.CLK signal and V_{I_LIMIT (fixes)}(V_{I_ current limliting (is fixed)})、V_{IO_MAX}、V_COMP And V_ISENVoltage was drawn relative to the time, wherein V_{I_LIMIT (fixes)}Voltage represents in fixed current limit I under stream level_LIMIT(I_{Current limliting}) current limitation signal.V_ISENIn time t1 response CLK pulse Rise, until it arrives V at time t2_COMPTill, V subsequently_ISENDecline, until time t3's Till next clock pulse.Equally at whenabouts t3, applying load ladder at outlet side, this makes VO Decline and responsively make V_COMPMake corresponding rising.V_COMPRise above V_{I_LIMIT (fixes)}Voltage. V_ISENSame rise after time t3 and in remaining circulation not with V_COMPIntersect, because V_COMP Have risen to higher than V_{I_LIMIT (fixes)}Voltage.On the contrary, V_ISENV is arrived at time t4_{I_LIMIT (fixes)}And with After after time t4 reduce, even if next CLK pulse occurs.V_ISENDecrease up at time t5 Next CLK pulse, rise subsequently, until at this circulation time t6 and V later_{I_LIMIT (fixes)} Till voltage intersects.V_ISENDecline after time t 6, but the most quickly to time t7, under Till one CLK pulse just occurs.V_ISENAgain rise, but quickly at time t8 and V_{I_LIMIT (Gu Fixed)}Voltage intersects, and subsequently in the remainder reduction of this circulation.Operation continues, such as time t9 and t10 As shown in.

Figure 12 is shown with constant current cut-off current (V_{I_LIMIT (fixes)}Voltage) additionally asking of may causing Topic.When dutycycle rises above about 50%, fixed current cut-off current may cause first harmonic to shake Swing, this subharmonic oscillation have a longer pulse followed by with relatively short pulse rush, as time t5 and t9 it Between figure shown in.This also causes average output current to be less than required electric current.

Figure 13 is to illustrate comprise compensation ramp signal and can be used to overcome and be configured to peak current pattern control Transducer processed the current limitation of the subharmonic oscillation of transducer 102 simultaneously worked in buck mode Voltage V_{I_LIMIT}One circulation sequential chart.V_{I_LIMIT}Minima be V_{IO_MAX}, it is instruction The voltage of the maximum output current required.The inductor current ripple with D～0 is of about VO·T_SW/ LO, and V_{I_LIMIT}Crest level V_{I_LIMIT_P}It is in compliance with what equation below (12) determined:

$V_{I\_LIMIT\_P}=V_{IO\_MAX}+\frac{VO\·T_{SW}\·G_R}{2\·LO}---\left(12\right)$

Wherein ramp value be the inductor current sensed during PWM=0 switching rate one Half.The same way that ramp value during each circulation can describe before is formed, wherein T_SWBy T_SW-t Replacing, wherein the time " t " passs to T from 0 during each clk cycle circulates_SW。

Figure 14 is to illustrate to comprise ramp signal and can be used to overcome and be configured to Controlled in Current Mode and Based and turn Parallel operation the electricity of the fixed current current limliting level problem of transducer 102 being simultaneously operated under boost mode Stream limit voltage V_{I_LIMIT}(V_{I_ current limliting}) one circulation sequential chart.Electric current for boost operations limits Stream voltage V_{I_LIMIT}Essentially identical, except based on input voltage VIN rather than based on output voltage VO. It addition, V_{I_LIMIT}Minima be V_{IO_MAX}, it is the maximum that instruction requires during boost mode The voltage of output electric current.The inductor current ripple with D～1 is of about VIN T_SW/ LO, and V_{I_LIMIT}Peak level V_{I_LIMIT_P}It is in compliance with what equation below (13) determined:

$V_{I\_LIMIT\_P}=V_{IO\_MAX}+\frac{VIN\·T_{SW}\·G_R}{2\·LO}---\left(13\right)$

Wherein ramp value be the inductor current sensed during PWM=1 switching rate one Half.Equally, the same way that the ramp value during each circulation can describe before is formed, wherein T_SW By T_SW-t replaces, and wherein the time " t " passs to T from 0 during each clk cycle circulates_SW。

Figure 15 is analogous to the sequential chart of Figure 12, and it illustrates and is configured to the conversion of peak current Schema control Device the staged increase in response to the output loading at about t3 are operated under buck or boost pattern Peak current pattern also has and the most substantially follows equation (12) and substantially abide by under boost mode Follow the V of equation (13)_{I_LIMIT}The operation of transducer 102.CLK signal and V_{I_LIMT}、V_{IO_MAX}、 V_COMPAnd V_ISENVoltage was drawn relative to the time.V_{I_LIMIT}It is illustrated as between CLK circulates Have and be similar to the repetitive pattern shown in Figure 13 or Figure 14 rather than fixed waveform as shown in figure 12 (such as V_{I_LIMIT (fixes)})。

When the staged of output loading increases beginning, operation is until time t3 is similar.Instruction The V of inductor current_ISENVoltage rises, but when it arrives the V that forward declivity becomes_{I_LIMIT}Time in the time T4 terminated in the time earlier of circulating.V_ISENVoltage upset also becomes to declivity, until next CLK arteries and veins Till the time t5 of punching, the most tiltedly become.At time t6, V_ISENAgain become with forward declivity V_{I_LIMIT}Intersect and overturn again to become to declivity.At next CLK pulse of time t7, V_ISEN Start again to rise.Operation repeats the most in an identical manner, V simultaneously_COMPIt is kept above V_{I_LIMIT}, wherein V_ISENAlong with each CLK pulse rises and works as and V_{I_LIMIT}The most tiltedly become version Decline when intersecting.V_{IO_MAX}Being maximum average inductor current, it is equal under step-down controller situation Maximum output current (corresponding to being in the maximum load current under steady state operation).

Figure 16 is to replace manipulator 103 with to the conversion being configured to peak current Schema control transducer The blood pressure lowering mode of operation of device 102 and boost operating mode form PWMA and PWMB pulse control The simplified block diagram of a part for the manipulator 1603 of signal processed.V_COMPCan shape in a substantially similar manner Become the outlet side at error amplifier 401.Valley current current limited generator 407 is limited by more generally electric current Flow-generator 1607 replacement, this current limitation generator 1607 is according to being indicated by mode signal MD Operator scheme (buck or boost) is followed equation (12) or (13) and is formed V at its outlet side_{I_LIMIT}Voltage. V_{IO_MAX}With the corresponding input that VIN/LO is provided to current limitation generator 1607.Also can carry For value K VO/LO, the mode that this value can be identical with the VIN/LO described before is formed.Value K VO Can be VFB or another value of instruction output voltage VO.It addition, CLK and MD can be by each Input be provided to current limitation generator 1607.Current limitation generator 1607 uses and pin before The technology of the basic simlarity that valley current current limited generator 407 describes is produced V_{I_LIMIT}Voltage, wherein V_{I_LIMIT}Decompression mode is followed equation (12) and boost mode is followed equation (13) and is formed by voltage.

LVS device 403 is provided and receives V at its input side_COMPAnd V_{I_LIMIT}, and defeated at it Go out side formation value V_{I_LIM}。V_{I_LIM}It is V_COMPAnd V_{I_LIMIT}In smaller value and be provided to compare Device 1605.Comparator 1605 replacement comparator 405 also can be used to being configured to peak current pattern control The bust-boost converter 102 of transducer processed for decompression mode and boost mode formed PWMA and PWMB signal.As those skilled in the art understand, at the electricity controlled by peak current In stream mode transducer, it is possible to by the maximum of the output voltage VCOMP of restraining error amplifier Reach current limitation rather than use single current limitation comparator and LVS circuit.The present invention The most also can be by by V_COMPMaximum be limited in V_{I_LIMIT_P}(V_{I_ current limliting _ P}) and will The negative trend slope of Figure 13 (under blood pressure lowering situation) or Figure 14 (under boosting situation) adds to V_COMPVoltage Realize.

Although with reference to specific embodiment, invention has been described, but the content be given is to make Make those skilled in the art can make under the background of application-specific and demand thereof and use the present invention.Many Plant to revise and change and be apparent to one of ordinary skill in the art, without departing from such as institute The scope of the present invention described in attached claims.Therefore, specification and drawings should be considered explanation Property and non-limiting, and this type of amendments all are intended within the scope of the present invention.Herein for spy Determine the solution of any interests, advantage or problem that embodiment describes be not intended to be interpreted arbitrary or The all key of claim, indispensable or required feature or key elements.Unless otherwise stated, such as " the One " and the term of " second " is used between the key element of these term descriptions optionally make difference.Cause This, these terms are not necessarily intended to represent the Time priority of these key elements or other priority.

Claims (20)

1. include that a manipulator for current limitation scheme, described manipulator are configured to input Voltage controls to flow through the inducer of transducer according to described current limitation scheme while being converted into output voltage The switching of electric current, described manipulator includes:

Current limitation generator, is configured to based on selected in described input voltage and described output voltage One and be based further on the inductance of described inducer of described transducer, timing signal and predetermined maximum defeated Go out electric current and the most tiltedly time-dependent current cut-off current is provided；And

Comparator network, is configured to the current sense value of electric current by instruction is flow through described inducer Compare with the value including less in compensation error amount and described periodicity oblique time-dependent current cut-off current one And provide switch controlling signal to control to flow through the switching of the electric current of described inducer.

2. manipulator as claimed in claim 1, it is characterised in that described current limitation generator Including the valley current current limited generator for boost operations pattern, wherein said valley current current limited generator bag Include:

Valley current timing switching network, be configured to based on described input voltage, the inductance of described inducer, The peak current limit value of described timing signal and described inducer provides described periodicity oblique time-dependent current cut-off current, its Described in peak current limit value described predetermined maximum output current based on described transducer；

Peak current switching network, is configured to based on described output voltage and described input voltage ratio, institute State predetermined maximum output current and flow through the peak-to-peak ripple electric current of described inducer to provide peak current current limliting Value；And

Described peak current cut-off current indicates the described peak current limit value of described inducer and is used to make described week Phase property oblique time-dependent current cut-off current is as valley current cut-off current.

3. manipulator as claimed in claim 2, it is characterised in that described peak current switching network Including:

First combiner, is configured to yield value and the peak-to-peak ripple value indicating described peak-to-peak ripple electric current It is multiplied to provide the first value indicated as it；

Second combiner, is configured to the ratio by indicating described output voltage and described input voltage ratio It is multiplied with the maximum current value indicating described predetermined maximum output current, second indicated as it using offer Value；And

3rd combiner, is configured to be added to provide described peak electricity by described first value and described second value Ductility limit flow valuve.

4. manipulator as claimed in claim 2, it is characterised in that also include rate conversion network, Including:

Ramp generator, is configured to be formed the most tiltedly based on described input voltage and described timing signal Slope signal；

Comparator, is configured to described periodic ramp signal and the output valve indicating described output voltage Compare the duty cycle signals indicated using offer as it；And

Wave filter, is configured to that described duty cycle signals is converted into the described output voltage of instruction defeated with described Enter the ratio of the ratio of voltage.

5. manipulator as claimed in claim 4, it is characterised in that described periodic ramp signal Represent the inductor current when inducer is coupling between described input voltage and power reference voltage.

6. manipulator as claimed in claim 2, it is characterised in that also include ripple switching network, Including:

Amplifier, is configured to the value by indicating described input voltage divided by the inductance indicating described inducer Value to provide ripple quantity；

On-off circuit, is configured to use described switch controlling signal repeatedly to trigger described ripple quantity to be formed The duty cycle signals of the peak-to-peak ripple electric current of described inducer is flow through in instruction；And

Wave filter, is configured to be converted into described duty cycle signals described peak-to-peak ripple value.

7. manipulator as claimed in claim 2, it is characterised in that described valley current timing conversion Network includes:

Timing circuit, is configured to switching cycle based on described timing signal and is changed by described timing signal Become there is the periodic ramp signal of peak level；

First combiner, be configured to be multiplied by described periodic ramp signal the described input voltage of instruction with The ratio of the ratio of the inductance of described inducer and be multiplied by that a yield value indicates using offer as it first Value；And

Second combiner, is configured to the peak current limit from the described peak current limit value indicating described inducer Flow valuve deducts described first value to provide described periodicity oblique time-dependent current cut-off current.

8. manipulator as claimed in claim 1, it is characterised in that also include:

Error amplifier, is configured to provide the described compensation error amount indicating described output voltage error； And

Smaller value selector, is configured to determine and includes that described compensation error amount and described periodicity tiltedly become The selected current limitation value that the value of less in current limitation value one indicates using offer as it.

9. manipulator as claimed in claim 1, it is characterised in that described transducer is configured to Work as the boost converter by peak current Schema control, and described current limitation generator is configured to Described input voltage based on described transducer, the inductance of described inducer, described timing signal and predetermined Maximum output current provides described periodicity oblique time-dependent current cut-off current.

10. manipulator as claimed in claim 1, it is characterised in that described transducer is configured to As peak current Schema control step-down controller work, and described current limitation generator be configured to based on The described output voltage of described transducer, the inductance of described inducer, described timing signal and described predetermined Maximum output current provides described periodicity oblique time-dependent current cut-off current.

11. 1 kinds of electronic equipments including current limitation scheme, including:

Transducer, including:

Inducer；

Coupled to the on-off circuit of described inducer, be configured to switch the electric current flowing through described inducer with Based on the first switch controlling signal, input voltage is converted into output voltage；And

According to the manipulator of described current limitation arrangements, including:

Current limitation generator, is configured to the input value and instruction based on indicating described input voltage described Selected in the output valve of output voltage one and be based further on the electricity of described inducer of described transducer Sense, clock signal and predetermined maximum output current provide the most tiltedly time-dependent current cut-off current；And

Comparator network, is configured to the current sense value of electric current by instruction is flow through described inducer Compare with the value including less in compensation error amount and described periodicity oblique time-dependent current cut-off current one And described first switch controlling signal is provided.

12. electronic equipments as claimed in claim 11, it is characterised in that also include coupleding to described The processor of transducer and memorizer.

13. electronic equipments as claimed in claim 11, it is characterised in that described current limitation occurs Device includes the valley current current limited generator for boost operations pattern, wherein said valley current current limited generator bag Include:

Valley current timing switching network, be configured to based on described input value, the inductance of described inducer, The peak current limit value of described clock signal and described inducer provides described periodicity oblique time-dependent current cut-off current, its Described in peak current limit value described predetermined maximum output current based on described transducer；

Peak current switching network, is configured to based on described output voltage and described input voltage ratio, institute State predetermined maximum output current and the peak-to-peak ripple value of peak-to-peak ripple electric current of described inducer is flow through in instruction Described peak current limit value is provided.

14. electronic equipments as claimed in claim 13, it is characterised in that also include switching network, It is configured to by indicate described output voltage described output valve with indicate described clock signal circulation it Between the ramp signal of described input voltage make comparisons to produce periodically rate signal, and be configured to institute State periodically rate signal to filter to provide the ratio of described output voltage and described input voltage ratio through RC Value.

15. electronic equipments as claimed in claim 13, it is characterised in that also include switching network, It is configured to the value by indicating described input voltage divided by indicating the value of inductance of described inducer to provide ripple Stricture of vagina value, is configured to repeatedly trigger described ripple quantity to be formed periodically by described first switch controlling signal Ripple signal, and be configured described periodic dimple signal is filtered through RC to provide described peak-to-peak ripple Value.

16. electronic equipments as claimed in claim 11, it is characterised in that described transducer is configured Become and work as peak current Schema control boost converter, and described current limitation generator is configured to base In the described input voltage of described transducer, the inductance of described inducer, described clock signal and described pre- Determine maximum output current and described periodicity oblique time-dependent current cut-off current is provided.

17. electronic equipments as claimed in claim 11, it is characterised in that described transducer is configured Become and work as peak current Schema control step-down controller, and described current limitation generator is configured to base In the described output valve of described transducer, the inductance of described inducer, described clock signal and described predetermined Maximum output current provides described periodicity oblique time-dependent current cut-off current.

The side of 18. 1 kinds of current limitations being configured to the inducer flowing through the transducer controlled by electric current Method, input voltage is converted into output voltage by the described transducer controlled by electric current, and described method includes:

Receive the current sense value that the electric current of described inducer is flow through in instruction；

Receive the compensation of error value indicating described output voltage；

Based on one selected in described output voltage and described input voltage and be based further on described conversion The inductance of described inducer of device, clock signal and predetermined maximum output current form the most tiltedly power transformation Ductility limit flow valuve；

Determine what the smaller in described offset and described periodicity oblique time-dependent current cut-off current selected with offer Current limitation value；And

Use described clock signal and by described selected current limitation value being made with described current sense value Relatively provide switch controlling signal to control to flow through the switching of the electric current of described inducer.

19. methods as claimed in claim 18, it is characterised in that described formation the most tiltedly power transformation Ductility limit flow valuve includes described input voltage based on described transducer, the inductance of described inducer, described clock Signal and described predetermined maximum output current form the most tiltedly time-dependent current cut-off current.

20. methods as claimed in claim 18, it is characterised in that described formation the most tiltedly power transformation Ductility limit flow valuve includes described output voltage based on described transducer, the inductance of described inducer, described clock Signal and described predetermined maximum output current form the most tiltedly time-dependent current cut-off current.