CN103928903A - Self-recovery fault treatment circuit - Google Patents
Self-recovery fault treatment circuit Download PDFInfo
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- CN103928903A CN103928903A CN201310007724.4A CN201310007724A CN103928903A CN 103928903 A CN103928903 A CN 103928903A CN 201310007724 A CN201310007724 A CN 201310007724A CN 103928903 A CN103928903 A CN 103928903A
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- fault
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- flop
- door
- logic circuits
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Abstract
The invention discloses a self-recovery fault treatment circuit, which comprises a fault trigger circuit, a fault treatment circuit, an OR circuit and a D-type trigger. One input of the OR door is output of the fault trigger circuit, and the other input of the OR door is a first signal source. The output of the OR door is connected with a CK end of the D-type trigger. A second signal source is connected with a D end of the D-type trigger. The S end and the R end of the D-type trigger are respectively grounded. The Q end of the D-type trigger is connected with the input end of the fault treatment circuit. The self-recovery fault treatment circuit aims to provide the self-recovery fault treatment circuit which has an advantage of simple design. When a fault occurs, hardware is firstly locked for performing a function of protecting the hardware preferentially. After the fault is eliminated, the locked state of the hardware can be automatically eliminated.
Description
Technical field
The present invention relates to a kind of from recovering fault logic circuits.
Background technology
At present; on concentrated combining inverter master control borad; disturb, when the fault such as overcurrent, overvoltage, short circuit; fault circuits for triggering can directly trigger fault logic circuits and go handling failure; hardware precedence is not entered to row lock protection; also cannot ensure under software systems condition out of control positive lock hardware circuit.
Summary of the invention
The object of the present invention is to provide a kind of from recovering fault logic circuits; this circuit design is simple; in the time that fault occurs; locking hardware plays the effect of priority protection hardware; can ensure under software systems condition out of control; positive lock hardware circuit, after trouble shooting, can remove hardware lock state automatically.
The present invention is a kind of at least comprises master control controller, fault circuits for triggering, fault logic circuits from recovering fault logic circuits, also comprise or door and D flip-flop,
Master control controller, to described or door and D flip-flop send respectively first signal source, secondary signal source;
Fault circuits for triggering, produce fault start pulse signal and send to described or door;
Or door, the level value in the fault start pulse signal receiving and first signal source is compared to processing, the pulse voltage signal after transmission processing is to D flip-flop;
D flip-flop, compares processing by the level value in the pulse voltage signal receiving and secondary signal source, sends low level signal to fault logic circuits;
Fault logic circuits, handles it and sends fault message according to the low level signal receiving, and system receives this information and carries out troubleshooting.
Preferably, an output that is input as fault circuits for triggering of described or door, or door another be input as first signal source, or the output of door and the CK end of D flip-flop are connected, secondary signal source is connected with the D end of D flip-flop, S end and the R of D flip-flop hold equal ground connection, and the Q end of D flip-flop is connected with the input of fault logic circuits; .
Preferably, the Q of described D flip-flop end is also in series with light-emitting diode, resistance and power supply (VCC) successively.
The present invention is a kind of from recovering fault logic circuits, when system power-up initializing, first signal source output low level, secondary signal source output high level, postpone after the t1 time, first signal source port produces a set pulse, and at the rising edge place (t1 moment) of pulse, trigger output Q becomes high level (regardless of state before it).Rising edge after t2 time delay, secondary signal source port output low level.After this, fault logic circuits enters standby condition, waits pending fault to produce.
When a certain moment, fault circuits for triggering produce fault trigger impulse, and trigger impulse is that high level is effective.Because the normality in first signal source is low level, therefore or the output of door determined by the output of fault circuits for triggering completely, will there is the impulse form identical with the output of fault circuits for triggering in CK end.Now, because the D end of trigger is low level, after the rising edge of fault trigger impulse occurs, the Q output of trigger is forced to low level, this low level signal will provide fault message input to fault processing system, carry out dependent failure process operation by troubleshooting software.Carry out in failed operation process at fault processing system, except nonsystematic is carried out initialization operation, otherwise this low level signal will be in the lock state always.This function can ensure under software systems condition out of control, positive lock hardware circuit.
When fault processing system completes after the processing operation of fault, automatically perform failure recovery operation program (operation of carrying out during with said system power-up initializing is consistent), after carrying out, fault logic circuits, again in standby condition, is waited for the appearance of next fault.
The present invention is a kind of has played the effect of protection hardware from recovering fault logic circuits preferential locking hardware in the time that fault occurs, and can automatically solve hardware lock after trouble shooting.
Below in conjunction with drawings and Examples in detail the present invention is described in detail.
Brief description of the drawings
Fig. 1 is that the present invention is a kind of from recovering fault logic circuits schematic diagram;
Fig. 2 is that the present invention is a kind of from recovering fault logic circuits failure response and automatically removing working waveform figure.
Embodiment
Referring to Fig. 1 and Fig. 2, one of the present invention, from recovering fault logic circuits, is applicable to concentrated combining inverter master control borad, at least comprises master control controller, fault circuits for triggering, fault logic circuits, also comprise or door and D flip-flop,
Master control controller, to described or door and D flip-flop send respectively first signal source, secondary signal source;
Fault circuits for triggering, produce fault start pulse signal and send to described or door;
Or door, the level value in the fault start pulse signal receiving and first signal source is compared to processing, the pulse voltage signal after transmission processing is to D flip-flop;
D flip-flop, compares processing by the level value in the pulse voltage signal receiving and secondary signal source, sends low level signal to fault logic circuits;
Fault logic circuits, handles it and sends fault message according to the low level signal receiving, and system receives this information and carries out troubleshooting.
An output 3 that is input as fault circuits for triggering of described or door, or door another be input as first signal source 2, or the output of door and the CK end of D flip-flop are connected, secondary signal source 1 is connected with the D end of D flip-flop, S end and the R of D flip-flop hold equal ground connection, and the Q end of D flip-flop is connected with the input of fault logic circuits.
The Q end of D flip-flop is also in series with light-emitting diode 4, resistance 5 and power supply VCC successively.
Failure response and software reset's principle are as follows:
1) fault logic circuits initialization
Referring to Fig. 2, after system powers on, master control system control signal source port output low level, secondary signal source port output high level.Postpone after the t1 time, first signal source port produces a set pulse, and at the rising edge place (t1 moment) of pulse, trigger output Q becomes high level (regardless of state before it).Rising edge after t2 time delay, secondary signal source port output low level.After this, fault logic circuits enters standby condition, waits pending fault to produce.
2) fault locking
When a certain moment, as t3 in Fig. 2, fault circuits for triggering produce fault trigger impulse, and trigger impulse is that high level is effective.Because the normality in first signal source is low level, therefore or the output of door determined by the output of fault circuits for triggering completely, will there is the impulse form identical with the output of fault circuits for triggering in CK end.Now, because the D end of trigger is low level, after the rising edge of fault trigger impulse occurs, the Q output of trigger is forced to low level, this low level signal will provide fault message input to fault processing system, carry out dependent failure process operation by troubleshooting software.Carry out in failed operation process at fault processing system, except nonsystematic carry out as 1) described in failure recovery operation, otherwise this low level signal will be in the lock state always.This function can ensure under software systems condition out of control, positive lock hardware circuit.
3) fault logic circuits is from recovering
When fault processing system completes after the processing operation of fault, automatically perform 1) described in failure recovery operation program, after carrying out, fault logic circuits, again in standby condition, is waited for the appearance of next fault.
So; the present invention is a kind of from recovering fault logic circuits; in the time that the faults such as interference, overcurrent, overvoltage, short circuit occur, preferential locking hardware utilizes software can initiatively remove hardware fault lock-out state after troubleshooting completes, and makes hardware protection possess auto restore facility.
Realize in essence hardware protection preferential, and can automatically realize hardware locking function under software condition out of control.
Can find out to only have software initiatively could realize the reset of fault locking circuit by controlling the state in first signal source and secondary signal source according to Fig. 2, under software condition out of control, fault locking circuit will keep lock-out state always.
Claims (3)
1. from recovering a fault logic circuits, at least comprise master control controller, fault circuits for triggering, fault logic circuits, it is characterized in that: also comprise or door and D flip-flop,
Master control controller, to described or door and D flip-flop send respectively first signal source, secondary signal source;
Fault circuits for triggering, produce fault start pulse signal and send to described or door;
Or door, the level value in the fault start pulse signal receiving and first signal source is compared to processing, the pulse voltage signal after transmission processing is to D flip-flop;
D flip-flop, compares processing by the level value in the pulse voltage signal receiving and secondary signal source, sends low level signal to fault logic circuits;
Fault logic circuits, handles it and sends fault message according to the low level signal receiving, and system receives this information and carries out troubleshooting.
2. according to claim 1 from recovering fault logic circuits, it is characterized in that, an output (3) that is input as fault circuits for triggering of described or door, or door another be input as first signal source (2), or the output of door and the CK end of D flip-flop are connected, secondary signal source (1) is connected with the D end of D flip-flop, and S end and the R of D flip-flop hold equal ground connection, and the Q end of D flip-flop is connected with the input of fault logic circuits.
3. one according to claim 1, from recovering fault logic circuits, is characterized in that: the Q end of D flip-flop is also in series with light-emitting diode (4), resistance (5) and power supply (VCC) successively.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310007724.4A CN103928903A (en) | 2013-01-10 | 2013-01-10 | Self-recovery fault treatment circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310007724.4A CN103928903A (en) | 2013-01-10 | 2013-01-10 | Self-recovery fault treatment circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN103928903A true CN103928903A (en) | 2014-07-16 |
Family
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201310007724.4A Pending CN103928903A (en) | 2013-01-10 | 2013-01-10 | Self-recovery fault treatment circuit |
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| CN (1) | CN103928903A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107741741A (en) * | 2017-10-23 | 2018-02-27 | 安徽栋霖电气有限公司 | A kind of multi input d type flip flop rest-set flip-flop electrical combination |
| CN108981554A (en) * | 2018-05-24 | 2018-12-11 | 河海大学 | The appearance coral formula displacement meter circuit and its method of probe absolute position can be identified after power supply |
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| CN201813147U (en) * | 2010-10-09 | 2011-04-27 | Bcd半导体制造有限公司 | Short circuit protection circuit of switching power |
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| CN102566640A (en) * | 2011-12-24 | 2012-07-11 | 西安启芯微电子有限公司 | Voltage-stabilizing circuit with hiccup mode over-current protection function |
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| US20060236182A1 (en) * | 2005-03-04 | 2006-10-19 | Tsinghua University | Scan-based self-test structure and method using weighted scan-enable signals |
| CN1901339A (en) * | 2006-07-21 | 2007-01-24 | 杭州中信网络自动化有限公司 | Digital fixed frequency anti-interference circuit |
| CN201813147U (en) * | 2010-10-09 | 2011-04-27 | Bcd半导体制造有限公司 | Short circuit protection circuit of switching power |
| CN202275321U (en) * | 2011-10-12 | 2012-06-13 | 国营红峰机械厂 | Fault diagnosis device for embedded system |
| CN102566640A (en) * | 2011-12-24 | 2012-07-11 | 西安启芯微电子有限公司 | Voltage-stabilizing circuit with hiccup mode over-current protection function |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107741741A (en) * | 2017-10-23 | 2018-02-27 | 安徽栋霖电气有限公司 | A kind of multi input d type flip flop rest-set flip-flop electrical combination |
| CN108981554A (en) * | 2018-05-24 | 2018-12-11 | 河海大学 | The appearance coral formula displacement meter circuit and its method of probe absolute position can be identified after power supply |
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Application publication date: 20140716 |