CN103928046A - Memory apparatus with decoding device and manufacturing method thereof - Google Patents
Memory apparatus with decoding device and manufacturing method thereof Download PDFInfo
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- CN103928046A CN103928046A CN201310015908.5A CN201310015908A CN103928046A CN 103928046 A CN103928046 A CN 103928046A CN 201310015908 A CN201310015908 A CN 201310015908A CN 103928046 A CN103928046 A CN 103928046A
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Abstract
The invention discloses a memory apparatus with decoding devices and a manufacturing method thereof, and the decoding devices are disposed in device levels separated by array levels. The memory apparatus possesses a memorizer array and a peripheral circuit, and the memorizer array is formed in the array levels; and the peripheral circuit comprises the decoding devices and other peripheral circuit, and is formed in the device levels. A storage unit array possesses an edge which defines pillars, and the pillars extend to the upward side and the downward side of the storage unit array. The decoding device and the other periphery circuit, or at least part of the decoding device and at least part of the other periphery circuit, are arranged in the pillars in the device level. The memory apparatus also comprises multiples pads in a pad level. A first multiple inter-level conductor wire is electrically coupled with the decoding device to bit lines and word lines in the storage unit array.
Description
Technical field
The invention relates to the structure of storage arrangement, relate to especially high density memory cells device and manufacture method thereof.
Background technology
Storage arrangement uses the storage unit being configured in array with storage data.See through the use of code translator, the enterprising line operate of specific storage unit in memory cell array, and wherein code translator is connected to word line and the bit line in array, the word line in array and bit line are supported by the peripheral circuit that is located at the outer peripheral areas that memory device is set up.In typical architecture of memory device, be configured in the area that has increased device adjacent to the code translator of memory cell array.In addition, other outer peripheral areas that configure near peripheral circuit code translator and memory cell array, have also increased the area installing.This structure is used at dissimilar storer, comprises the DRAM storer (volatileDRAM memory) and non-volatile NOR/NAND flash memory (non-volatileNOR/NAND Flash memory) of volatibility.
This kind of architecture of memory device has many shortcomings.First, the code translator of architecture of memory device and the peripheral circuit of outer peripheral areas are configured in memory cell array edge, thereby have very large taking up room.Very large the taking up room of architecture of memory device caused chip size to become large.
Moreover sort memory apparatus structure has the too high shortcoming of manufacturing cost.Conventionally, forming memory array required manufacturing step is different from and forms code translator and the required manufacturing step of peripheral circuit.Form the required manufacturing step of memory array, need complicated staggered flow process.
Therefore, provide a kind of very little architecture of memory device that takes up room to be expected.And also expect to provide a kind of architecture of memory device of low manufacturing cost.
Summary of the invention
The invention provides the structure for storage arrangement, and for the manufacture of the method for architecture of memory device.
This architecture of memory device comprises memory cell array, memory cell array is configured in array stratum, code translator and other circuit, memory cell array is arranged on the outer peripheral areas of the architecture of memory device of prior art conventionally, and memory cell array is configured in device stratum.Memory cell array can comprise that the lamination of two dimension (2D) memory cell array is to set up three-dimensional (3D) memory cell array.Device stratum configurable on array stratum or under.The edge of the memory cell array in array stratum has defined cylinder, and in device stratum, cylinder extends to define the region of cylinder inner side in the above and below of array.In one embodiment, code translator and partly or entirely other peripheral circuits be both arranged on completely in the cylinder in device stratum.In alternate embodiment, code translator can be arranged in the cylinder in device stratum at least partly.In other alternate embodiments, when another x-code translator or y-code translator are fully arranged on outside cylinder, x-code translator or both one of y-code translator are arranged in cylinder completely.
Memory cell array comprises bit line word line, and bit line word line is coupled to row and the row of the storage unit in array.One first many interlayer conductor wire electric property coupling bit lines and word line are to the code translator in device stratum.Interlayer conductor wire is included in array stratum and extends to cylinder inner side from cylinder outside and do the part contacting.Therefore, interlayer conductor wire is not passed in the memory cell array of column body position.
Architecture of memory device also can comprise pad stratum, and pad stratum comprises multiple pads in cylinder inner side.Pad can have contact area, and contact area is as I/O (I/O) contact, power supply supply contact, earthing power supply contact, data and address contact etc.At an embodiment, all pads are arranged in the cylinder in pad stratum.At another embodiment, the setting of pad, is located in the cylinder in pad stratum some pads of some pads or part partially or completely.Pad is electrically coupled to code translator and other circuit in device stratum via one second many interlayer conductor wires.More than second interlayer conductor wire is included in pad stratum, extends to the inner side of cylinder as the part of contact from the outside of cylinder.Consequently, more than second interlayer conductor wire do not pass through in the position of memory cell array in cylinder.
For there is to better understanding above-mentioned and other aspect of the present invention, special embodiment below, and coordinate appended graphicly, be described in detail below.
Brief description of the drawings
Fig. 1 illustrates the skeleton view of the architecture of memory device of a prior art, and memory array, x-code translator, y-code translator and other peripheral circuits of the architecture of memory device of prior art are all in same layer.
Fig. 2 A illustrates the decomposition diagram of an architecture of memory device, and the x-code translator of this architecture of memory device and y-code translator are below memory array.
Fig. 2 B illustrates the bottom layout figure of architecture of memory device as shown in Figure 2 A.
Fig. 3 A illustrates the decomposition diagram of an architecture of memory device, and the x-code translator of this architecture of memory device and y-code translator are all configured in the below of memory array.
Fig. 3 B illustrates the layout of architecture of memory device device stratum as shown in Figure 3A.
Fig. 4 A illustrates the decomposition diagram of another architecture of memory device, and the x-code translator of this architecture of memory device and y-code translator are all configured in the below of memory array.
Fig. 4 B illustrates the layout of architecture of memory device device stratum as shown in Figure 4 A.
Fig. 5 illustrates the layout of another architecture of memory device device stratum.
Fig. 6 illustrates the vertical view that is shown in top Shang Dian stratum of device stratum as Fig. 3 A and Fig. 3 B, the array stratum that omits architecture of memory device in figure.
Fig. 7 illustrates the simplification sectional view of architecture of memory device.
Fig. 8 A illustrates the calcspar of the circuit component of carrying out computing in memory cell array, and any numeral in figure or all circuit components are configurable in cylinder, and cylinder is defined by the edge of memory cell array.
Fig. 8 B illustrates the calcspar that pads as shown in Figure 8 A stratum above device stratum and array stratum.
[main element symbol description]
100,200,300,400,700: architecture of memory device
102,206,302,406,714: memory array
104,202,504,802a, 802b:x-code translator
106,204,506:y-code translator
108: peripheral circuit
110,112,208,210,310,312,314,316,408,410,412,414,620,622,630,634: side
212,214: whole length
216,328,436,718A, 724A: region
304,402,704: array stratum
306,404,500,702: device stratum
308,426,708: substrate
318,416,502,606,716: cylinder
320,322,324,326,418,420,422,424,428,430,432,434,602,604,608,610,616: part
612a, 612b, 612c, 612d, 726,832a-d: pad
614a, 614b, 614c, 614d: conductor wire region
618,624: width
626: length
628,632: distance
706,830: pad stratum
710,720,722: patterned polysilicon region
712: dielectric layer
718,724: interlayer conductor wire
800: edge
804a, 804b: page buffer
810: bus
812: Data In-Line
814: circuit
816: controller
818: piece
820a, 820b, 824a, 824b, 834a, 834b, 834c, 834d: line
822a, 822b, 826a, 826b, 836a, 836b, 836c, 836d: perpendicular interconnection section
Embodiment
Fig. 1 to Fig. 8 provides the detailed description of the embodiment of the present invention.
Fig. 1 illustrates the skeleton view of the architecture of memory device of a prior art, and memory array, x-code translator, y-code translator and other peripheral circuits of the architecture of memory device of this prior art are all in same layer.Storage arrangement 100 comprises memory array 102 and peripheral circuit, and peripheral circuit comprises x-code translator 104, y-code translator 106 and other peripheral circuits 108 in outer peripheral areas (peripheral region).Memory array 102, with the peripheral circuit that comprises x-code translator 104, y-code translator 106 and other peripheral circuits 108 all in same layer.Specifically, x-code translator 104 along side 110 adjacent to memory array 102.Y-code translator 106 along side 112 adjacent to memory array 102.Other peripheral circuits 108 are in the region adjacent to x-code translator 104 and y-code translator 106.Other peripheral circuits can comprise other circuit of carrying out computing in page buffer (page buffers), sensor circuit (sense circuitry), control circuit (control circuit), supply potential circuit (supplyvoltage circuitry) and any storage unit in memory cell array.In addition, another peripheral circuit can comprise that processor, special logic (special purposelogic), communication interface (communication interfaces) and other can be incorporated into the element on single-chip (single chip) with memory array.
Fig. 2 A illustrates the decomposition diagram of an architecture of memory device, and the x-code translator of this architecture of memory device and y-code translator are below memory array.Fig. 2 B illustrates the layout of architecture of memory device as shown in Figure 2 A.Architecture of memory device 200 as shown in Fig. 2 A and Fig. 2 B comprises the x-code translator 202 and y-code translator 204 that are arranged on memory array 206 belows.Y-code translator 204 is aligned in the first side 208 of cylinder, and the first side 208 of cylinder is defined by the edge of memory array 206.It is the circuit that comprises input node (input nodes) and output node (output nodes) based on the object of the invention x-code translator 202, input node is from address source (source of addresse) receiver address signal, output node directly connects the conductor (conductors) that comprises an individual word line in memory array, or output node is electrically coupled to the conductor being connected with in memory array individual word line.It is the circuit that comprises input node and output node based on the object of the invention y-code translator 204, input node is from address source (source of addresse) receiver address signal, and output node is connected directly to conductor and sends a signal to the row selecting switch (column select switches) of controlling for the indivedual bit lines in memory array.When being while being configured in cylinder completely at input node, output node, with inputting the circuit that transmits signal between node and output node, x-code translator is to be configured in completely in cylinder.When being while being configured in cylinder completely at input node, output node, with inputting the circuit that transmits signal between node and output node, y-code translator is to be configured in completely in cylinder.
Y-code translator forms the row selecting switch being connected to for bit line, the whole length 212 of its first side 208 that spreads all over memory array that can distribute in fact.For instance, can have the demand that is connected to the row selecting switch of each bit line of latch (latch on) from decoding output node, and in array each or the every storage unit indivedual bit lines of access as required of some row.This can cause the demand of the hundreds of or thousands of connections to bit line from peripheral circuit to array.
X-code translator 202 is aligned in the second side 210 of cylinder, and the second side 210 of cylinder is defined by the edge of memory array.X-code translator forms and is connected to word line, and word line also may thousands of in fact distributions strides across the whole length 214 of second side 210.If the mode be as shown in Figure 2 A arranged to extend across the x-code translator of the whole width of array 206 and length and whole y-code translator and be fully arranges the below of memory array, code translator or at least being connected between being connected between x-code translator and array (connection) and y-code translator and array will overlap in region 216 so.
Fig. 3 A illustrates the decomposition diagram of an architecture of memory device, and the x-code translator of this architecture of memory device and y-code translator are all configured in the below of memory array.Fig. 3 B illustrates the layout of architecture of memory device device stratum (device level) as shown in Figure 3A.Architecture of memory device 300 in Fig. 3 A comprises array stratum 304 and device stratum 306.As shown, device stratum 306 configurable below array stratum 304 or array stratum above.Device stratum 306 is formed on substrate 308.Array stratum comprises memory array 302.
Memory array can be thin film transistor (TFT) (TFT) memory array of lamination, and thin film transistor (TFT) memory array is separated from device stratum by interlayer dielectric layer (not illustrating).The thin film transistor (TFT) memory array of the lamination of example has disclosed the United States Patent (USP) 7 for " Thin Film Transistor; Non-Volatile Memory Device and Methods forFabricating the Same " at title with the method for the thin film transistor (TFT) memory array of manufacturing lamination, 473, in No. 589B2, this patent is included into reference at this, as fully set forth.Particularly, memory array can comprise multilayer bit line layer.Particularly, in the thin film transistor (TFT) memory array example of a lamination, each storage unit lamination comprises bit line layer, word line electric conductor and catches layer, and seizure layer is between bit line layer and word line electric conductor.Bit line layer is a film, and bit line layer comprises territory, multiple source/drain pole region and channel region.The structure obtaining is the thin film transistor (TFT) memory array organization of lamination.
Memory array 302 has first side 310, second side 310, the 3rd side 314 and four side 316.The opposition side of 310 second side, first side 310, and the 3rd side 314 opposition sides at four side 316.The edge of side 310,312,314 and 316 define storage arrays.The edge definition cylinder 318 (being illustrated by the broken lines) of memory array, and cylinder 318 above memory cell array with below two sides extend.
Cylinder is with the projection definition of the two-dimensional curve (two-dimensional curve) of a sealing, as being the edge of memory array in this example, along the axis that intersects (intersects) plane, and whole two-dimensional closed curve planar.The edge of the two-dimensional curve of definition can be square (square), rectangle (rectangle), circular (circle), oval (ellipse) or depends on the irregular a little shape of manufacture process.For the object of simplifying, two-dimensional curve represents with square (square) and describes in this application.But, be understandable that this two dimension curve can be any shape.
Device stratum 306 comprises x-code translator and the y-code translator for memory array 302.X-code translator and y-code translator are arranged in cylinder 318.The Part I 320 of x-code translator is aligned in the first side 310 of memory cell array in cylinder.The Part II 322 of x-code translator is aligned in the second side 312 of memory cell array in cylinder.In addition, the Part I 324 of y-code translator is aligned in the 3rd side 314 of memory array.The Part II 326 of y-code translator is aligned in the four side 316 of memory array.
Device stratum 306 also comprises the region 328 in cylinder 318, and region 328 does not arrange the part of x-code translator and y-code translator.Other peripheral circuits can be arranged in region 328.Via x-code translator, y-code translator and peripheral circuit being arranged in cylinder and memory array below, reduce the space that architecture of memory device takies (footprint).
Fig. 4 A illustrates the decomposition diagram of another architecture of memory device, and the x-code translator of this architecture of memory device and y-code translator are all configured in the below of memory array.Fig. 4 B illustrates the layout of architecture of memory device device stratum as shown in Figure 4 A.As the architecture of memory device shown in Fig. 3 A and Fig. 3 B, the architecture of memory device 400 shown in Fig. 4 A and Fig. 4 B comprises array stratum 402 and device stratum 404.Device stratum 404 is arranged on substrate 426.Substrate 426 can comprise silicon.Array stratum 402 comprises memory array 406.Memory array has edge, and edge comprises first side 408, second side 410, the 3rd side 412 and four side 414.The opposition side of 408 second side, first side 410, and the 3rd side 412 opposition sides at four side 414.The edge of side 408,410,412 and 414 define storage arrays.The edge of memory array and vertical (normal) be in the axis definition cylinder 416 (being illustrated by the broken lines) of array, and cylinder 416 above memory array with below two sides extend.
Device stratum 404 comprises x-code translator and y-code translator, and x-code translator and y-code translator are all arranged in cylinder 416.Particularly, device stratum 404 comprises the Part I 418 and Part III 420 of x-code translator, and Part I 418 and the Part III 420 of x-code translator is aligned in the first side 408 of memory array 406.Part II 422 and the Part IV 424 of x-code translator is aligned in the second side 410 of memory array.
In addition, device stratum comprises the Part I 428 and Part III 430 of y-code translator, and Part I 418 and the Part III 420 of y-code translator is aligned in the 3rd side 412 of memory cell array.In device stratum, Part II 432 and the Part IV 434 of y-code translator is aligned in the four side of memory cell array.
Device stratum 404 also comprises the region 436 in cylinder 416, and the part of x-code translator and y-code translator is not set in region 436.Other peripheral circuits can be arranged in region 436.
Architecture of memory device in another embodiment as shown in Fig. 3 A, Fig. 3 B, Fig. 4 A and Fig. 4 B, can understand device stratum configurable on the top of memory cell array.In this another embodiment, device stratum can have the identical layout of embodiment as shown, and can use thin-film transistor technologies to implement.Array in this embodiment can be implemented in silicon bulk substrate (bulk substrate).Therefore, x-code translator, y-code translator and peripheral circuit are arranged on the top of the memory array in cylinder, and cylinder is defined by the edge of memory array.
Fig. 5 illustrates the layout of the device stratum of another architecture of memory device.Device stratum 500 comprises the cylinder 502 being illustrated by the broken lines.Cylinder 502 is defined in the axis of array with vertical (normal) by the edge of the memory array (not illustrating) in array region.Device stratum comprises x-code translator 504 and y-code translator 506.X-code translator 504 is fully arranged in cylinder, and y-code translator 506 is fully arranged on cylinder outside.In the embodiment of another architecture of memory device, x-code translator 504 fully arranges cylinder outside, and y-code translator is fully arranged in cylinder.
In the embodiment of Fig. 3 A, Fig. 3 B, Fig. 4 A, Fig. 4 B and another alternative architecture of memory device that Fig. 5 is shown in, array stratum can comprise the Multilayer Memory array stratum being stacked in each other on bottom, therefore forms 3D memory array.
In another alternative embodiment, x-code translator and y-code translator can have the part in the cylinder outside being arranged in device stratum.Particularly, in another embodiment, code translator can be arranged on and be shown in configuration roughly the same in device stratum as Fig. 3 A, Fig. 3 B, Fig. 4 A, Fig. 4 B and Fig. 5, but non-ly aims at the side of memory array exactly.Therefore, code translator is partly arranged on the cylinder outside in device stratum.
Fig. 6 illustrates the vertical view that is shown in the pad stratum (pad lever) on the top of device stratum as Fig. 3 A and Fig. 3 B, the array stratum that omits architecture of memory device in figure.Device stratum comprises the Part I 602 and Part III 604 of x-code translator, Part I 602 and the Part III 604 of x-code translator are arranged in cylinder 606 (being represented by square dotted line), and cylinder 606 is defined by the edge of the memory array (not illustrating) in array stratum.Device stratum also comprises the Part I 608 and Part II 610 of y-code translator, and Part I 608 and the Part II 610 of y-code translator are arranged in cylinder 606.
Pad stratum comprises multiple pads (pad), for the sake of simplicity, four pad 612a-612d is shown.But can there is dozens of pad, or more, and this depends on selected interconnection technique (interconnecttechnology).Pad is current-carrying plate (conductive plate) or electric conductor (conductive body), is connected to an external circuit or wire pad in order to form.In one embodiment, pad 612a-612d is arranged in the cylinder 606 in pad stratum.In another embodiment, pad 612a-612d is arranged in pad stratum, makes all or part of outside that is arranged on the cylinder 606 in pad stratum of one or more pads.Pad can comprise I/O region (I/O regions), and this I/O region is the region that data line (data lines) is connected to external circuit (external circuitry) on pad.Pad also can comprise power supply supply (power supply) region, ground connection supply (ground supply) region and data address (data address) region.I/O connects the pad that can be formed in I/O region, power supply supply (power supply) connects the pad that can be formed at power supply area (power regions), grounding connection (ground connections) can be formed in ground area the pad of (ground regions), and data address connects the pad that can be formed in address (address regions) region.Multiple conductor wire 614a-614d couple pad to installing stratum.Conductor wire 614a-614d has the part (as 616) that extends to cylinder inner side (in pad stratum) from cylinder 606 outsides (array stratum), and forms contact in pad stratum.Therefore, conductor wire is not passed in the memory cell array in array stratum (not drawing).
Each conductor wire has width, and the region that conductor wire can arrange is arranged for do effective layout and connection according to structure.Particularly, conductor wire region 614c has width 618, and width 618 is the distance between the opposition side 620,622 of conductor wire region 614c.The part of each x-code translator and y-code translator has width and length.For example, the Part II 604 of x-code translator has width 624.The Part I 608 of y-code translator has length 626.The first distance 628 is the distance between the side 620 in conductor wire region and the side 630 of cylinder 606.Second distance 632 is the distance between the side 622 in conductor wire region and the side 634 of cylinder 606.Conductor wire region 614c has width 618 and is arranged in pad stratum, the width 624 that makes distance 628 be greater than the Part II 604 of x-code translator, and second distance 632 is greater than the length 626 of the Part I 608 of y-code translator.This may be used on all conductor wire region 614a-614d, makes the aforementioned side from any conductor wire to the distance of cylinder opposition side be greater than corresponding width and the length with the part of y-code translator adjacent to x-code translator.Therefore, in pad stratum, coupling device stratum is non-in the same area of device stratum with the conductor wire in device stratum to the conductor wire of pad, and this conductor wire installing in stratum connects code translator to the memory array in array stratum.
Fig. 7 illustrates the simplification sectional view of architecture of memory device 700 examples, and architecture of memory device 700 has device stratum 702, array stratum 704 and pad stratum 706.These stratum are configured on substrate 708.
Array stratum 704 comprises memory array 714, and memory array 714 has bit line and word line.The edge definition cylinder 716 of memory array 714, and the memory array of cylinder 716 in array stratum 704 above with below two sides extend.
Device stratum comprises forming the logical device of peripheral circuit, and it comprises x-code translator, y-code translator and other peripheral circuits.Illustrate and simplify the parts that are arranged on this logical device in cylinder 716.Based on the object inspiring, three patterned polysilicon regions 710,720 and 722 are in the polysilicon layer installing as shown in stratum.It should be noted that in fact to have thousands of or millions of patterned polysilicon regions configurable in polysilicon layer, and in the cylinder of polysilicon layer in device stratum.Dielectric layer 712 extends between patterned polysilicon region 710,720 and 722 and substrate 708.Patterned polysilicon region 710,720 and 722 can be corresponding transistorized grid, and transistor has the source/drain (not illustrating) in substrate 708.The part of x-code translator or y-code translator can be formed in patterned polysilicon region 710, and other peripheral circuits can be formed in patterned polysilicon region 720 and 722.And patterned polysilicon region 710,720 and 722 is in cylinder 716.Device stratum also comprises various interconnects (interconnects) 728,730,732 and 734, as is arranged on patterned metal layer and interlayer hole (vias) in cylinder 716.Interconnects 728,730,732 and 734 connects patterning polysilicon region 710,720 together with 722.Therefore, in embodiment, the part of x-code translator or y-code translator is arranged in cylinder 716 with other peripheral circuits as shown.In this example, region 718A represents an output node of one of x-code translator and y-code translator, or the output node of x-code translator and y-code translator, the output node of x-code translator and y-code translator is all positioned at cylinder 716, and x-code translator is connected to the interlayer conductor wire (as 718) in corresponding many interlayers (inter-level) conductor wire with y-code translator.
Interlayer conductor wire 718 connective word lines in more than first interlayer conductor wire or bit line both one of to the part of x-code translator and y-code translator, wherein in word line or the bit line storage unit in array stratum 704, and the part of x-code translator and y-code translator is arranged in patterned polysilicon region 710.Particularly, interlayer conductor wire 718 extends to substrate 708 and connects, and making in this example is directly to contact with transistorized regions and source/drain (not illustrating), and the patterned polysilicon region 710 of conduction is as transistorized grid.Interlayer conductor wire is alternately connected to touchdown area (landing area), metal wire or other interconnect architectures in device stratum in patterned polysilicon element.The part of interlayer conductor wire 718 extends out from the cylinder array stratum, makes conductor wire not be passed in the memory array 714 in array stratum.
Interlayer conductor wire 724 coupling arrangement stratum in more than second interlayer conductor wire are to the pad 726 in pad stratum 706.Particularly, interlayer conductor wire 724 extends from pad 726, and directly contacts with the substrate 708 in the 724A of region in this example.In an example, region 724A is the input node (input node) on input/output driver, and input/output driver provides address signal to code translator.Interlayer conductor wire is alternately connected to touchdown area, the metal wire in patterned polysilicon element or obtains other interconnect architectures in device stratum.In this example, directly contact with substrate via interlayer conductor wire 724, pad is connected to other peripheral circuits, and these other peripheral circuits are positioned at patterned polysilicon region 722.Interlayer conductor wire 724 has and extends in array stratum cylinder and extends back the part in the cylinder that pads stratum.Therefore, interlayer conductor wire is not passed in the memory array 714 in array stratum.
In another embodiment, device stratum can be above array stratum.Again another substitute implement in, array stratum can comprise multilayered memory cell array stratum, therefore sets up 3D memory cell array.
Fig. 8 A illustrates the calcspar of circuit component in device stratum, and circuit component can be arranged in cylinder, and cylinder is defined by the edge 800 of memory array, and it is projected in the device stratum top shown in Fig. 8 A, as uses heuristic dotted line to represent.Calcspar comprises memory cell array, and shown in memory cell array in array stratum there is edge 800, as extend on the circuit component as shown in all in device stratum.But any quantity of the circuit component shown in being understandable that can be below memory cell array.Be understandable that equally stratum is changeable, making the memory cell array in array stratum is below the circuit component in device stratum.
In this example, circuit component is in cylinder inner side, and circuit component comprises the part of x-code translator 802a and 802b, and the part of this x-code translator 802a and 802b is coupled to the word line of the memory array in array stratum.The part of x-code translator 802a and 802b is coupled to word line, and via line 820a and 820b, to perpendicular interconnection section (vertical interconnection segments), perpendicular interconnection section represents with symbol 822a and 822b.The part of y-code translator is coupled to global bit lines (global bit line) with page buffer 804a and 804b, and via line 824a and 824b, to perpendicular interconnection section, perpendicular interconnection section represents with symbol 826a and 826b.Global bit lines is coupled to local bitline (local bit line), and local bitline is arranged along the row (columns) in the memory array in array stratum.Each perpendicular interconnection section 822a, 822b, 826a and the 826b of part or all both one of extend to cylinder outside, and cylinder is defined by the edge 800 of memory array, wherein the edge 800 of memory array is between device stratum and array stratum.
In bus (bus) 810, provide address (address) to x-code translator 802a and the part of 802b, part and page buffer 804a and the 804b of y-code translator, address is selectively from pad stratum (illustrating among Fig. 8 B), or from device, the input/output terminal stratum provides.Data are supplied via the Data In-Line 812 from other circuit datas 814, the application circuit (special purpose application circuitry) of for example specific use or the combination (combination ofmodules) of module, the combination of module provides the function (system-on-a-chip functionality) of the system single chip of being supported by memory cell array.Data are supplied via Data In-Line 812 to I/O (I/O) end, selectively from pad stratum (illustrating among Fig. 8 B), or from the input/output terminal stratum at device, or to the integrated circuit memory of inner or outside other data endpoints (data destinations).
The application that controller 816 provides signal to arrange supply voltage (bias arrangementsupply voltages) to control biasing, biasing arranges supply voltage to see through voltage supply (voltage supply) or the supply in piece 818 (block 818) produces or provide to carry out various operation described herein.These operations comprise editor or erase operation, and read operation.Controller can use special purpose logic circuitry (special-purpose logic circuitry) as known in the art to implement.In another embodiment, controller comprises general service processor (general-purpose processor), and general service processor can be implemented on identical integrated circuit, and integrated circuit computer program is with the operation of control device.In other embodiment again, special purpose logic circuitry and the combination of general service processor can be used for the execution of controller.
Fig. 8 B illustrates and pads as shown in Figure 8 A the calcspar of stratum 830 above device stratum and array stratum.Array stratum comprises the memory array at tool edge 800, and edge 800 defines cylinder.Device stratum comprises multiple pad 832a-d.Device stratum is coupled to pad, is coupled to perpendicular interconnection section (vertical interconnection segments) via line 834a-d, and perpendicular interconnection section represents with symbol 836a-d.Each perpendicular interconnection section 836a-d of a part or whole each perpendicular interconnection section 836a-d both one of them extend to cylinder outside, and cylinder is defined by the edge 800 of memory array, wherein the edge 800 of memory array is between device stratum and pad stratum.
In sum, although the present invention discloses as above with preferred embodiment, so it is not in order to limit the present invention.Persond having ordinary knowledge in the technical field of the present invention, without departing from the spirit and scope of the present invention, when being used for a variety of modifications and variations.Therefore, protection scope of the present invention is when being as the criterion of defining depending on the claim scope of enclosing.
Claims (20)
1. a storage arrangement, comprising:
One memory cell array, is in an array stratum, and this memory cell array has multiple sides, and the plurality of side defines an edge;
One x-code translator and a y-code translator, be in a device stratum, and this x-code translator and this y-code translator one of them or both are at least partially disposed in a cylinder, and this cylinder is defined by this edge; And
Many interlayer conductor wires, to be connected to this x-code translator in this device stratum and this y-code translator to multiple bit lines and many word lines in this array stratum, the plurality of interlayer conductor wire has multiple parts, and the plurality of part extends to this cylinder inner side to form contact this array stratum from this cylinder outside.
2. storage arrangement according to claim 1, wherein this x-code translator and this y-code translator are to be fully arranged in this cylinder.
3. storage arrangement according to claim 1, wherein:
One Part I of this x-code translator is a first side that is aligned in this array, and a Part II of this x-code translator is a second side that is aligned in this array, the Shi opposition side, Yu Gai second side, this first side of this array; And
One Part I of this y-code translator is one the 3rd side that is aligned in this array, and a Part II of this y-code translator is a four side that is aligned in this array, the 3rd side and this four side are in opposition side and intersect at the Yu Gai second side, this first side of this array.
4. storage arrangement according to claim 3, wherein:
One Part III of this x-code translator is this first side that is aligned in this array, and a Part IV of this x-code translator is this second side that is aligned in this array; And
One Part III of this y-code translator is the 3rd side that is aligned in this array, and a Part IV of this y-code translator is this four side that is aligned in this array.
5. storage arrangement according to claim 1, further comprises:
Multiple page buffers are that the plurality of page buffer is arranged in this cylinder in this device stratum.
6. storage arrangement according to claim 1, further comprises:
One controller circuitry and a supply potential circuit, be in this device stratum, and this controller circuitry and this supply potential circuit are arranged in this cylinder.
7. storage arrangement according to claim 1, further comprises:
Multiple connection pads, are in a pad stratum, and Gai Dian stratum separates with this device stratum and this array stratum, and the plurality of connection pad is at least partially disposed in this cylinder; And
One second many interlayer conductor wires, are coupled between the plurality of connection pad and this device stratum, and a part for the plurality of more than second interlayer conductor wire extends to this cylinder inner side to form contact Gai Dian stratum from this cylinder outside.
8. storage arrangement according to claim 7, wherein:
The plurality of part of each this x-code translator has a corresponding x-code translator width and an x-code translator length, and the plurality of part of each this y-code translator has a corresponding y-code translator width and a y-code translator length; And comprise:
First and second distance, distance between one side of one first side that this first distance is more than a second interlayer conductor wire in the plurality of more than second interlayer conductor wire and this relative cylinder, this side of this cylinder is this first side in contrast to this more than second the interlayer conductor wire in the plurality of more than second interlayer conductor wire, this second distance is the distance between one second side of this more than second the interlayer conductor wire in the plurality of more than second interlayer conductor wire and a side of relative this cylinder, this side of this cylinder is in contrast to this this second side in the plurality of more than second interlayer conductor wire, this first distance is less than this second distance, this first distance is greater than this x-code translator width and this y-code translator width, this second distance is greater than this x-code translator length and this y-code translator length.
9. storage arrangement according to claim 7, wherein the plurality of many interlayer conductor wires of mentioning are for the first time arranged in one first many regions in this device stratum, and the plurality of more than second interlayer conductor wire be arranged in one second many regions in this device stratum, this more than first region is different from this more than second region.
10. storage arrangement according to claim 7, wherein the connection pad in the plurality of connection pad comprises an I/O spacer region, a power source pad panel region, a ground pad region and an address pad panel region.
Manufacture the method for storage arrangement, comprising for 11. 1 kinds:
Form a memory cell array in an array stratum, this memory cell array has multiple sides and defines an edge;
Form an x-code translator and a y-code translator in a device stratum, this x-code translator and this y-code translator are at least partially disposed in a cylinder, and this cylinder is defined by this edge; And
Form many interlayer conductor wires and be connected to this x-code translator in this device stratum and this y-code translator to multiple bit lines and many word lines in this array stratum, the plurality of interlayer conductor wire has multiple parts and extends to this cylinder inner side to form contact this array stratum from this cylinder outside.
12. manufacture methods according to claim 11, wherein this x-code translator and this y-code translator are to be fully arranged in this cylinder, this cylinder is defined by this edge.
13. manufacture methods according to claim 11, wherein:
One Part I of this x-code translator is a first side that is aligned in this array, and a Part II of this x-code translator is a second side that is aligned in this array, the Shi opposition side, Yu Gai second side, this first side of this array; And
One Part I of this y-code translator is one the 3rd side that is aligned in this array, and a Part II of this y-code translator is a four side that is aligned in this array, the 3rd side and this four side are in opposition side and intersect at the Yu Gai second side, this first side of this array.
14. manufacture methods according to claim 13, wherein:
One Part III of this x-code translator is this first side that is aligned in this array, and a Part IV of this x-code translator is this second side that is aligned in this array; And
One Part III of this y-code translator is the 3rd side that is aligned in this array, and a Part IV of this y-code translator is this four side that is aligned in this array.
15. manufacture methods according to claim 11, further comprise:
Form multiple page buffers in this device stratum, the plurality of page buffer is arranged in this cylinder.
16. manufacture methods according to claim 11, further comprise:
Form a controller circuitry and a supply potential circuit in this device stratum, this controller circuitry and this supply potential circuit are arranged in this cylinder.
17. manufacture methods according to claim 11, further comprise:
Form multiple connection pads in a pad stratum, Gai Dian stratum separates with this device stratum and this array stratum, and the plurality of connection pad is arranged in this cylinder at least partly; And
Form one second many interlayer conductor wires and be coupled between the plurality of connection pad and this device stratum, a part for the plurality of more than second interlayer conductor wire extends to this cylinder inner side to form contact Gai Dian stratum from this cylinder outside.
18. manufacture methods according to claim 17, wherein:
The plurality of part of each this x-code translator has a corresponding x-code translator width and an x-code translator length, and the plurality of part of each this y-code translator has a corresponding y-code translator width and a y-code translator length; And comprise:
First and second distance, distance between one side of one first side that this first distance is more than a second interlayer conductor wire in the plurality of more than second interlayer conductor wire and this relative cylinder, this side of this cylinder is this this first side in contrast to the plurality of more than second interlayer conductor wire, this second distance is the distance between one second side of this more than second the interlayer conductor wire in the plurality of more than second interlayer conductor wire and a side of relative this cylinder, this side of this cylinder is this second side in contrast to this more than second the interlayer conductor wire in the plurality of more than second interlayer conductor wire, this first distance is less than this second distance, this first distance is greater than this x-code translator width and this y-code translator width, this second distance is greater than this x-code translator length and this y-code translator length.
19. manufacture methods according to claim 17, wherein the plurality of many interlayer conductor wires of mentioning are for the first time arranged in one first many regions in this device stratum, and the plurality of more than second interlayer conductor wire be arranged in one second many regions in this device stratum, this more than first region is different from this more than second region.
20. manufacture methods according to claim 17, wherein the connection pad in the plurality of connection pad comprises an I/O spacer region, a power source pad panel region, a ground pad region and an address pad panel region.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201310015908.5A CN103928046B (en) | 2013-01-16 | 2013-01-16 | There is storage arrangement and the manufacture method thereof of code translator |
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| CN201310015908.5A CN103928046B (en) | 2013-01-16 | 2013-01-16 | There is storage arrangement and the manufacture method thereof of code translator |
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| CN101232038A (en) * | 2008-02-26 | 2008-07-30 | 中国科学院上海微系统与信息技术研究所 | Structure of high-density phase transition memory and process of preparation thereof |
| US20100157647A1 (en) * | 2008-12-19 | 2010-06-24 | Unity Semiconductor Corporation | Memory access circuits and layout of the same for cross-point memory arrays |
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| US5581498A (en) * | 1993-08-13 | 1996-12-03 | Irvine Sensors Corporation | Stack of IC chips in lieu of single IC chip |
| CN1838322A (en) * | 2005-03-22 | 2006-09-27 | 海力士半导体有限公司 | Flash memory with reduced size and method for accessing the same |
| CN101232038A (en) * | 2008-02-26 | 2008-07-30 | 中国科学院上海微系统与信息技术研究所 | Structure of high-density phase transition memory and process of preparation thereof |
| US20100157647A1 (en) * | 2008-12-19 | 2010-06-24 | Unity Semiconductor Corporation | Memory access circuits and layout of the same for cross-point memory arrays |
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