CN103915464A - 1T1R array based on transparent RRAM grid-control thin film transistor and preparing method thereof - Google Patents

Abstract

The invention discloses a 1T1R array based on a transparent RRAM grid-control thin film transistor and a preparing method thereof. The 1T1R array comprises a logic circuit, a signal input circuit, a signal output circuit and a power source Vdd. The logic circuit comprises a 1T1R unit and a first transistor. The 1T1R unit comprises a resistance changing resistor and a second transistor. The logic circuit is connected with the signal input circuit and the signal output circuit. The complex logic function of the 1T1R array is achieved through the connecting relation between the transistors and the resistance changing resistor.

Description

Based on transistorized 1T1R array of transparent RRAM grid controlled thin film and preparation method thereof

Technical field

The present invention relates to technical field of information storage, more specifically relate to a kind of based on transistorized 1T1R array of transparent RRAM grid controlled thin film and preparation method thereof.

Background technology

Resistance-variable storing device (resistive random access memory), be that RRAM is as the novel non-volatility memorizer of one, by utilizing the variation of resistance under different voltage effects, realizing the features such as high speed (< 5ns), high density, low operating voltage (< 1V), high integration, is the strong competitor of following semiconductor memory.Transparent RRAM device generally has the structure of metal-insulator-metal type, by add one deck nickel oxide (NiO), titanium oxide (TiO between two conductive metal ₂), hafnium oxide (HfO ₂) or zirconia (ZrO ₂) etc. there is the dielectric thin-film material of resistive characteristic, realize the transformation of resistive material at high low resistance state, thereby realize the erasable of data.Typically, thin-film material can form by methods such as sputter, chemical vapor deposition, atomic layer deposition and collosol and gels.

Thin-film transistor (thin-film transistor), TFT is a kind of transistor technology of based thin film technique, conventionally can prepare by the method such as chemical vapor deposition, collosol and gel.It is widely used in logical circuit.In 1T1R (the 1Transistor and1RRAM Device) structure of tradition based on RRAM, thin-film transistor (TFT) is as selecting pipe, and RRAM is as memory cell, and its function is comparatively single, cannot realize complicated logic function.

Summary of the invention

(1) technical problem that will solve

The technical problem to be solved in the present invention is how to overcome the deficiency that 1T1R array functional is single, realizes complicated logic function.

(2) technical scheme

In order to solve the problems of the technologies described above, the invention provides one based on the transistorized 1T1R array of transparent RRAM grid controlled thin film, described 1T1R array comprises logical circuit, signal input circuit, signal output apparatus, power supply Vdd; Wherein said logical circuit comprises 1T1R unit, the first transistor; Described 1T1R unit comprises resistive resistance and transistor seconds;

Described transistor seconds is nmos pass transistor or PMOS transistor; When described transistor seconds is nmos pass transistor, the first transistor is PMOS transistor, being connected to of described 1T1R array: one end of described resistive resistance connects described signal input circuit, the other end connects the grid of described transistor seconds, the source ground of described transistor seconds, its drain electrode is connected with the drain electrode of described signal output apparatus and described the first transistor, the grounded-grid of described the first transistor, and its source electrode connects power supply Vdd;

When described transistor seconds is PMOS transistor, the first transistor is nmos pass transistor, being connected to of described 1T1R array: one end of described resistive resistance connects described signal input circuit, the other end connects the grid of described transistor seconds, the source electrode of described transistor seconds connects described power supply Vdd, and its drain electrode is connected with the drain electrode of described signal output apparatus, described the first transistor; The grid of described the first transistor connects described power supply Vdd, its source ground.

Preferably, described 1T1R unit is at least one, unnecessary 1 time, and described 1T1R unit parallel connection.

Based on a preparation method for the transistorized 1T1R array of transparent RRAM grid controlled thin film, it is characterized in that, comprise the following steps:

S1, making logical circuit, be specially:

Prepare the substrate of described transistor seconds;

In described substrate, generate grid;

Generate resistive resistance at described grid;

On described grid, generate insulating barrier;

On described resistive resistance, generate electrode layer;

In described substrate, generate transistor seconds unit remainder;

Prepare grid, source electrode and the drain electrode of the first transistor;

S2, prepare signal input circuit and signal output apparatus;

S3, by signal input circuit and signal output apparatus be connected corresponding with described logical circuit respectively.

Preferably, in described step S1, in described substrate, generating transistor seconds unit remainder is specially:

On described insulating barrier, generate channel layer;

Generate respectively source electrode and drain electrode at described channel layer.

(3) beneficial effect

The invention provides one based on the transistorized 1T1R array of transparent RRAM grid controlled thin film and preparation method, by the annexation design of transistor AND gate resistive resistance, realized the logic function of 1T1R array complexity.

Accompanying drawing explanation

In order to be illustrated more clearly in the embodiment of the present invention or technical scheme of the prior art, to the accompanying drawing of required use in embodiment or description of the Prior Art be briefly described below, apparently, accompanying drawing in the following describes is only some embodiments of the present invention, for those of ordinary skills, do not paying under the prerequisite of creative work, can also obtain according to these accompanying drawings other accompanying drawing.

Fig. 1 is a kind of structural representation that 1T1R array of the present invention comprises two 1T1R unit;

Fig. 2 is the another kind of structural representation that 1T1R array of the present invention comprises two 1T1R unit;

Fig. 3 preparation method's flow chart of the present invention;

The structural representation of Fig. 4 transistor seconds of the present invention and resistive resistance.

Reference numeral:

1, substrate; 2, grid; 3 insulating barriers; 4 channel layers; 5 source electrodes; 6 drain electrodes; 7, resistive resistance; 8, upper electrode layer.

Embodiment

Below in conjunction with drawings and Examples, the present invention is described in further detail.Following examples are used for illustrating the present invention, but can not be used for limiting the scope of the invention.

Of the present invention based on the transistorized 1T1R array of transparent RRAM grid controlled thin film, comprise logical circuit, signal input circuit, signal output apparatus, power supply Vdd; Wherein said logical circuit comprises 1T1R unit, the first transistor; Described 1T1R unit comprises resistive resistance and transistor seconds; Described 1T1R unit is at least one, unnecessary 1 time, and the parallel connection of 1T1R unit.Transistor seconds is nmos pass transistor or PMOS transistor.

Fig. 1 is a kind of structural representation that 1T1R array of the present invention comprises two 1T1R unit; When in figure, transistor seconds is nmos pass transistor, the first transistor is PMOS transistor, being connected to of 1T1R array: one end of described resistive resistance connects described signal input circuit, the other end connects the grid of described transistor seconds, the source ground of described transistor seconds, its drain electrode is connected with the drain electrode of described signal output apparatus and described the first transistor, the grounded-grid of described the first transistor, and its source electrode connects power supply Vdd.The output that in figure, OUT is signal output apparatus; R1, r2 are resistive resistance; A, B are input signal.OUT output can form following logic according to input A, B signal and RRAM break-make, $\mathrm{OUT}=\stackrel{\&OverBar;}{r_1}\&CenterDot;\stackrel{\&OverBar;}{r_2}+\stackrel{\&OverBar;}{r_1}\&CenterDot;r_2\&CenterDot;\stackrel{\&OverBar;}{B}+\stackrel{\&OverBar;}{r_2}\&CenterDot;r_1\&CenterDot;\stackrel{\&OverBar;}{A}+r_1\&CenterDot;r_2\&CenterDot;\stackrel{\&OverBar;}{A}\&CenterDot;\stackrel{\&OverBar;}{B}.$ By the r to 1T1R ₁, r ₂programming, realize different break-makes combination (wherein 0 represents that high-impedance state disconnects, and 1 represents that low resistance state is communicated with), can obtain logical combination as shown in the table:

It is pointed out that input variable is not limited to A, B, can on Fig. 1 basis, add arbitrarily more inputs.But it should be noted that the 1T1R unit of realizing logic function must occur with form in parallel.

While realizing above-mentioned 1T1R array, need in the substrate of transistor seconds, be prepared transistor seconds, resistive resistance etc., be specially:

Described substrate 1 is preferably glass substrate, can be also some transparent flexible substrates.Described drain region is preferably the electric conducting materials such as platinum, titanium, copper, aluminium, titanium oxide, nickel, tungsten.Described resistive resistance 7 can be metal oxide materials or their combinations such as hafnium oxide, titanium oxide, zirconia, zinc oxide, tungsten oxide, tantalum oxide, and thickness can be 10nm-100nm.The sull chemical general formula that described channel layer can adopt is In-X-Zn-O, wherein, X is silicon, germanium, lanthanum, iridium etc., the film of at least one element in In-X-Zn-O oxide in doped metallic elements titanium, aluminium, magnesium, zirconium, hafnium, praseodymium, cerium and neodymium.Described grid 2 can adopt the electric conducting material such as FTO, ITO.Described source electrode 5 and drain electrode 6 can adopt the electric conducting materials such as platinum, titanium, copper, aluminium, titanium oxide, nickel, tungsten.The dielectric material that described insulating barrier 3 can be hafnium oxide, zirconia etc. and so on or their mixture.Described top electrode can be the electric conducting material such as ITO, FTO.

As shown in Figure 4, when grid-control 1T1R array is as shown in Figure 1 when structure, preparation method comprises step:

Clean substrate 1: use supersonic cleaning machine to clean substrate of glass;

Prepare grid 2: make grid by lithography, adopt magnetron sputtering technique growth FTO (fluorine tin-oxide) conductive film, use stripping means to form grid 2;

Preparation ZrO2 gate medium (insulating barrier 3) and change resistance layer 7: adopt sol-gel method, PECVD (Plasma Enhanced Chemical Vapor Deposition, plasma enhanced chemical vapor deposition method) technology or magnetron sputtering technique or ALD technology growth zirconium dioxide gate dielectric layer and change resistance layer film;

Preparation In-Y-Zn-O film (channel layer 4): use sol-gel method, form In-Y-Zn-O film;

Prepare source-drain electrode: above-mentioned sample is carried out to photoetching, adopt PVD (Physical VaporDeposition, physical vapour deposition (PVD)) technique deposit, use stripping means to form source electrode 5 and drain electrode 6, obtain TFT device;

Prepare top electrode: the hearth electrode using grid 2 as RRAM, with sol gel process or PVD (Physical Vapor Deposition, physical vapour deposition (PVD)), CVD (Chemical Vapor Deposition, chemical vapour deposition (CVD)) or ALD (Atomic layer deposition, ald) etc. the electric conducting material such as deposition techniques ITO, FTO, and carry out annealing in process, form top electrode 8.

Structure after completing is as shown in corresponding diagram 4.

The present invention, by resistive resistance being applied to the default different resistances of voltage, makes signal output apparatus can export the signal needing.

Fig. 2 is the another kind of structural representation that 1T1R array of the present invention comprises two 1T1R unit; When described transistor seconds is PMOS transistor, the first transistor is nmos pass transistor, being connected to of described 1T1R array: one end of described resistive resistance connects described signal input circuit, the other end connects the grid of described transistor seconds, the source electrode of described transistor seconds connects described power supply Vdd, and its drain electrode is connected with the drain electrode of described signal output apparatus, described the first transistor; The grid of described the first transistor connects described power supply Vdd, its source ground.The output that in figure, OUT is signal output apparatus; R1, r2 are resistive resistance; A, B are input signal.OUT output can form following logic according to input A, B signal and RRAM break-make, $\mathrm{OUT}=\stackrel{\&OverBar;}{r_1}\&CenterDot;\stackrel{\&OverBar;}{r_2}+\stackrel{\&OverBar;}{r_1}\&CenterDot;r_2\&CenterDot;\stackrel{\&OverBar;}{B}+\stackrel{\&OverBar;}{r_2}\&CenterDot;r_1\&CenterDot;\stackrel{\&OverBar;}{A}+r_1\&CenterDot;r_2\&CenterDot;\stackrel{\&OverBar;}{A}\&CenterDot;\stackrel{\&OverBar;}{B}.$ By the r to 1T1R ₁, r ₂programming, realize different break-makes combination (wherein 0 represents that high-impedance state disconnects, and 1 represents that low resistance state is communicated with), can obtain logical combination as shown in the table:

It is pointed out that input variable is not limited to A, B, can on Fig. 2 basis, add arbitrarily more inputs.But it should be noted that the transistor of realizing logic function must occur with form in parallel.Fig. 2 shows that the preparation method of array is identical with the preparation method of the array shown in Fig. 1 and the material of use, repeats no more here.

The invention also discloses a kind of preparation method based on the transistorized 1T1R array of transparent RRAM grid controlled thin film, be summarized as follows, as shown in Figure 3:

S1: prepare logical circuit;

S2: prepare signal input circuit and signal output apparatus;

In reality, can in a substrate, realize the preparation of logical circuit, signal input circuit and signal output apparatus.

S3: be connected corresponding with described logical circuit to described signal input circuit and signal output apparatus.Described corresponding connection refers to, as required, signal input circuit, signal output apparatus and logical circuit is connected to the signal that signal output apparatus output is needed.

In reality, conventionally first logical circuit is prepared, then just signal input circuit and signal output apparatus is prepared.Take Fig. 4 as example, described in corresponding step S1, prepare logical circuit and be specially:

S11: preparation substrate 1;

S12: generate grid material 2 in described substrate;

S13: generate resistive resistance 7 and TFT insulating barrier 3 in described substrate;

S14: generate transistor remaining element in described substrate;

S15: generate upper electrode layer 8 on described resistive resistance 7;

S16: prepare grid, source electrode and the drain electrode of the first transistor.

Described in step S14, in described substrate, generating transistor unit is specially:

S141: generate channel layer 4 on described insulating barrier 3;

S142: generate respectively source electrode 5 and drain electrode 6 at described channel layer 4.

Described resistive resistance 7 can be metal oxide materials or their combinations such as hafnium oxide, titanium oxide, zirconia, zinc oxide, tungsten oxide, tantalum oxide, and forms by physical vapour deposition (PVD), chemical vapour deposition (CVD), ald or sol gel process.

Above execution mode is only for the present invention is described, but not limitation of the present invention.Although the present invention is had been described in detail with reference to embodiment, those of ordinary skill in the art is to be understood that, technical scheme of the present invention is carried out to various combinations, revises or is equal to replacement, do not depart from the spirit and scope of technical solution of the present invention, all should be encompassed in the middle of claim scope of the present invention.

Claims (4)

1. based on the transistorized 1T1R array of transparent RRAM grid controlled thin film, it is characterized in that, described 1T1R array comprises logical circuit, signal input circuit, signal output apparatus, power supply Vdd; Wherein said logical circuit comprises 1T1R unit, the first transistor; Described 1T1R unit comprises resistive resistance and transistor seconds;

Described transistor seconds is nmos pass transistor or PMOS transistor; When described transistor seconds is nmos pass transistor, the first transistor is PMOS transistor, being connected to of described 1T1R array: one end of described resistive resistance connects described signal input circuit, the other end connects the grid of described transistor seconds, the source ground of described transistor seconds, its drain electrode is connected with the drain electrode of described signal output apparatus and described the first transistor, the grounded-grid of described the first transistor, and its source electrode connects power supply Vdd;

When described transistor seconds is PMOS transistor, the first transistor is nmos pass transistor, being connected to of described 1T1R array: one end of described resistive resistance connects described signal input circuit, the other end connects the grid of described transistor seconds, the source electrode of described transistor seconds connects described power supply Vdd, and its drain electrode is connected with the drain electrode of described signal output apparatus, described the first transistor;

The grid of described the first transistor connects described power supply Vdd, its source ground.

2. 1T1R array according to claim 1, is characterized in that, described 1T1R unit is at least one, unnecessary 1 time, and described 1T1R unit parallel connection.

3. the preparation method based on the transistorized 1T1R array of transparent RRAM grid controlled thin film, is characterized in that, comprises the following steps:

S1, making logical circuit, be specially:

Prepare the substrate of described transistor seconds;

In described substrate, generate grid;

Generate resistive resistance at described grid;

On described grid, generate insulating barrier;

On described resistive resistance, generate electrode layer;

In described substrate, generate transistor seconds unit remainder;

Prepare grid, source electrode and the drain electrode of the first transistor;

S2, prepare signal input circuit and signal output apparatus;

S3, by signal input circuit and signal output apparatus be connected corresponding with described logical circuit respectively.

4. method according to claim 3, is characterized in that, generates transistor seconds unit remainder and be specially in described step S1 in described substrate:

On described insulating barrier, generate channel layer;

Generate respectively source electrode and drain electrode at described channel layer.