CN103905157A - Accumulation left-shift QC-LDPC encoder with partial parallel input in deep space communication - Google Patents

Abstract

The invention provides an accumulation left-shift QC-LDPC encoder with partial parallel input in deep space communication. The encoder comprises 12 generator polynomial searching tables which store all cyclic matrix generator polynomials in all code generator matrixes in advance, 12 2048-bit binary multipliers used for carrying out scalar multiplying on message segments and generator polynomial bits, 12 2048-bit binary adders used for carrying out modulo-2 adding on products and shifting register content, and 12 2048-bit shifting registers used for storing the sum of content subjected to one-bit ring shift left. Finally, verification data are contained in the 12 shifting registers. The encoder with partial codes input in parallel is compatible with all QC-LDPC in a CCSDS deep space communication system, and has the advantages of being few in register, simple in structure, low in power consumption, low in cost, high in work efficiency and large in throughput.

Description

The cumulative QC-LDPC encoder that moves to left of part parallel input in deep space communication

Technical field

The present invention relates to field of channel coding, particularly the cumulative QC-LDPC encoder that moves to left of part parallel input in a kind of CCSDS deep space communication system.

Background technology

Low-density checksum (Low-Density Parity-Check, LDPC) code is one of efficient channel coding technology, and quasi-cyclic LDPC (Quasi-Cyclic LDPC, QC-LDPC) code is a kind of special LDPC code.Generator matrix G and the check matrix H of QC-LDPC code are all the arrays being made up of circular matrix, have the feature of segmentation circulation, therefore be called as QC-LDPC code.The first trip of circular matrix is the result of 1 of footline ring shift right, and all the other each provisional capitals are results of 1 of its lastrow ring shift right, and therefore, circular matrix is characterized by its first trip completely.Conventionally, the first trip of circular matrix is called as its generator polynomial.

CCSDS deep space communication standard adopts the QC-LDPC code of system form, and the left-half of its generator matrix G is a unit matrix, and right half part is by a × c b × b rank circular matrix G _i,jthe array that (0≤i<a, a≤j<t, t=a+c) forms, as follows:

Wherein, I is b × b rank unit matrixs, the full null matrix in the 0th, b × b rank.Capable and the b row of the continuous b of G are called as respectively the capable and piece row of piece.From formula (1), G has the capable and t piece of a piece row.Make circular matrix G _i,jfirst trip g _i,jit is its generator polynomial.CCSDS deep space communication standard has adopted 9 kinds of QC-LDPC codes, all has c=12.Fig. 1 has provided parameter a, b and the t under different code class π.

For CCSDS deep space communication standard, the corresponding code word v=of generator matrix G (s, p), that the front a piece of G is listed as correspondence is information vector s=(e ₀, e ₁..., e _{a × b-1}), that rear c piece row are corresponding is verification vector p=(d ₀, d ₁..., d _{c × b-1}).Take b bit as one section, information vector s is divided into a section, i.e. s=(s ₀, s ₁..., s _a-1); Verification vector p is divided into c section, i.e. p=(p ₀, p ₁..., p _c-1).From v=sG, j-a section verification vector meets

P _j-a=s ₀g _{0, j}+ s ₁g _{1, j}+ ... + s _ig _i,j+ ... + s _a-1g _{a-1, j}(2) wherein, 0≤i<a, a≤j<t, t=a+c.Order

with

respectively generator polynomial g _i,jthe result of ring shift right n position and ring shift left n position, wherein, 0≤n≤b.So, the i item on formula (2) equal sign the right is deployable is

$s_i{G}_{i,j}=e_{i\&times;b}{g}_{i,j}^{r\left(0\right)}+e_{i\&times;b+1}{g}_{i,j}^{r\left(1\right)}+\&CenterDot;\&CenterDot;\&CenterDot;e_{i\&times;b+b-1}{g}_{i,j}^{r(b-1)}---\left(3\right)$

What at present, QC-LDPC code extensively adopted is the serial encoder that adds accumulator (Type-I Shift-Register-Adder-Accumulator, SRAA-I) circuit based on c I type shift register.Fig. 2 is the functional block diagram of single SRAA-I circuit, and information vector s by turn serial sends into this circuit.When using SRAA-I circuit to verification section p _j-awhen (a≤j<t) encodes, all generator polynomials of the j piece row of the pre-stored generator matrix G of generator polynomial look-up table, accumulator is cleared initialization.In the time that the 0th clock cycle arrives, shift register loads the 0th row of G, the generator polynomial of j piece row from generator polynomial look-up table

information bit e0 moves into circuit, and with the content of shift register

carry out scalar multiplication, product

add with content 0 mould 2 of accumulator, and deposit back accumulator.In the time that the 1st clock cycle arrives, 1 of shift register ring shift right, content becomes

information bit e1 moves into circuit, and with the content of shift register

carry out scalar multiplication, product

content with accumulator

mould 2 adds, and deposit back accumulator.Above-mentionedly move to right-take advantage of-Jia-storing process proceeds down.In the time that b-1 clock cycle finishes, information bit e _b-1moved into circuit, now that cumulative adder stores is part and s ₀g _{0, j}, this is message segment s ₀to p _j-acontribution.In the time that b clock cycle arrives, shift register loads the 1st row of G, the generator polynomial of j piece row from generator polynomial look-up table

repeat above-mentionedly to move to right-take advantage of-Jia-storing process.In the time that message segment s1 moves into circuit completely, cumulative adder stores be part and s ₀g _{0, j}+ s ₁g _{1, j}.Repeat said process, until the whole serials of whole information vector s move into circuit.Now, that cumulative adder stores is verification section p _j-a.Use c the serial encoder shown in SRAA-I circuit energy pie graph 3, it obtains c verification section within a × b clock cycle simultaneously.This scheme needs 2 × c × b register, c × b two input and door and c × b two input XOR gate, also needs the generator polynomial of c a × b bit ROM storage circular matrix.

For compatible 9 kinds of code classes, in CCSDS deep space communication standard, the existing solution of QC-LDPC encoder is based on 12 SRAA-I circuit.This scheme has two shortcomings: the one, need 49152 registers, and cause the power consumption of circuit large, cost is high; The 2nd, serial input information bit, loaded in parallel generator polynomial, needs 24577 connecting lines.So many line can cause that circuit structure complexity, the operating frequency of encoder is low, throughput is little.

Summary of the invention

In CCSDS deep space communication system there is the shortcoming that power consumption is large, cost is high, circuit structure is complicated, operating frequency is low, throughput is little in the existing implementation of many yards of class QC-LDPC encoders, for these technical problems, the invention provides a kind of based on the cumulative part parallel input coding device moving to left.

As shown in Figure 5, in CCSDS deep space communication system, the cumulative QC-LDPC of the moving to left encoder of part parallel input is mainly made up of 4 parts: generator polynomial look-up table, b position binary multiplier, b position binary adder and shift register.Cataloged procedure divides 5 steps to complete: the 1st step, zero clearing shift register R ₀, R ₁..., R ₁₁; The 2nd step, input message section s _i(0≤i<a); The 3rd step, generator polynomial look-up table L ₀, L ₁..., L ₁₁a during difference output code class π generator matrix G i piece is capable, a+1 ..., the generator polynomial bit of t-1 piece row, these generator polynomial bits are respectively by b position binary multiplier M ₀, M ₁..., M ₁₁with message segment s _icarry out scalar multiplication, b position binary multiplier M ₀, M ₁..., M ₁₁product respectively by b position binary adder A ₀, A ₁..., A ₁₁with shift register R ₀, R ₁..., R ₁₁content be added, b position binary adder A ₀, A ₁..., A ₁₁and be recycled the result moving to left after 1 and deposit respectively shift register R in ₀, R ₁..., R ₁₁; The 4th step, repeats the 3rd step b time; The 5th step, changes the value of i take 1 as step-length increases progressively, and repeats 2nd～4 step a time, until that whole information vector s inputs is complete, now, shift register R ₀, R ₁..., R ₁₁that store is respectively verification section p ₀, p ₁..., p ₁₁, they have formed verification vector p=(p ₀, p ₁..., p ₁₁).

Part parallel input coding device provided by the invention is simple in structure, the QC-LDPC code of all code classes in compatible CCSDS deep space communication system, can keep, under the condition of coding rate, reducing register and line, reduce power consumption and cost, improve operating frequency and throughput.

Can be further understood by detailed description and accompanying drawings below about advantage of the present invention and method.

Accompanying drawing explanation

Fig. 1 has gathered parameter a and the c of 9 kinds of code class QC-LDPC code generator matrixes in CCSDS deep space communication system;

Fig. 2 is the functional block diagram that I type shift register adds accumulator SRAA-I circuit;

Fig. 3 is the QC-LDPC serial encoder being made up of c SRAA-I circuit;

Fig. 4 is the functional block diagram that adds shift register MASR circuit of taking advantage of of parallel input;

Fig. 5 is be made up of the MASR circuit of 12 parallel inputs a kind of based on the cumulative part parallel input QC-LDPC encoder moving to left.

Embodiment

Below in conjunction with accompanying drawing, preferred embodiment of the present invention is elaborated, thereby so that advantages and features of the invention can be easier to be it will be appreciated by those skilled in the art that, protection scope of the present invention is made to more explicit defining.

Make generator polynomial g _i,j=(g _{i, j, 0}, g _{i, j, 1}..., g _{i, j, b-1}), G _i,jcan be considered the weighted sum of unit matrix ring shift right version,

G _i,j=g _{i, j, 0}i ^{r (0)}+ g _{i, j, 1}i ^{r (1)}+ ... + g _{i, j, b-1}i ^{r (b-1)}(4) so, the i item on formula (2) equal sign the right is deployable is

$\begin{array}{c}{s}_i{G}_{i,j}=s_i(g_{i,j,0}{I}^{r\left(1\right)}+\&CenterDot;\&CenterDot;\&CenterDot;+g_{i,j,b-1}{I}^{r(b-1)})\\ =g_{i,j,0}{I}^{r\left(0\right)}+g_{i,j,1}{s}_i{I}^{r\left(1\right)}+\&CenterDot;\&CenterDot;\&CenterDot;+g_{i,j,b-1}{s}_i{I}^{r(b-1)}\\ =g_{i,j,0}{s}_i^{r\left(0\right)}+g_{i,j,1}{s}_i^{r\left(1\right)}+\&CenterDot;\&CenterDot;\&CenterDot;+g_{i,j,b-1}{s}_i^{r(b-1)}\end{array}---\left(5\right)$

Since by s _iring shift right n position is equivalent to by its ring shift left b-n position, formula (5) can be rewritten as so

$\begin{array}{c}{s}_i{G}_{i,j}=g_{i,j,0}{s}_i^{1\left(b\right)}+g_{i,j,1}{s}_i^{1(b-1)}+\&CenterDot;\&CenterDot;\&CenterDot;+s_{i,j}^{1\left(1\right)}\\ ={\left(g_{i,j,0}{s}_i\right)}^{1\left(b\right)}+{\left(g_{i,j,1}{s}_i\right)}^{1(b-1)}+\&CenterDot;\&CenterDot;\&CenterDot;+{\left(g_{i,j,b-1}{s}_i\right)}^{1\left(1\right)}\\ ={(0+g_{i,j,0}{s}_i)}^{1\left(b\right)}+{\left(g_{i,j,1}{s}_i\right)}^{1(b-1)}+\&CenterDot;\&CenterDot;\&CenterDot;+{\left(g_{i,j,b-1}{s}_i\right)}^{1\left(1\right)}\\ ={({(0+g_{i,j,0}{s}_i)}^{1\left(1\right)}+g_{i,j,1}{s}_i)}^{1(b-1)}+\&CenterDot;\&CenterDot;\&CenterDot;+{\left(g_{i,j,b-1}{s}_i\right)}^{1\left(1\right)}\\ ={(\&CenterDot;\&CenterDot;\&CenterDot;{({(0+g_{i,j,0}{s}_{i}1)}^{\left(}+g_{i,j,1}{s}_i)}^{1\left(1\right)}+\&CenterDot;\&CenterDot;\&CenterDot;+g_{i,j,b-1}{s}_i)}^{1\left(1\right)}\end{array}---\left(6\right)$

Compared with formula (3), the remarkable advantage of formula (6) is the parallel input information bits of segmentation, and serial loads generator polynomial g _i,j, without ring shift right generator polynomial g _i,j.Formula (6) is the process of a take advantage of-Jia-move to left-store, and it is realized and adds shift register (Multiplier-Adder-Shift-Register, MASR) circuit with taking advantage of of parallel input.Fig. 4 is the functional block diagram of the MASR circuit of parallel input, and information vector s is take b bit as one section of parallel this circuit of sending into.When the MASR circuit of inputting with walking abreast is to verification section p _j-awhen (a≤j<t) encodes, all generator polynomials of the j piece row of the pre-stored generator matrix G of generator polynomial look-up table, shift register is cleared initialization.In the time that the 0th clock cycle arrives, message segment s ₀move into circuit, the 0th row of generator polynomial look-up table output G, the generator polynomial g of j piece row _{0, j}the 0th bit g _{0, j, 0}, and with message segment s ₀carry out scalar multiplication, product g _{0, j, 0}s ₀add with content 0 mould 2 of shift register, and g _{0, j, 0}s ₀result (the 0+g that ring shift left is 1 _{0, j, 0}s ₀) ^{l (1)}deposit travelling backwards bit register.In the time that the 1st clock cycle arrives, generator polynomial look-up table output g _{0, j}the 1st bit g _{0, j, 1}, and with message segment s ₀carry out scalar multiplication, product g _{0, j, 1}s ₀content (0+g with shift register _{0, j, 0}s ₀) ^{l (1)} mould 2 adds, and (0+g _{0, j, 0}s ₀) ^{l (1)}+ g _{0, j, 1}s ₀the result ((0+g that ring shift left is 1 _{0, j, 0}s ₀) ^{l (1)}+ g _{0, j, 1}s ₀) ^{l (1)}deposit travelling backwards bit register.Above-mentioned taking advantage of-Jia-move to left-storing process is proceeded down.In the time that b-1 clock cycle finishes, shift register storage be part and s ₀g _{0, j}, this is message segment s ₀to p _j-acontribution.In the time that b clock cycle arrives, message segment s ₁move into circuit, repeat above-mentioned taking advantage of-Jia-move to left-storing process.When generator polynomial look-up table has been exported g _{1, j}last bit g _{1, j, b-1}time, shift register storage be part and s ₀g _{0, j}+ s ₁g _{1, j}.Repeat said process, until all parallel circuit that moves into of whole information vector s.Now, that shift register storage is verification section p _j-a.

Fig. 5 has provided be made up of the MASR of 12 parallel inputs a kind of based on the cumulative part parallel input QC-LDPC encoder moving to left, and is made up of generator polynomial look-up table, b position binary multiplier, b position binary adder and four kinds of functional modules of shift register.Generator polynomial look-up table L ₀, L ₁..., L ₁₁all codes class that prestores respectively generator matrix G a, a+1 ..., all circular matrix generator polynomials in t-1 piece row.Generator polynomial look-up table L ₀, L ₁..., L ₁₁output generator polynomial bit respectively with message segment s _i(0≤i<a) carries out scalar multiplication, and these 12 scalar multiplications are respectively by b position binary multiplier M ₀, M ₁..., M ₁₁complete.B position binary multiplier M ₀, M ₁..., M ₁₁product respectively with shift register R ₀, R ₁..., R ₁₁content be added, these 12 nodulo-2 additions are respectively by b position binary adder A ₀, A ₁..., A ₁₁complete.B position binary adder A ₀, A ₁..., A ₁₁and be recycled the result moving to left after 1 and deposit respectively shift register R in ₀, R ₁..., R ₁₁.

Generator polynomial look-up table L ₀, L ₁..., L ₁₁store the circular matrix generator polynomial in all code class QC-LDPC code generator matrixes.L ₀～L ₁₁store respectively all generator polynomials in all code class generator matrix G a～t-1 piece row, for arbitrary row, store successively the 0th, 1 ..., the capable corresponding generator polynomial of a-1 piece.

The invention provides a kind of part parallel input QC-LDPC coding method moving to left based on adding up, 9 kinds of code class QC-LDPC codes in its compatible CCSDS deep space communication standard, its coding step is described below:

The 1st step, zero clearing shift register R ₀, R ₁..., R ₁₁;

The 2nd step, input message section s _i(0≤i<a);

The 3rd step, generator polynomial look-up table L ₀, L ₁..., L ₁₁a during difference output code class π generator matrix G i piece is capable, a+1 ..., the generator polynomial bit of t-1 piece row, these generator polynomial bits are respectively by b position binary multiplier M ₀, M ₁..., M ₁₁with message segment s _icarry out scalar multiplication, b position binary multiplier M ₀, M ₁..., M ₁₁product respectively by b position binary adder A ₀, A ₁..., A ₁₁with shift register R ₀, R ₁..., R ₁₁content be added, b position binary adder A ₀, A ₁..., A ₁₁and be recycled the result moving to left after 1 and deposit respectively shift register R in ₀, R ₁..., R ₁₁;

The 4th step, repeats the 3rd step b time;

The 5th step, changes the value of i take 1 as step-length increases progressively, and repeats 2nd～4 step a time, until that whole information vector s inputs is complete, now, shift register R ₀, R ₁..., R ₁₁that store is respectively verification section p ₀, p ₁..., p ₁₁, they have formed verification vector p=(p ₀, p ₁..., p ₁₁).

Be not difficult to find out from above step, whole cataloged procedure needs a × b clock cycle altogether, identical with the existing serial encoding method based on 12 SRAA-I circuit.

In CCSDS deep space communication standard, the existing solution of QC-LDPC encoder needs 49152 registers, 24576 two inputs and door and 24576 two input XOR gate, and the present invention needs 24576 registers, 24576 two inputs and door and 24576 two input XOR gate.Two kinds of coding methods expend equal number with door and XOR gate, but the present invention has saved 50% register.

Existing solution needs 24577 lines to connect shift register and generator polynomial look-up table, and the present invention only needs 2060 connecting lines.

As fully visible, for the encoder of 9 kinds of QC-LDPC codes in CCSDS deep space communication standard, compared with existing solution, the present invention has kept identical coding rate, save the register of half, greatly simplify circuit connection, there is the advantages such as simple in structure, power consumption is little, cost is low, operating frequency is high, throughput is large.

The above; it is only one of the specific embodiment of the present invention; but protection scope of the present invention is not limited to this; any those of ordinary skill in the art are in the disclosed technical scope of the present invention; the variation that can expect without creative work or replacement, within all should being encompassed in protection scope of the present invention.Therefore, protection scope of the present invention should be as the criterion with the protection range that claims were limited.

Claims (3)

1. the cumulative QC-LDPC encoder that moves to left of part parallel input in deep space communication, the generator matrix G of QC-LDPC code is divided into the capable and t piece row of a piece, and it is by a × c b × b rank circular matrix G that rear c piece is listed as corresponding part generator matrix _i,jthe array forming, g _i,jcircular matrix G _i,jgenerator polynomial, wherein, t=a+c, a, b, c, i, j and t are nonnegative integer, 0≤i<a, a≤j<t, CCSDS deep space communication standard has adopted the QC-LDPC code of 9 kinds of different code class π, π is respectively 0, 1, 2, 3, 4, 5, 6, 7, 8, for these 9 kinds different code class quasi-cyclic LDPC codes, all there is c=12, 9 kinds of parameter a corresponding to different code class are respectively 8, 8, 8, 16, 16, 16, 32, 32, 32, 9 kinds of parameter b corresponding to different code class are respectively 2048, 512, 128, 1024, 256, 64, 512, 128, 32, 9 kinds of parametric t corresponding to different code class are respectively 20, 20, 20, 28, 28, 28, 44, 44, 44, the corresponding code word v=of generator matrix G (s, p), that the front a piece of G is listed as correspondence is information vector s, that rear c piece row are corresponding is verification vector p, take b bit as one section, information vector s is divided into a section, be s=(s ₀, s ₁..., s _a-1), verification vector p is divided into c section, i.e. p=(p ₀, p ₁..., p ₁₁), it is characterized in that, described encoder comprises following parts:

Generator polynomial look-up table L ₀, L ₁..., L ₁₁, a in all code class QC-LDPC code generator matrix G that prestore respectively, a+1 ..., the circular matrix generator polynomial of t-1 piece row;

B position binary multiplier M ₀, M ₁..., M ₁₁, respectively to message segment and generator polynomial look-up table L ₀, L ₁..., L ₁₁output bit carry out scalar multiplication;

B position binary adder A ₀, A ₁..., A ₁₁, respectively to b position binary multiplier M ₀, M ₁..., M ₁₁sum of products shift register R ₀, R ₁..., R ₁₁content carry out mould 2 and add;

Shift register R ₀, R ₁..., R ₁₁, store respectively b position binary adder A ₀, A ₁..., A ₁₁and be recycled the result that moves to left after 1 and final verification section p ₀, p ₁..., p ₁₁.

2. the cumulative QC-LDPC encoder that moves to left of part parallel input in a kind of deep space communication according to claim 1, is characterized in that described generator polynomial look-up table L ₀～L ₁₁store respectively all generator polynomials in all code class generator matrix G a～t-1 piece row, for arbitrary row, store successively the 0th, 1 ..., the capable corresponding generator polynomial of a-1 piece.。

3. the cumulative QC-LDPC coding method that moves to left of part parallel input in deep space communication, the generator matrix G of QC-LDPC code is divided into the capable and t piece row of a piece, and it is by a × c b × b rank circular matrix G that rear c piece is listed as corresponding part generator matrix _i,jthe array forming, g _i,jcircular matrix G _i,jgenerator polynomial, wherein, t=a+c, a, b, c, i, j and t are nonnegative integer, 0≤i<a, a≤j<t, CCSDS deep space communication standard has adopted the QC-LDPC code of 9 kinds of different code class π, π is respectively 0, 1, 2, 3, 4, 5, 6, 7, 8, for these 9 kinds different code class quasi-cyclic LDPC codes, all there is c=12, 9 kinds of parameter a corresponding to different code class are respectively 8, 8, 8, 16, 16, 16, 32, 32, 32, 9 kinds of parameter b corresponding to different code class are respectively 2048, 512, 128, 1024, 256, 64, 512, 128, 32, 9 kinds of parametric t corresponding to different code class are respectively 20, 20, 20, 28, 28, 28, 44, 44, 44, the corresponding code word v=of generator matrix G (s, p), that the front a piece of G is listed as correspondence is information vector s, that rear c piece row are corresponding is verification vector p, take b bit as one section, information vector s is divided into a section, be s=(s ₀, s ₁..., s _a-1), verification vector p is divided into c section, i.e. p=(p ₀, p ₁..., p ₁₁), it is characterized in that, described coding method comprises the following steps:

The 1st step, zero clearing shift register R ₀, R ₁..., R ₁₁;

The 2nd step, input message section s _i, wherein, 0≤i<a;

The 3rd step, generator polynomial look-up table L ₀, L ₁..., L ₁₁a during difference output code class π generator matrix G i piece is capable, a+1 ..., the generator polynomial bit of t-1 piece row, these generator polynomial bits are respectively by b position binary multiplier M ₀, M ₁..., M ₁₁with message segment s _icarry out scalar multiplication, b position binary multiplier M ₀, M ₁..., M ₁₁product respectively by b position binary adder A ₀, A ₁..., A ₁₁with shift register R ₀, R ₁..., R ₁₁content be added, b position binary adder A ₀, A ₁..., A ₁₁and be recycled the result moving to left after 1 and deposit respectively shift register R in ₀, R ₁..., R ₁₁;

The 4th step, repeats the 3rd step b time;

The 5th step, changes the value of i take 1 as step-length increases progressively, and repeats 2nd～4 step a time, until that whole information vector s inputs is complete, now, shift register R ₀, R ₁..., R ₁₁that store is respectively verification section p ₀, p ₁..., p ₁₁, they have formed verification vector p=(p ₀, p ₁..., p ₁₁).

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