CN103903550B - Non-crystalline silicon integrated circuit is driven about a kind of grid - Google Patents

Abstract

The invention provides the non-crystalline silicon integrated circuit that a kind of grid drive, TFT(T1 is started) including state, state reset TFT(T2), pulling drive TFT(T3), drop-down driving TFT(T4) and state storage electric capacity (C1), because circuit is simple, area occupied is little, can preferably meet the display requirement to frame.

Description

Non-crystalline silicon integrated circuit is driven about a kind of grid

Technical field

Non-crystalline silicon integrated circuit is driven about a kind of grid.

Background technology

The driving element non-crystalline silicon tft (thin film transistor (TFT)) of active display is except for display device pixel Beyond switch, also it is used for the integrated of grid drive circuit.Current integrated circuit mostly is 7 transistors and adds 1 The mode of individual electric capacity, such as Fig. 1.Output signal Qn-1 or the high voltage of unlatching signal STV when upper level During arrival, transistor T1 opens the grid of transistor T3 and T6 and is in high-voltage state.T3, T6 open, The grid of T4, T5 are in low-voltage state, and T4, T5 close, and now, Qn-1 or STV closes, T3, T6 continues to be held open state, and T4 continues to remain off, and the high voltage of CK signal arrives, and passes through The transistor 6 opened forms this stage circuit and output Qn, CK signal at stop, and Qn is set to low-voltage State, output completes.The when that next stage signal arriving, T2 pipe is opened, and T3, T6 grid sets low pressure, T3, T6 close.CK periodically opens the periodicity unlatching of T4 and T5, T4 by C1 can keep T3, The closed mode of T6, the T7 that the periodicity of T5 is opened and also periodically opened by CKB control alternately opens, Keep being output as low-voltage state.It it is more than the operation principle of 7T1C circuit.

In derivative circuit, add integral reset transistor and reset signal, when circuit abnormal, can lead to Crossing this transistor allows all circuit resets to original state, and such as Fig. 2, when needing to reset, Reset signal is opened T8, T9, set low voltage status by T6, T3 grid, and output simultaneously sets low voltage status, and reset completes.By Little in non-crystalline silicon electron mobility, that driving force is weak reason, TFT is required for bigger breadth length ratio, because of This, the circuit of 7T1C can occupy bigger frame space, causes the display frame of non-crystalline silicon to do narrow being subject to Limit.

Summary of the invention

The invention provides a kind of non-crystalline silicon drive integrated circult, 4T1C gets final product work, can effectively reduce and drive Area shared by galvanic electricity road.

Refer to Fig. 3, the work schedule of circuit of the present invention is as follows: when upper level output signal or startup start When signal arrives T1 grid, T1 opens, and the grid of T3 and electric capacity C1 charge to high-voltage state.Then T1 closes, and the grid of T3 keeps high-voltage state with C1.Under this state, the when that the pulse of CK arriving, Outfan can be transferred to by T3, form the output of grid this one-level of integrated circuit.When next stage exports The when of reaching T2, T2 opens, and the grid of T3 and C1 pulled down to low-voltage state.T3 closes.This Time, output current potential periodically can be remained to low-voltage Vgl state by CKB.

Refer to Fig. 4, transistor T5, the T6 of integral reset function on the basis of the present invention, can be added, When circuit abnormal, starting Reset signal, this signal makes T3 be closed by T5, and By C1 storing state and keep.Reset signal makes outfan Qn be set to low-voltage shape by T6 simultaneously State, it is to avoid the impact on the superior and the subordinate's circuit.Reset terminates.

Refer to Fig. 5, when the input voltage of the present invention and signal change, reverse scan pattern can be supported.Will The signal of the source electrode of former T1 changes Vgl into from Vgh, changes the drain signal of former T2 into Vgh from Vgl, when During next line Qn+1 output, T2 opens, and the grid of T3 and electric capacity C1 charge to high-voltage state.Then T2 closes, and the grid of T3 keeps high-voltage state with C1.Under this state, the when that the pulse of CK arriving, Outfan can be transferred to by T3, form the output of grid this one-level of integrated circuit.When next stage exports Qn-1 The when of arriving T1, T1 opens, and the grid of T3 and C1 pulled down to low-voltage state.T3 closes. Now, output current potential periodically can be remained to low-voltage Vgl state by CKB.

Accompanying drawing explanation

Accompanying drawing 1 is the 7T1C amorphous silicon gate could drive integrated circult schematic diagram of current main-stream.

On the basis of accompanying drawing 2 is the 7T1C of current main-stream, add integral reset transistor and reset signal 9T1C amorphous silicon gate could drive integrated circult schematic diagram.

Accompanying drawing 3 is 4T1C amorphous silicon gate could drive integrated circult schematic diagram of the present invention.

On the basis of accompanying drawing 4 is 4T1C of the present invention, add integral reset transistor and the 6T1C of reset signal Amorphous silicon gate could drive integrated circult schematic diagram.

Accompanying drawing 5 is the principle explanation of counter-scanning function on the basis of 4T1C of the present invention.

Accompanying drawing 6 is each input sequential chart with output signal of 4T1C mono-specific embodiment of the present invention.

Detailed description of the invention

Be described below be the present invention multiple embodiments in some, it is desirable to provide basic to the present invention Understand, it is no intended to confirm the crucial or decisive key element of the present invention or limit scope of the claimed.According to Technical scheme, under the connotation not changing the present invention, can mutually replace and obtain other Implementation.As between amorphous silicon film transistor source and drain the two poles of the earth and grid exist electric capacity, at this circuit On the basis of, the circuit or adding arbitrary size electric capacity between the grid source of any transistor between grid leak is included in In the range of the invention of this circuit.For another example, the simple string of transistor and after be still transistor circuit characteristic, any Transistor is carried out the mode circuit gone here and there and split, if equivalent circuit is identical with circuit of the present invention, still at this electricity Within the invention scope on road.

One embodiment of the invention, refer to Fig. 3, starts TFT T1, state reset TFT T2 including state, Pulling drive TFT T3, drop-down driving TFT T4 and state storage electric capacity C1, wherein the grid of T1 connects Enabling signal STV or upper level output Qn-1, T1 source electrode meet high voltage source Vgh, the drain electrode of T1 with The source electrode of T2 connects, and the grid of T2 receives reset signal Reset or the leakage of next stage output Qn+1, T2 LVPS Vgl is received in pole.One end of C1 is connected with the drain electrode of T1, and it is solid that the other end of C1 receives one Determine current potential.The source electrode of T3 receives CK signal, and the grid of T3 is connected with the drain electrode of T1, the drain electrode of T3 Being connected to outfan Qn, T4 source electrode is connected to outfan Qn, and the grid of T4 is connected to CKB, T4 leakage Pole is connected to LVPS Vgl.CK with CKB is that the high pressure of amplitude is identical with Vgh, low pressure and Vgl Identical, high pressure dutycycle 0.25, phase contrast differs one group of clock signal of 180 °.CK Yu CKB and Waveform such as Fig. 6 of upper level output.When upper level output signal or startup commencing signal arrive T1 grid, T1 opens, and the grid of T3 and electric capacity C1 charge to high-voltage state.Then T1 closes, the grid of T3 High-voltage state is kept with C1.Under this state, the when that the pulse of CK arriving, can be passed by T3 It is passed to outfan, forms the output of grid this one-level of integrated circuit.When next stage output arrives T2 when, T2 opens, and the grid of T3 and C1 pulled down to low-voltage state.T3 closes.Now, CKB can week Phase property output current potential is remained to low-voltage Vgl state.CK and CKB, upper level output waveform, When the output waveform of prime, the output waveform of next stage is as shown in Figure 6.

Claims (1)

1. drive non-crystalline silicon integrated circuit about a kind of grid, start TFT, state reset TFT including state, Pulling drive TFT, drop-down driving TFT and state storage electric capacity, wherein said state starts the grid of TFT Pole meets enabling signal STV or upper level output Qn-1, and described state starts the source electrode of TFT and connects high voltage source Vgh, described state starts the drain electrode of TFT and is connected with the source electrode of described state reset TFT, and described state is multiple The grid of position TFT receives reset signal Reset or next stage output Qn+1, described state reset TFT's LVPS Vgl is received in drain electrode, and one end of described state storage electric capacity and described state start the leakage of TFT The most connected, the other end of described state storage electric capacity receives a fixed potential, the source of described pulling drive TFT CK signal is received in pole, and the drain electrode that the grid of described pulling drive TFT starts TFT with described state is connected Connecing, the drain electrode of described pulling drive TFT is connected to outfan Qn, and described drop-down driving TFT source electrode connects To outfan Qn, the grid of described drop-down driving TFT is connected to CKB, described drop-down driving TFT leakage Pole is connected to LVPS Vgl；

CK signal is identical with Vgh with the high pressure that CKB is amplitude, and low pressure is identical with Vgl, high pressure duty Ratio is less than 0.5, and phase contrast differs one group of clock signal of 180 °, and wherein, Vgh is the unlatching electricity of TFT Pressure, Vgl is that TFT turns off voltage.