CN103901771A - System and method for extracting time information of Beidou satellite based on FPGA - Google Patents
System and method for extracting time information of Beidou satellite based on FPGA Download PDFInfo
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- CN103901771A CN103901771A CN201410155441.9A CN201410155441A CN103901771A CN 103901771 A CN103901771 A CN 103901771A CN 201410155441 A CN201410155441 A CN 201410155441A CN 103901771 A CN103901771 A CN 103901771A
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Abstract
The invention discloses a system and method for extracting time information of a Beidou satellite based on an FPGA. The method comprises the following steps that firstly, satellite information output by a Beidou receiving machine is received by an FPGA processing unit, secondly, time of the received satellite information is extracted, so that coordinated universal time is extracted; thirdly, extracted coordinated universal time is converted into national standard time. According to the system and method, the time information of the Beidou satellite is extracted, so that the purpose that a time service is provided through the Beidou satellite is achieved.
Description
Technical field
The present invention relates to a kind of extracting method and device of satellite information, particularly relate to a kind of system and method that extracts big-dipper satellite temporal information based on FPGA.
Background technology
China Beidou satellite navigation system (BeiDou Navigation Satellite System, BDS) be global positioning satellite and the communication system that China develops voluntarily, the 3rd ripe satellite navigation system after Shi Ji U.S. Global Positioning System (GPS) (Global Positioning System, GPS) and Russian GLONASS GPS (Global Position System).System is made up of vacant terminal, ground surface end and user side, can be in the world round-the-clock, round-the-clock provides high precision, highly reliable location, navigation, time service service for all types of user, and tool short message communication capacity, tentatively possess area navigation, location and time service ability, positioning precision is better than 20m, and time service precision is better than 100ns.
At present, select from economy and stability, generally adopt the mode of gps satellite time service to obtain universal time, by universal time, the time of current demonstration is adjusted to synchronizeing of the time that reaches and universal time.But it is real-time time service that gps satellite time set utilizes the time service that gps satellite system is carried out, power dissipation ratio is larger, and gps satellite system is the satellite system abroad having, its safe reliability is poor, therefore, be necessary to propose in fact a kind of technological means, to utilize big-dipper satellite to carry out time service by extracting the realization of big-dipper satellite temporal information.
Summary of the invention
The deficiency existing for overcoming above-mentioned prior art, one of the present invention object is to provide a kind of system and method that extracts big-dipper satellite temporal information based on FPGA, it receives the satellite information of Beidou receiver output by FPGA serial ports, and the satellite information of reception is carried out to the extraction of temporal information by temporal information extraction module, finally the temporal information of extraction being converted to the standard time carries out the synchronous of other clock systems again, has realized the extraction to big-dipper satellite temporal information and then has utilized big-dipper satellite to carry out the object of time service.
For reaching above-mentioned and other object, the present invention proposes a kind of system of extracting big-dipper satellite temporal information based on FPGA, at least comprises:
Beidou receiver, receives the navigation message of big-dipper satellite transmission, and the navigation message receiving is obtained to satellite information through decoding;
FPGA processing unit, receives the satellite information that this Beidou receiver is exported, and the national standard time is extracted afterwards and be converted into the satellite information of the acquisition time of carrying out.
Further, this FPGA processing unit comprises:
Dual port RAM, carries out real time data buffer memory by the satellite information of reception;
Time extraction module, carries out time extraction according to default data layout to satellite information, extracts universal time;
Time modular converter, is converted to the national standard time by the universal time extracting.
Further, this FPGA processing unit utilizes UART mouth to receive the satellite information of this Beidou receiver output.
Further, the baud rate of the serial ports of this FPGA processing unit reception satellite information is consistent with the baud rate of the serial ports of this Beidou receiver output satellite information.
Further, this satellite information comprises temporal information, position coordinates, speed, the elevation angle, position angle, signal to noise ratio (S/N ratio).
Further, this FPGA processing unit is made up of logic gate and trigger, and command execution mode is executed in parallel.
For achieving the above object, the present invention also provides a kind of method of extracting big-dipper satellite temporal information based on FPGA, comprises the steps:
Step 1, FPGA processing unit receives the satellite information of Beidou receiver output;
Step 2, carries out time extraction to the satellite information receiving, and extracts universal time;
Step 3, is converted to the national standard time by the universal time information of extraction.
Further, this FPGA processing unit receives the satellite information of this Beidou receiver by UART mouth, and the baud rate of the serial ports of this FPGA reception satellite information is consistent with the baud rate of the serial ports of this Beidou receiver output satellite information.
Further, this satellite information comprises temporal information, position coordinates, speed, the elevation angle, position angle, signal to noise ratio (S/N ratio).
Further, in step 2, the temporal information of extraction comprises year, month, day, hour, min, second, and is accurate to second after the radix point of position three.
Compared with prior art, a kind of system and method that extracts big-dipper satellite temporal information based on FPGA of the present invention receives the satellite information of Beidou receiver output by FPGA serial ports, and the satellite information of reception is carried out to the extraction of temporal information by temporal information extraction module, finally the temporal information of extraction being converted to the standard time carries out the synchronous of other clock systems again, has realized the extraction to big-dipper satellite temporal information and then has utilized big-dipper satellite to carry out the object of time service
Accompanying drawing explanation
Fig. 1 is a kind of system architecture diagram that extracts the system of big-dipper satellite temporal information based on FPGA of the present invention;
Fig. 2 is a kind of flow chart of steps of extracting the method for big-dipper satellite temporal information based on FPGA of the present invention;
Fig. 3 is the process flow diagram of the time information extraction of preferred embodiment of the present invention.
Embodiment
Below, by specific instantiation accompanying drawings embodiments of the present invention, those skilled in the art can understand other advantage of the present invention and effect easily by content disclosed in the present specification.The present invention also can be implemented or be applied by other different instantiation, and the every details in this instructions also can be based on different viewpoints and application, carries out various modifications and change not deviating under spirit of the present invention.
Fig. 1 is a kind of system architecture diagram that extracts the system of big-dipper satellite temporal information based on FPGA of the present invention.As shown in Figure 1, a kind of system of extracting big-dipper satellite temporal information based on FPGA of the present invention, at least comprises: Beidou receiver 101 and FPGA processing unit 102.
Wherein, Beidou receiver 101 receives the navigation message of big-dipper satellite transmission, and the navigation message receiving is obtained to satellite information through decoding, according to the Big Dipper two generations satellite navigation system principle of work, Beidou receiver 101 will receive 4 big-dipper satellites just can carry out three-dimensional localization, receives 3 satellites and carries out two-dimensional localization.After Beidou receiver 101 location positionings and under the condition no longer changing, receiver only need to receive a wherein big- dipper satellite 103 or 104 just can carry out precise time transmission, Beidou receiver 101 can obtain satellite information through decoding after the navigation message that receives big- dipper satellite 103 or 104 transmission, this satellite information comprises temporal information, position coordinates, speed, the elevation angle, position angle, signal to noise ratio (S/N ratio) etc., it should be noted that, the big-dipper satellite information receiving, follows UNICORE+NMEA agreement, FPGA processing unit 102 receives by serial communication the satellite information that Beidou receiver 101 is exported, the national standard time is extracted afterwards and be converted into the satellite information of the acquisition time of carrying out, it should be noted that, the baud rate of serial ports that FPGA processing unit 102 receives satellite information is consistent with the baud rate of the serial ports of Beidou receiver 101 output satellite information, only in this way just can receive satellite information, in preferred embodiment of the present invention, FPGA processing unit 102 logic-based door and triggers, adopt executed in parallel structure, therefore there is data processing speed fast, it comprises dual port RAM 105, time extraction module 106 and time modular converter 107, dual port RAM 105 is for carrying out the buffer memory of real time data, the satellite information receiving by FPGA processing unit 102 deposits in dual port RAM 105, when being filled with after data in dual port RAM 105, notice time extraction module 106 carries out the extraction of temporal information according to UNICORE agreement, in UNICORE agreement, stipulate the message format for different application, as BDRMC, BDGGA, BDGSV, BDVTG etc., and every kind of content difference that message format comprises.The satellite information that only extracts a kind of message format of the temporal information extraction procedure identification of the present invention's design, for example, extract the temporal information in BDRMC message format.Particularly, time extraction module 106, ceaselessly detect the satellite information receiving, in the time detecting that message format is " $ BDRMC ", this information is sent into the extraction of carrying out temporal information in temporal information extraction procedure, in " $ BDRMC ", need the temporal information of extracting, immediately following after a frame $ BDRMC, secondly position effectively identifies, and is the information such as latitude again; Based on $ BDRMC message format, temporal information extraction procedure need be only that UTC time (hhmmss, sss) extracts by the information of 10 bytes after a frame $ BDRMC, can complete the extraction of UTC time.Time extraction module 106 need to select suitable data layout can reach best effect according to user, and elapsed time extraction module time of extracting can not be immediately synchronous for clock system (A clock system 108 or B clock system 109 as shown in the figure), because the time of extracting is Coordinated Universal Time(UTC) (Universal Time Coordinated, UTC), claim again universal time, it is the basis that current countries in the world time signal is broadcast, therefore, before carrying out clock synchronous, to carry out time conversion by time modular converter 107, the UTC time is converted to the national standard time, for example, in China, time modular converter 107 is converted into Beijing time, Beijing time and UTC time phase difference eight hours, time after conversion just can be for synchronous other each clock systems, will be had unified clock by synchronous A clock system and B clock system, what this just made each clock system time has relatively had a meaning.
Fig. 2 is a kind of flow chart of steps of extracting the method for big-dipper satellite temporal information based on FPGA of the present invention.As shown in Figure 2, a kind of method of extracting big-dipper satellite temporal information based on FPGA of the present invention, comprises the steps:
Fig. 3 is the process flow diagram of the time information extraction of preferred embodiment of the present invention.First FPGA processing unit will receive the satellite information of Beidou receiver output, according to serial communication principle, two serial ports only just can intercom mutually in the time that baud rate is consistent, before communication, the baud rate of the reception serial ports of FPGA is consistent with the baud rate of Beidou receiver serial ports for this reason, receive at satellite information time to constantly detect serial ports and whether have data transmission (step 301), in the time of the negative edge of data detection signal, explanation has data to send over, at this moment start reception Baud rate generator generation clock and carry out the reception (step 302) of data, if the negative edge of data-signal do not detected, do not start, and continue to detect.Further, when receiving after Baud rate generator startup, will continue to receive big-dipper satellite information (step 303), and the satellite information of reception is stored in dual port RAM 105, time extraction module carries out time extraction from the another port of dual port RAM simultaneously, before extracting, according to the extraction time form (as BDRMC) pre-seting, the information of extracting is judged, judge whether the temporal information form receiving meets (step 304), whether a frame of the satellite information receiving is BDRMC, if met, carry out extracting time information (step 305), if do not met, by information filtering, because the temporal information of extracting is the UTC time, before clock synchronous, to convert Beijing time (step 306) to, distribute according to world time zone, China Dong 8th district, therefore the mistiming of Beijing time and UTC is eight hours, therefore only need UTC to add eight and just can obtain Beijing time.Just can extract fast and accurately and can be used for the synchronous temporal information of each clock system according to above-mentioned temporal information extracting method.
Visible, a kind of system and method based on FPGA extraction big-dipper satellite temporal information of the present invention utilizes the feature of FPGA high speed data processing, set it as the data acquisition and processing (DAP) unit that receives and process big-dipper satellite information, FPGA receives the satellite information of Beidou receiver by UART mouth, in order to realize data reception and extraction real-time, in FPGA, design a dual port RAM and carried out satellite information buffer memory, when FPGA receives satellite information in real time, carried out the extraction of temporal information by time extraction module, the temporal information extracting is further converted to Beijing time, for synchronous other clock systems, realize " to clock " unified between each system.
Above-described embodiment is illustrative principle of the present invention and effect thereof only, but not for limiting the present invention.Any those skilled in the art all can, under spirit of the present invention and category, modify and change above-described embodiment.Therefore, the scope of the present invention, should be as listed in claims.
Claims (10)
1. a system of extracting big-dipper satellite temporal information based on FPGA, at least comprises:
Beidou receiver, receives the navigation message of big-dipper satellite transmission, and the navigation message receiving is obtained to satellite information through decoding;
FPGA processing unit, receives the satellite information that this Beidou receiver is exported, and the national standard time is extracted afterwards and be converted into the satellite information of the acquisition time of carrying out.
2. a kind of system of extracting big-dipper satellite temporal information based on FPGA as claimed in claim 1, is characterized in that, this FPGA processing unit comprises:
Dual port RAM, carries out real time data buffer memory by the satellite information of reception;
Time extraction module, carries out time extraction according to the data layout of user preset to satellite information, extracts universal time;
Time modular converter, is converted to the national standard time by the universal time extracting.
3. a kind of system of extracting big-dipper satellite temporal information based on FPGA as claimed in claim 2, is characterized in that: this FPGA processing unit utilizes UART mouth to receive the satellite information of this Beidou receiver output.
4. a kind of system of extracting big-dipper satellite temporal information based on FPGA as claimed in claim 3, is characterized in that: the baud rate of the serial ports of this FPGA processing unit reception satellite information is consistent with the baud rate of the serial ports of this Beidou receiver output satellite information.
5. a kind of system of extracting big-dipper satellite temporal information based on FPGA as claimed in claim 2, is characterized in that: this satellite information comprises temporal information, position coordinates, speed, the elevation angle, position angle, signal to noise ratio (S/N ratio).
6. a kind of system of extracting big-dipper satellite temporal information based on FPGA as claimed in claim 2, is characterized in that: this FPGA processing unit is made up of logic gate and trigger, and command execution mode is executed in parallel.
7. a method of extracting big-dipper satellite temporal information based on FPGA, comprises the steps:
Step 1, FPGA processing unit receives the satellite information of Beidou receiver output;
Step 2, carries out time extraction to the satellite information receiving, and extracts universal time;
Step 3, is converted to the national standard time by the universal time information of extraction.
8. a kind of method of extracting big-dipper satellite temporal information based on FPGA as claimed in claim 7, it is characterized in that: this FPGA processing unit receives the satellite information of this Beidou receiver by UART mouth, the baud rate of the serial ports of this FPGA reception satellite information is consistent with the baud rate of the serial ports of this Beidou receiver output satellite information.
9. a kind of method of extracting big-dipper satellite temporal information based on FPGA as claimed in claim 7, is characterized in that: this satellite information comprises temporal information, position coordinates, speed, the elevation angle, position angle, signal to noise ratio (S/N ratio).
10. a kind of method of extracting big-dipper satellite temporal information based on FPGA as claimed in claim 7, is characterized in that: in step 2, the temporal information of extraction comprises year, month, day, hour, min, second, and after the radix point being accurate to second three.
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| CN105388751A (en) * | 2015-11-26 | 2016-03-09 | 株洲南车时代电气股份有限公司 | Method and system used for preventing clock jump in motor train unit |
| CN107229217A (en) * | 2017-06-01 | 2017-10-03 | 中船航海科技有限责任公司 | A kind of time synchronism apparatus and its synchronous method |
| CN109525346A (en) * | 2017-09-20 | 2019-03-26 | 中兴通讯股份有限公司 | A kind of method and device for realizing time synchronization |
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Application publication date: 20140702 |