CN103888109A - Circuit for detecting clock source fault - Google Patents
Circuit for detecting clock source fault Download PDFInfo
- Publication number
- CN103888109A CN103888109A CN201410160364.6A CN201410160364A CN103888109A CN 103888109 A CN103888109 A CN 103888109A CN 201410160364 A CN201410160364 A CN 201410160364A CN 103888109 A CN103888109 A CN 103888109A
- Authority
- CN
- China
- Prior art keywords
- signal
- low frequency
- frequency pulse
- pulse signal
- clock source
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Abstract
The invention discloses a circuit for detecting a clock source fault. The circuit comprises a processor. The processor is provided with an input end and an output end. The input end is used for being connected with a clock source, the clock source is used for generating low-frequency pulse signals, and the output end is used for outputting indicator signals. The processor is used for locking and storing the low-frequency pulse signal, generated by the clock source, at the start timing point of each timing period. Whether the current low-frequency pulse signal generated by the clock source is always the same as the locked and stored low-frequency pulse signal or not is detected in the timing period; if yes, a first indicator signal is output, wherein the first indicator signal is used for indicating that the low-frequency pulse signal is lost, and if not, a second indicator signal is output, wherein the second indicator signal is used for indicating that the low-frequency signal is not lost. The timing period is longer than or equal to the clock period of the low-frequency pulse signal. In this way, whether the clock source fault exists or not is detected by detecting whether the low-frequency pulse signal is lost.
Description
Technical field
The present invention relates to power automation technical field, relate in particular a kind of circuit that detects clock source failure.
Background technology
In power automation technical field, between communication equipment and communication equipment, generally carry out the transmission of information by pulse signal, for a certain communication equipment, generally there are multiple clock sources, if when presently used clock source breaks down, can be switched on another clock source of backup.
Seen from the above description, whether presently used clock source breaks down, and becomes the major issue of the normal work of communication equipment, therefore, how clock source is detected, to ensure that its serviceability is as those skilled in the art's technical problem in the urgent need to address.
Summary of the invention
In view of this, the invention provides a kind of circuit that detects clock source failure, to realize, whether presently used clock source is broken down and detected.
For achieving the above object, the invention provides following technical scheme:
A device that detects clock source failure, comprises processor, and described processor has input and output, and described input is for being connected with described clock source, and described clock source is for generation of low frequency pulse signal; Described output is used for exporting index signal;
Described processor starts the low frequency pulse signal of the described clock source generation of timing point each time-count cycle for latch; And within time-count cycle, detect current low frequency pulse signal that described clock source produces whether always identical with the low frequency pulse signal of institute latch; If so, export the first index signal, described the first index signal is used to indicate described low frequency pulse signal and loses; If not, output the second index signal, described the second index signal is used to indicate described low frequency pulse signal and loses;
Wherein, be more than or equal to the clock cycle of described low frequency pulse signal described time-count cycle.
Whether always identical with the low frequency pulse signal of institute latch preferably, described processor is within time-count cycle, detect current low frequency pulse signal that described clock source produces; If so, export the first index signal; If not, output the second index signal, is specially,
Whether the current low frequency pulse signal that described processor produces for more described clock source is identical with the low frequency pulse signal of institute's latch, and according to comparative result, generates first signal; Within time-count cycle, determine that described first signal, for the low frequency pulse signal for characterizing described current low frequency pulse signal and institute latch is when different, generates the 3rd signal; Determine that described first signal, for the low frequency pulse signal for characterize described current low frequency pulse signal and institute latch is always when identical, generates secondary signal; And export the first index signal according to described secondary signal, export the second index signal according to described the 3rd signal.
Whether always identical with the low frequency pulse signal of institute latch preferably, described processor is within time-count cycle, detect current low frequency pulse signal that described clock source produces; If so, export the first index signal; If not, output the second index signal, is specially:
Whether the current low frequency pulse signal that described processor produces for more described clock source is identical with the low frequency pulse signal of institute's latch, and according to comparative result, generates first signal; Within time-count cycle, whether always identically with default standard signal detect described first signal, the described standard signal signal identical with the low frequency pulse signal of institute latch that be the current low frequency pulse signal that produces of the described clock source of sign;
If so, export the first index signal; If not, output the second index signal.
Preferably, described processor is exported the first index signal and is specially:
The current low frequency pulse signal that described processor produces at described clock source and the low frequency pulse signal of institute latch continue the identical time while reaching Preset Time, export the first index signal.
Preferably,
In the time that the low frequency pulse signal of described current low frequency pulse signal and institute latch is identical, described first signal is low level signal;
In the time that the low frequency pulse signal of described current low frequency pulse signal and institute latch is different, described first signal is high level signal;
Described standard signal is low level signal;
Or in the time that the low frequency pulse signal of described current low frequency pulse signal and institute latch is identical, described first signal is high level signal;
In the time that the low frequency pulse signal of described current low frequency pulse signal and institute latch is different, described first signal is low level signal;
Described standard signal is high level signal.
Detect a device for clock source failure, described clock source is for generation of low frequency pulse signal, and this device comprises:
For the first timer of the timing that circulates, be more than or equal to the clock cycle of described low frequency pulse signal the time-count cycle of described the first timer;
The first register being connected with described the first timer with described clock source respectively, described the first register starts the low frequency pulse signal of the described clock source generation of timing point each time-count cycle for latch;
The detecting unit being connected with described clock source, described the first timer and described the first register respectively;
Whether always identical with the low frequency pulse signal of institute latch wherein, described detecting unit is within time-count cycle, detect current low frequency pulse signal that described clock source produces; If so, export the first index signal, described the first index signal is used to indicate described low frequency pulse signal and loses; If not, output the second index signal, described the second index signal is used to indicate described low frequency pulse signal and loses.
Preferably, described detecting unit comprises:
First input end is connected with described clock source, the logical circuit that the second input is connected with described the first register, whether the current low frequency pulse signal that described logical circuit produces for more described clock source is identical with the low frequency pulse signal of institute's latch, and according to comparative result, output first signal;
The second register being connected with the output of logical circuit, described the first timer respectively, the output signal of described the second register is set to secondary signal in the time that start timing point each time-count cycle;
Described the second register is within time-count cycle, and the first signal that is recorded to described logical circuit output, for the low frequency pulse signal for characterizing described current low frequency pulse signal and institute latch is when different, is exported the 3rd signal; The first signal that is recorded to the output of described logical circuit, for the low frequency pulse signal for characterize described current low frequency pulse signal and institute latch is always when identical, keeps exporting secondary signal;
The 3rd register being connected with described the second register with described the first timer respectively, for the signal in the second register output described in the beginning timing point latch of each time-count cycle, and in the time that the signal of institute's latch is secondary signal, export the first index signal, in the time that the signal of institute's latch is the 3rd signal, output the second index signal.
Preferably, also comprise and second timer being connected of described detecting unit;
Described the second timer, in the time that described detecting unit is exported the first index signal, starts timing;
In the time that described detecting unit is exported the second index signal, zero clearing.
Preferably, described logical circuit is XOR gate logical circuit;
In the time that the low frequency pulse signal of described current low frequency pulse signal and institute latch is identical, described first signal is low level signal;
In the time that the low frequency pulse signal of described current low frequency pulse signal and institute latch is different, described first signal is high level signal;
Described secondary signal is high level signal; Described the 3rd signal is low level signal;
Or described logical circuit is same or gate logic;
In the time that the low frequency pulse signal of described current low frequency pulse signal and institute latch is identical, described first signal is high level signal;
In the time that the low frequency pulse signal of described current low frequency pulse signal and institute latch is different, described first signal is low level signal;
Described secondary signal is low level signal; Described the 3rd signal is high level signal.
Known via above-mentioned technical scheme, compared with prior art, the embodiment of the invention discloses a kind of device that detects clock source failure, comprise processor, the input of this processor is for being connected with clock source, output is used for exporting index signal, starts the low frequency pulse signal of the described clock source generation of timing point by latch each time-count cycle; And within time-count cycle, detect current low frequency pulse signal that described clock source produces whether always identical with the low frequency pulse signal of institute latch; If so, export the first index signal, described the first index signal is used to indicate described low frequency pulse signal and loses, and in the time that low frequency pulse signal occurs to lose, can confirm that fault has occurred clock source; If not, export the second index signal, described the second index signal is used to indicate described low frequency pulse signal and loses, in the time that low frequency pulse signal is lost, can confirm that clock source does not break down, as can be seen here, the present invention is by determining that whether low frequency pulse signal is lost, and has realized the detection whether clock source is broken down.
Brief description of the drawings
In order to be illustrated more clearly in the embodiment of the present invention or technical scheme of the prior art, to the accompanying drawing of required use in embodiment or description of the Prior Art be briefly described below, apparently, accompanying drawing in the following describes is only embodiments of the invention, for those of ordinary skill in the art, do not paying under the prerequisite of creative work, other accompanying drawing can also be provided according to the accompanying drawing providing.
Fig. 1 is the structural representation of an embodiment of the disclosed a kind of device that detects clock source failure of the embodiment of the present invention;
Fig. 2 is the structural representation of an embodiment of the disclosed another kind of device that detects clock source failure of the embodiment of the present invention;
Fig. 3 is the structural representation of another embodiment of the disclosed another kind of device that detects clock source failure of the embodiment of the present invention;
Fig. 4 is the structural representation of another embodiment of the disclosed another kind of device that detects clock source failure of the embodiment of the present invention.
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is clearly and completely described, obviously, described embodiment is only the present invention's part embodiment, instead of whole embodiment.Based on the embodiment in the present invention, those of ordinary skill in the art, not making the every other embodiment obtaining under creative work prerequisite, belong to the scope of protection of the invention.
The embodiment of the invention discloses a kind of device that detects clock source failure, as shown in Figure 1, this device can comprise processor 100, and this processor has input 101 and output 102, wherein:
The input 101 of processor 100 is for being connected with clock source, and the present clock source that this clock source is communication equipment, for generation of low frequency pulse signal; The present invention does not limit the clock frequency of low frequency pulse signal, and for example, low frequency pulse signal can be pps pulse per second signal.
The output 100 of processor 100 is for exporting index signal, and whether the low frequency pulse signal that this index signal can telltable clock source produces is lost.
Concrete, this processor starts the low frequency pulse signal of the clock source generation of timing point each time-count cycle for latch;
Wherein, the timing that can circulate of this processor, be more than or equal to the clock cycle of low frequency pulse signal time-count cycle, it should be noted that, can be the clock cycle and the maximum frequency deviation sum that allows this clock source to produce of this clock source this time-count cycle, specifically can set according to actual conditions, the present invention does not limit.
For example, the clock cycle of low frequency pulse signal is 1 second, and the maximum frequency deviation that allows this clock source to produce is the clock cycle 10, and so, be 1.1 seconds this time-count cycle.
This processor starts after low frequency pulse signal that the clock source of timing point produces for latch each time-count cycle, can be within time-count cycle, detect current low frequency pulse signal that clock source produces whether always identical with the low frequency pulse signal of institute latch; If so, export the first index signal; If not, output the second index signal;
It should be noted that, clock source in normal operation,, in the situation that not breaking down, can not lost low frequency pulse signal, all can produce low level pulse signal and high level pulse signal in each clock cycle internal clock source; So, current low frequency pulse signal is can't be always identical with the low frequency pulse signal of institute latch, also can have the situation different from the low frequency pulse signal of institute latch.
For example, within a certain clock cycle, the low frequency pulse signal of institute's latch is low level pulse signal, and within this clock cycle, and the current low frequency pulse signal that clock source produces is first for being high electric impulse signal after low level pulse signal.
And clock source is under abnormal operating state, in the situation that breaking down, can lose some low frequency pulse signal, may only produce low level pulse signal or only produce high level pulse signal in some clock cycle internal clock source, in this case, current low frequency pulse signal is can be always identical with the low frequency pulse signal of institute latch.
For example, within a certain clock cycle, the low frequency pulse signal of institute's latch is low level pulse signal, and within this clock cycle, the current low frequency pulse signal that clock source produces is low level pulse signal always.
Therefore whether always identical with the low frequency pulse signal of institute latch, processor can be by within time-count cycle, detect current low frequency pulse signal that clock source produces, determines whether the low frequency pulse signal that clock source produces is lost.
Wherein, the first index signal is used to indicate low frequency pulse signal and loses, and loses and the second index signal is used to indicate low frequency pulse signal.
In embodiments of the present invention, the device that detects clock source failure can comprise processor, the input of this processor is for being connected with clock source, and output is used for exporting index signal, starts the low frequency pulse signal of the described clock source generation of timing point by latch each time-count cycle; And within time-count cycle, detect current low frequency pulse signal that described clock source produces whether always identical with the low frequency pulse signal of institute latch; If so, export the first index signal, described the first index signal is used to indicate described low frequency pulse signal and loses, and in the time that low frequency pulse signal occurs to lose, can confirm that fault has occurred clock source; If not, export the second index signal, described the second index signal is used to indicate described low frequency pulse signal and loses, in the time that low frequency pulse signal is lost, can confirm that clock source does not break down, as can be seen here, the present invention is by determining that whether low frequency pulse signal is lost, and has realized the detection whether clock source is broken down.
In the present invention, processor is within time-count cycle, detect current low frequency pulse signal that described clock source produces whether always the specific implementation identical with the low frequency pulse signal of institute latch have multiple;
As a kind of implementation:
Whether the current low frequency pulse signal that processor can produce for comparison clock source is identical with the low frequency pulse signal of institute's latch, and according to comparative result, generates first signal;
Wherein, current low frequency pulse signal with the low frequency pulse signal of the institute latch whether identical signal of first signal for producing for characterizing clock source, specific implementation is restriction not;
For example, when first signal is low level signal, identical with the low frequency pulse signal of institute latch for characterizing the current low frequency pulse signal that clock source produces; When first signal is high level signal, different from the low frequency pulse signal of institute latch for characterizing the current low frequency pulse signal that clock source produces;
Or, when first signal is high level signal, identical with the low frequency pulse signal of institute latch for characterizing the current low frequency pulse signal that clock source produces; When first signal is low level signal, different from the low frequency pulse signal of institute latch for characterizing the current low frequency pulse signal that clock source produces.
When processor determines that first signal, for the low frequency pulse signal for characterizing current low frequency pulse signal and institute latch is when different, generates the 3rd signal, and can export the second index signal according to the 3rd signal;
It should be noted that, clock source in normal operation, does not break down in situation, and clock source all can produce high level pulse signal and low level pulse signal in each clock cycle.That is to say, if clock source is not lost low frequency pulse signal, can determine that first signal changes within time-count cycle, it is identical with the low frequency pulse signal of institute latch to be that first signal not only characterized current low frequency pulse signal, also characterizes current low frequency pulse signal different from the low frequency pulse signal of institute latch.Therefore, as long as processor determines that first signal, for the low frequency pulse signal for characterizing current low frequency pulse signal and institute latch is when different, generates the 3rd signal; And export the second index signal according to the 3rd signal, to indicate low frequency pulse signal to lose.
When processor determines that first signal, for the low frequency pulse signal for characterized current low frequency pulse signal and institute latch is always when identical, generates secondary signal, and can export the first index signal according to secondary signal;
It should be noted that, clock source, at abnormal operating state, breaks down in situation, and clock source can only produce high level pulse signal or low level pulse signal in some clock cycle.That is to say, if the low frequency pulse signal that clock source produces is lost, can determine that first signal does not change within time-count cycle, first signal is for identical with the low frequency pulse signal of institute latch for characterize current low frequency pulse signal always.Therefore, processor is determining that first signal, for the low frequency pulse signal for characterize current low frequency pulse signal and institute latch is always when identical, generates secondary signal; And export the first index signal according to this secondary signal, to indicate low frequency pulse signal to lose.
As another kind of implementation:
Whether the current low frequency pulse signal that processor can produce for comparison clock source is identical with the low frequency pulse signal of institute's latch, and according to comparative result, generates first signal; And within time-count cycle, whether always identically with default standard signal detect first signal;
Wherein, processor is preset with standard signal, this standard signal signal identical with the low frequency pulse signal of institute latch that be the current low frequency pulse signal that produces of the described clock source of sign, and concrete implementation is restriction not;
For example, when first signal is low level signal, identical with the low frequency pulse signal of institute latch for characterizing the current low frequency pulse signal that clock source produces; When first signal is high level signal, different from the low frequency pulse signal of institute latch for characterizing the current low frequency pulse signal that clock source produces; Accordingly, default standard signal is low level signal;
Or, when first signal is high level signal, identical with the low frequency pulse signal of institute latch for characterizing the current low frequency pulse signal that clock source produces; When first signal is low level signal, different from the low frequency pulse signal of institute latch for characterizing the current low frequency pulse signal that clock source produces; Accordingly, default standard signal is high level signal.
When processor is in the time detecting that within time-count cycle first signal is always identical with default standard signal, export the first index signal, to indicate low frequency pulse signal to lose; In the time detecting that first signal is not always identical with default standard signal, for example, can first signal can be first identical with default standard signal, rear difference, exports the second index signal, to indicate low frequency pulse signal to lose.
In actual applications, detecting clock source failure device may be different to the susceptibility of different low frequency pulse signals, and therefore, in the present invention, processor determines whether low frequency pulse signal the also difference of standard of losing occurs;
In the time that detection clock source failure device is high to low frequency pulse signal susceptibility, processor can be within each time-count cycle, detect current low frequency pulse signal that clock source produces whether always identical with the low frequency pulse signal of institute latch, if so, export the first index signal; If not, export the second index signal;
In aforesaid way, if processor determine within a certain time-count cycle, low frequency pulse signal is always identical with the low frequency pulse signal of institute latch, determines that loss has occurred low frequency pulse signal, now, output the first index signal;
For the ease of understanding, describe with an example, suppose to start in a certain time-count cycle timing point, processor latch low level pulse signal; And within this time-count cycle, the current low frequency pulse signal that clock source produces is low level pulse signal always, so, can determine that loss has occurred low frequency pulse signal, now exports the first index signal; And if within this time-count cycle, the current low frequency pulse signal that clock source produces be first after low level pulse signal for high level pulse signal, so, can determine that low frequency pulse signal do not lose within this time-count cycle, now, export the second index signal.
When detecting clock source failure device when low to low frequency pulse signal susceptibility, the current low frequency pulse signal that processor can produce at clock source and the low frequency pulse signal of institute latch continue the identical time while reaching Preset Time, export the first index signal; Otherwise, output the second index signal.
Concrete, whether always identical with the low frequency pulse signal of institute latch processor, within time-count cycle, detect current low frequency pulse signal that clock source produces; If so, start timing, and in the time that timing time reaches Preset Time, output the first index signal; If not, timing time is carried out to zero clearing, and export the second index signal.
Wherein, Preset Time can be set according to actual conditions, and the present invention is concrete restriction not, and for example, time-count cycle, while being 1.1 seconds, Preset Time can be 10 seconds.
For example, processor within a certain time-count cycle, detects when current low frequency pulse signal that clock source produces is always identical with the low frequency pulse signal that starts the latch of timing point institute in this time-count cycle, starts timing; And within after this multiple continuous time-count cycles, the current low frequency pulse signal that clock source generation all detected is always identical with the low frequency pulse signal that starts the latch of timing point institute corresponding time-count cycle, continue so timing, in the time that definite timing time reaches Preset Time, output the first index signal; And before timing time does not reach Preset Time, if within a certain time-count cycle, detect when current low frequency pulse signal that clock source produces is always identical with the low frequency pulse signal that starts the latch of timing point institute in corresponding time-count cycle, so, timing time is carried out to zero clearing, and export the second index signal.
The invention also discloses the another kind of device that detects clock source failure, wherein, the present clock source that this clock source is communication equipment, for generation of low frequency pulse signal, the present invention does not limit the clock frequency of low frequency pulse signal, and for example, low frequency pulse signal can be pps pulse per second signal.
As shown in Figure 2, this device can comprise: the first timer 200, the first register 300, detecting unit 400, wherein:
The first timer 200, for the timing that circulates, wherein, is more than or equal to the clock cycle of described low frequency pulse signal the time-count cycle of the first timer; It should be noted that, be specifically as follows the clock cycle and the maximum frequency deviation sum that allows this clock source to produce of this clock source this time-count cycle, specifically can set according to actual conditions, the present invention does not limit.
For example, the clock cycle of low frequency pulse signal is 1 second, and the maximum frequency deviation that allows this clock source to produce is the clock cycle 10, and so, be 1.1 seconds this time-count cycle.
The first register 300 is connected with the first timer 200 and clock source respectively, and the first register starts the low frequency pulse signal of the clock source generation of timing point each time-count cycle for latch; That is to say the low frequency pulse signal that the first register produces in the beginning timing point latch clock source of each time-count cycle of the first timer.
Detecting unit 400 is connected with the first timer 200, the first register 300 and clock source respectively;
Wherein, after the low frequency pulse signal that the first register latch clock source produces, the low frequency pulse signal of institute's latch can be sent to detecting unit; And detecting unit is within time-count cycle, detect current low frequency pulse signal that clock source produces whether always identical with the low frequency pulse signal of institute latch; If so, export the first index signal; If not, output the second index signal.
It should be noted that, clock source in normal operation,, in the situation that not breaking down, can not lost low frequency pulse signal, and clock source all can produce low level pulse signal and high level pulse signal within each clock cycle; So, current low frequency pulse signal is can't be always identical with the low frequency pulse signal of institute latch, also can have the situation different from the low frequency pulse signal of institute latch.
For example, within a certain clock cycle, the low frequency pulse signal of institute's latch is low level pulse signal, and within this clock cycle, and the current low frequency pulse signal that clock source produces is first for being high electric impulse signal after low level pulse signal.
And clock source is under abnormal operating state, in the situation that breaking down, can lose some low frequency pulse signal, be that clock source may only produce low level pulse signal or only produce high level pulse signal within some clock cycle, in this case, current low frequency pulse signal is can be always identical with the low frequency pulse signal of institute latch.
For example, within a certain clock cycle, the low frequency pulse signal of institute's latch is low level pulse signal, and within this clock cycle, the current low frequency pulse signal that clock source produces is low level pulse signal always.
Therefore whether always identical with the low frequency pulse signal of institute latch, detecting unit can be by within time-count cycle, detect current low frequency pulse signal that clock source produces, determines whether the low frequency pulse signal that clock source produces is lost.
Wherein, the first index signal is used to indicate low frequency pulse signal and loses, and loses and the second index signal is used to indicate low frequency pulse signal.
In embodiments of the present invention, the device that detects clock source failure can comprise the first register, the first timer and detecting unit, the first timer is used for the timing that circulates, and the first register starts the low frequency pulse signal of the clock source generation of timing point each time-count cycle for latch; Whether always identical with the low frequency pulse signal of institute latch detecting unit is within time-count cycle, detect current low frequency pulse signal that clock source produces; If so, export the first index signal, described the first index signal is used to indicate described low frequency pulse signal and loses, and in the time that low frequency pulse signal occurs to lose, can confirm that fault has occurred clock source; If not, export the second index signal, described the second index signal is used to indicate described low frequency pulse signal and loses, in the time that low frequency pulse signal is lost, can confirm that clock source does not break down, as can be seen here, the present invention is by determining that whether low frequency pulse signal is lost, and has realized the detection whether clock source is broken down.
Another embodiment of the present invention also provides a kind of device that detects clock source failure, and as shown in Figure 3, this device can comprise the first timer 200, the first register 300 and detecting unit 400; Detecting unit 400 comprises logical circuit 401, the second register 402, the 3rd register 403; Wherein:
The first timer 200, for the timing that circulates, wherein, is more than or equal to the clock cycle of described low frequency pulse signal the time-count cycle of the first timer; It should be noted that, be specifically as follows the clock cycle and the maximum frequency deviation sum that allows this clock source to produce of this clock source this time-count cycle, specifically can set according to actual conditions, the present invention does not limit.
The first register 300 is connected with the first timer 200 and clock source respectively, and the first register starts the low frequency pulse signal of the clock source generation of timing point each time-count cycle for latch; That is to say the low frequency pulse signal that the first register produces in the beginning timing point latch clock source of each time-count cycle of the first timer.
The first input end of logical circuit 401 is connected with clock source, and the second input is connected with the first register 300; Whether the current low frequency pulse signal that this logical circuit produces for comparison clock source is identical with the low frequency pulse signal of institute's latch, and according to comparative result, output first signal;
Wherein, the specific implementation form of this logical circuit does not limit, and for example, can be XOR gate logical circuit or same or gate logic;
If logical circuit is XOR gate logical circuit, so, in the time that the low frequency pulse signal of the more current low frequency pulse signal of XOR gate logical circuit and institute latch is identical, the first signal of output is low level signal; In the time that the low frequency pulse signal of the more current low frequency pulse signal of XOR gate logical circuit and institute latch is different, the first signal of output is high level signal;
If logical circuit be with or gate logic, so, when with or the low frequency pulse signal of the more current low frequency pulse signal of gate logic and institute latch when identical, the first signal of output is high level signal; When with or the low frequency pulse signal of the more current low frequency pulse signal of gate logic and institute latch when different, the first signal of output is low level signal.
The second register 402 is connected with output, first timer of logical circuit respectively;
The output signal of this second register starts timing point in each time-count cycle and is set to secondary signal;
Wherein, the second register is within time-count cycle, and the first signal that is recorded to logical circuit output, for the low frequency pulse signal for characterizing current low frequency pulse signal and institute latch is when different, is exported the 3rd signal; The first signal that is recorded to logical circuit output, for the low frequency pulse signal for characterize described current low frequency pulse signal and institute latch is always when identical, keeps exporting secondary signal;
Wherein, specific implementation form the present invention of secondary signal and the 3rd signal does not limit, and can set according to actual conditions;
For example, if when first signal is low level signal, identical with the low frequency pulse signal of institute latch for characterizing current low frequency pulse signal; When first signal is high level signal, different from the low frequency pulse signal of institute latch for characterizing current low frequency pulse signal; So, secondary signal can be high level signal, and the 3rd signal can be low level signal;
Or, if when first signal is high level signal, identical with the low frequency pulse signal of institute latch for characterizing current low frequency pulse signal; When first signal is low level signal, different from the low frequency pulse signal of institute latch for characterizing current low frequency pulse signal; So, secondary signal can be low level signal, and the 3rd signal can be high level signal.
It should be noted that, clock source in normal operation, does not break down in situation, and clock source all can produce high level pulse signal and low level pulse signal in each clock cycle; So, current low frequency pulse signal is can't be always identical with the low frequency pulse signal of institute latch, also can have the situation different from the low frequency pulse signal of institute latch.In this case, the first signal of logical circuit output changes, it is identical with the low frequency pulse signal of institute latch to be that first signal not only characterized current low frequency pulse signal, also characterizes current low frequency pulse signal different from the low frequency pulse signal of institute latch.Therefore, the second register, being recorded to first signal for the low frequency pulse signal for characterizing current low frequency pulse signal and institute latch is when different, is exported the 3rd signal.
For example, if when first signal is low level signal, identical with the low frequency pulse signal of institute latch for characterizing current low frequency pulse signal; When first signal is high level signal, different from the low frequency pulse signal of institute latch for characterizing current low frequency pulse signal; So, in the time that the second register is recorded to first signal and was high level signal, export the 3rd signal.
It should be noted that, clock source, at abnormal operating state, breaks down in situation, and clock source can only produce high level pulse signal or low level pulse signal in some clock cycle, so, current low frequency pulse signal is can be always identical with the low frequency pulse signal of institute latch.In this case, the first signal of logical circuit output does not change, and first signal is for identical with the low frequency pulse signal of institute latch for characterize current low frequency pulse signal always.Therefore, the second register, being recorded to first signal for the low frequency pulse signal for characterize current low frequency pulse signal and institute latch is always when identical, keeps output secondary signal.
For example, if when first signal is low level signal, identical with the low frequency pulse signal of institute latch for characterizing current low frequency pulse signal; When first signal is high level signal, different from the low frequency pulse signal of institute latch for characterizing current low frequency pulse signal; So, in the time that the second register is recorded to first signal always for low level signal, keep output secondary signal.
The 3rd register 403 is connected with the second register 402 and the first timer 200 respectively;
Wherein, the 3rd register is for the signal of beginning timing point latch the second register output in each time-count cycle, and in the time that the signal of institute's latch is secondary signal, output the first index signal, to indicate low frequency pulse signal that loss has occurred; In the time that the signal of institute's latch is the 3rd signal, output the second index signal, to indicate low frequency pulse signal to lose.
Should be noted, there is delay in register in the time of saltus step, and therefore, even if the second register is set to secondary signal at the beginning timing point of time-count cycle by the 3rd signal, the 3rd register also can be latched into the 3rd signal at the beginning timing point of time-count cycle.
In actual applications, detecting clock source failure device may be different to the susceptibility of different low frequency pulse signals, therefore, in the present invention, determines whether low frequency pulse signal the also difference of standard of losing occurs;
When detecting clock source failure device when high to low frequency pulse signal susceptibility, export the first index signal or the second index signal can determine whether low frequency pulse signal is lost by detecting unit.
In the time that detection clock source failure device is low to low frequency pulse signal susceptibility, this device can also comprise the second timer, as shown in Figure 4, this device can comprise: the first timer 200, the first register 300, detecting unit 400, the second timer 500, wherein:
The first timer 200 is for the timing that circulates.
The first register 300 is connected with the first timer 200 and clock source respectively, and the first register starts the low frequency pulse signal of the clock source generation of timing point each time-count cycle for latch;
Detecting unit 400 is connected with the first timer 200, the first register 300 and clock source respectively;
Wherein, after the low frequency pulse signal that the first register latch clock source produces, the low frequency pulse signal of institute's latch can be sent to detecting unit; And detecting unit is within time-count cycle, detect current low frequency pulse signal that clock source produces whether always identical with the low frequency pulse signal of institute latch; If so, export the first index signal; If not, output the second index signal;
The second timer 500 is connected with detecting unit 400;
Wherein, the second timer, in the time that detecting unit is exported the first index signal, starts timing;
In the time that detecting unit is exported the second index signal, zero clearing.
It should be noted that, the corresponding device of Fig. 3 also can comprise the second timer, so, the second timer can be connected with the 3rd register, in the time that the 3rd register is exported the first index signal, starts timing, in the time that the 3rd register is exported the second index signal, zero clearing.
Concrete, the second timer starts timing in the time that detecting unit is exported the first index signal, if detecting unit is exported the first index signal continuous multiple time-count cycles always, so, this second timer can continue timing, in the time that timing time reaches Preset Time, can assert that loss has occurred low frequency pulse signal, and then can determine that clock source breaks down.
And do not reaching before Preset Time at the second timing time, if within a certain time-count cycle, detecting unit is exported the second index signal, the second timer zero clearing so, now, can assert that low frequency pulse signal loses, and then can determine that clock source does not break down.
In this specification, each embodiment adopts the mode of going forward one by one to describe, and what each embodiment stressed is and the difference of other embodiment, between each embodiment identical similar part mutually referring to.For the disclosed device of embodiment, because it corresponds to the method disclosed in Example, so description is fairly simple, relevant part illustrates referring to method part.
To the above-mentioned explanation of the disclosed embodiments, make professional and technical personnel in the field can realize or use the present invention.To be apparent for those skilled in the art to the multiple amendment of these embodiment, General Principle as defined herein can, in the situation that not departing from the spirit or scope of the present invention, realize in other embodiments.Therefore, the present invention will can not be restricted to these embodiment shown in this article, but will meet the widest scope consistent with principle disclosed herein and features of novelty.
Claims (9)
1. a device that detects clock source failure, is characterized in that, comprises processor, and described processor has input and output, and described input is for being connected with described clock source, and described clock source is for generation of low frequency pulse signal; Described output is used for exporting index signal;
Described processor starts the low frequency pulse signal of the described clock source generation of timing point each time-count cycle for latch; And within time-count cycle, detect current low frequency pulse signal that described clock source produces whether always identical with the low frequency pulse signal of institute latch; If so, export the first index signal, described the first index signal is used to indicate described low frequency pulse signal and loses; If not, output the second index signal, described the second index signal is used to indicate described low frequency pulse signal and loses;
Wherein, be more than or equal to the clock cycle of described low frequency pulse signal described time-count cycle.
2. whether always identical with the low frequency pulse signal of institute latch device according to claim 1, is characterized in that, described processor is within time-count cycle, detect current low frequency pulse signal that described clock source produces; If so, export the first index signal; If not, output the second index signal, is specially,
Whether the current low frequency pulse signal that described processor produces for more described clock source is identical with the low frequency pulse signal of institute's latch, and according to comparative result, generates first signal; Within time-count cycle, determine that described first signal, for the low frequency pulse signal for characterizing described current low frequency pulse signal and institute latch is when different, generates the 3rd signal; Determine that described first signal, for the low frequency pulse signal for characterize described current low frequency pulse signal and institute latch is always when identical, generates secondary signal; And export the first index signal according to described secondary signal, export the second index signal according to described the 3rd signal.
3. whether always identical with the low frequency pulse signal of institute latch device according to claim 1, is characterized in that, described processor is within time-count cycle, detect current low frequency pulse signal that described clock source produces; If so, export the first index signal; If not, output the second index signal, is specially:
Whether the current low frequency pulse signal that described processor produces for more described clock source is identical with the low frequency pulse signal of institute's latch, and according to comparative result, generates first signal; Within time-count cycle, whether always identically with default standard signal detect described first signal, the described standard signal signal identical with the low frequency pulse signal of institute latch that be the current low frequency pulse signal that produces of the described clock source of sign;
If so, export the first index signal; If not, output the second index signal.
4. according to the device described in claim 1～3 any one, it is characterized in that, described processor is exported the first index signal and is specially:
The current low frequency pulse signal that described processor produces at described clock source and the low frequency pulse signal of institute latch continue the identical time while reaching Preset Time, export the first index signal.
5. device according to claim 3, is characterized in that,
In the time that the low frequency pulse signal of described current low frequency pulse signal and institute latch is identical, described first signal is low level signal;
In the time that the low frequency pulse signal of described current low frequency pulse signal and institute latch is different, described first signal is high level signal;
Described standard signal is low level signal;
Or in the time that the low frequency pulse signal of described current low frequency pulse signal and institute latch is identical, described first signal is high level signal;
In the time that the low frequency pulse signal of described current low frequency pulse signal and institute latch is different, described first signal is low level signal;
Described standard signal is high level signal.
6. a device that detects clock source failure, is characterized in that, described clock source is for generation of low frequency pulse signal, and this device comprises:
For the first timer of the timing that circulates, be more than or equal to the clock cycle of described low frequency pulse signal the time-count cycle of described the first timer;
The first register being connected with described the first timer with described clock source respectively, described the first register starts the low frequency pulse signal of the described clock source generation of timing point each time-count cycle for latch;
The detecting unit being connected with described clock source, described the first timer and described the first register respectively;
Whether always identical with the low frequency pulse signal of institute latch wherein, described detecting unit is within time-count cycle, detect current low frequency pulse signal that described clock source produces; If so, export the first index signal, described the first index signal is used to indicate described low frequency pulse signal and loses; If not, output the second index signal, described the second index signal is used to indicate described low frequency pulse signal and loses.
7. device according to claim 6, is characterized in that, described detecting unit comprises:
First input end is connected with described clock source, the logical circuit that the second input is connected with described the first register, whether the current low frequency pulse signal that described logical circuit produces for more described clock source is identical with the low frequency pulse signal of institute's latch, and according to comparative result, output first signal;
The second register being connected with the output of logical circuit, described the first timer respectively, the output signal of described the second register is set to secondary signal in the time that start timing point each time-count cycle;
Described the second register is within time-count cycle, and the first signal that is recorded to described logical circuit output, for the low frequency pulse signal for characterizing described current low frequency pulse signal and institute latch is when different, is exported the 3rd signal; The first signal that is recorded to the output of described logical circuit, for the low frequency pulse signal for characterize described current low frequency pulse signal and institute latch is always when identical, keeps exporting secondary signal;
The 3rd register being connected with described the second register with described the first timer respectively, for the signal in the second register output described in the beginning timing point latch of each time-count cycle, and in the time that the signal of institute's latch is secondary signal, export the first index signal, in the time that the signal of institute's latch is the 3rd signal, output the second index signal.
8. device according to claim 6, is characterized in that, also comprises the second timer being connected with described detecting unit;
Described the second timer, in the time that described detecting unit is exported the first index signal, starts timing;
In the time that described detecting unit is exported the second index signal, zero clearing.
9. device according to claim 6, is characterized in that, described logical circuit is XOR gate logical circuit;
In the time that the low frequency pulse signal of described current low frequency pulse signal and institute latch is identical, described first signal is low level signal;
In the time that the low frequency pulse signal of described current low frequency pulse signal and institute latch is different, described first signal is high level signal;
Described secondary signal is high level signal; Described the 3rd signal is low level signal;
Or described logical circuit is same or gate logic;
In the time that the low frequency pulse signal of described current low frequency pulse signal and institute latch is identical, described first signal is high level signal;
In the time that the low frequency pulse signal of described current low frequency pulse signal and institute latch is different, described first signal is low level signal;
Described secondary signal is low level signal; Described the 3rd signal is high level signal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410160364.6A CN103888109A (en) | 2014-04-21 | 2014-04-21 | Circuit for detecting clock source fault |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410160364.6A CN103888109A (en) | 2014-04-21 | 2014-04-21 | Circuit for detecting clock source fault |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN103888109A true CN103888109A (en) | 2014-06-25 |
Family
ID=50956850
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410160364.6A Pending CN103888109A (en) | 2014-04-21 | 2014-04-21 | Circuit for detecting clock source fault |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN103888109A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109412581A (en) * | 2017-08-18 | 2019-03-01 | 杭州晶华微电子有限公司 | A kind of clock failure of oscillation detection circuit |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN2559168Y (en) * | 2002-04-16 | 2003-07-02 | 华为技术有限公司 | Circuit for detection of clock loss |
| CN1474508A (en) * | 2003-07-02 | 2004-02-11 | 西安大唐电信有限公司 | High frequency clock pulse loss monitoring detection circuit with low frequency clock |
| US20050012525A1 (en) * | 2001-08-03 | 2005-01-20 | Greg Starr | Clock loss detection and switchover circuit |
-
2014
- 2014-04-21 CN CN201410160364.6A patent/CN103888109A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050012525A1 (en) * | 2001-08-03 | 2005-01-20 | Greg Starr | Clock loss detection and switchover circuit |
| CN2559168Y (en) * | 2002-04-16 | 2003-07-02 | 华为技术有限公司 | Circuit for detection of clock loss |
| CN1474508A (en) * | 2003-07-02 | 2004-02-11 | 西安大唐电信有限公司 | High frequency clock pulse loss monitoring detection circuit with low frequency clock |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109412581A (en) * | 2017-08-18 | 2019-03-01 | 杭州晶华微电子有限公司 | A kind of clock failure of oscillation detection circuit |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US9231576B1 (en) | Device and method for clock signal loss detection | |
| EP3321839A1 (en) | Method and detection circuit for detecting security chip operating state | |
| US9747244B2 (en) | Clockless virtual GPIO | |
| EP3223145A1 (en) | Data reading circuit | |
| JP2013061863A (en) | Electronic control device | |
| US20140132315A1 (en) | Integrated circuit with degradation monitoring | |
| US8525597B2 (en) | Clock frequency overshoot detection circuit | |
| US9899992B1 (en) | Low power adaptive synchronizer | |
| EP3289471B1 (en) | Communication between integrated circuits | |
| CN103888109A (en) | Circuit for detecting clock source fault | |
| US8878569B1 (en) | Self-recovering bus signal detector | |
| CN112462160B (en) | Clock surge detection circuit | |
| CN111384933B (en) | Clock pulse frequency attack detection system | |
| WO2013005313A1 (en) | Signal processing device | |
| CN203951451U (en) | A kind of circuit that detects clock source failure | |
| KR20140036284A (en) | Frequency divider and method for dividing frequency of frequency divider | |
| JP4819707B2 (en) | Redundant computing system and computing unit | |
| CN108089631A (en) | A kind of clock circuit for detecting for microcontroller chip | |
| US9054685B2 (en) | Programmable bus signal hold time without system clock | |
| KR101671956B1 (en) | Device and method for resetting of system | |
| CN107390045B (en) | Crystal oscillator detection circuit and crystal oscillator detection method | |
| JP2019215947A (en) | Storage device and operation method thereof | |
| CN207867388U (en) | A kind of clock circuit for detecting for microcontroller chip | |
| CN103888108A (en) | Data decoding method and device | |
| KR102343211B1 (en) | laser clock signal generator |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20140625 |
|
| RJ01 | Rejection of invention patent application after publication |