CN103887309B

CN103887309B - Semiconductor device, the manufacture method of semiconductor device, power supply and high frequency amplifier

Info

Publication number: CN103887309B
Application number: CN201310559631.2A
Authority: CN
Inventors: 山田敦史
Original assignee: Fujitsu Ltd
Current assignee: Fujitsu Ltd
Priority date: 2012-12-21
Filing date: 2013-11-12
Publication date: 2016-11-30
Anticipated expiration: 2033-11-12

Abstract

The present invention relates to a kind of semiconductor device, a kind of method, a kind of power supply and a kind of high frequency amplifier being used for producing the semiconductor devices.The invention provides a kind of semiconductor device, described semiconductor device includes: the first transistor, described the first transistor includes that first gate electrode, the first source electrode, the first drain electrode and the first nitride semiconductor layers, described first nitride semiconductor layers include the first electron transit layer and the first electron supply layer；Transistor seconds, described transistor seconds includes second gate electrode, the second source electrode, the second drain electrode and the second nitride semiconductor layers, described second nitride semiconductor layers includes the second electron transit layer and the second electron supply layer, described second electric leakage extremely also serves as the public electrode of described first source electrode, and described second electron transit layer has the part being positioned under described second gate electrode and comprising p-type dopant；And p-type dopant diffusion impervious layer.

Description

Semiconductor device, the manufacture method of semiconductor device, power supply and high frequency amplifier

Technical field

Embodiment discussed herein relates to a kind of semiconductor device, one for manufacturing quasiconductor The method of device, a kind of power supply and a kind of high frequency amplifier.

Background technology

Nitride compound semiconductor device has as presented high saturated electrons speed and the characteristic of broad-band gap.Profit Promote that there is high withstanding voltage and the exploitation of high-power device by such characteristic.For this tool There is the example of the nitride compound semiconductor device that the exploitation of high withstanding voltage and high-power device used Including field-effect transistor, specifically, HEMT (HEMT).

The example of HEMT is the GaN-HEMT with HEMT-structure (AlGaN/GaN-HEMT), in this HEMT-structure, GaN electron transit layer sets It is equipped with AlGaN electron supply layer.In GaN-HEMT, due to AlGaN in AlGaN And differences between lattice constant between GaN and produce stress, and this stress causes piezoelectric polarization.Should The spontaneous polarization of piezoelectric polarization and AlGaN results in the two-dimensional electron gas (2DEG) of high concentration. Therefore, this GaN-HEMT makes it possible to exploitation and has high withstanding voltage and high-power device.

But, in GaN-HEMT, high concentration 2DEG makes operating difficulties under normal off pattern. For making it possible under normal off pattern in the technology of operation, such as, immediately below etch-gate electrode The part of electron supply layer is to interrupt the flowing of 2DEG.This technology is referred to herein as the first skill Art.Additionally, at another for making it possible under normal off pattern in the technology of operation, such as, Gate electrode is formed immediately below p-type GaN layer to offset 2DEG.This technology is referred to herein as Two technology.Such structure is also known as p-GaN grid structure.Additionally, such as, make being used for Obtain and can operate under normal off pattern, and make it possible to realize low source resistance and in high operation In the technology operating the two under voltage, the 2DEG doped with p-type dopant is reduced layer and mixes The miscellaneous conductive formation having n-type dopant is formed as making it cover at electron supply layer at source electrode and grid Part between electrode.This technology is referred to herein as the 3rd technology.Additionally, such as, it is being used for Make it possible to operate and make it possible to realize low on-resistance and high withstanding voltage under normal off pattern In the technology of the two, the part that electron transit layer is positioned under source electrode and gate electrode is mixed doped with p-type Miscellaneous dose.This technology is referred to herein as the 4th technology.

But, in the first technology, the part of etching damage nomal closed type transistor side under the gate electrode, This causes the increase of conducting resistance and leakage current.Therefore, the first technology is for making it possible at normal off mould It is unpractical for realizing stable operation with low on-resistance under formula.In the second technology, in order at normal off Operate under pattern, p-type GaN layer offset 2DEG and make to reduce the thickness of electron supply layer； But, in which case it is difficult to be capable of low on-resistance and high withstanding voltage.Specifically, In the case of in order to operate under normal off pattern and reduce the thickness of electron supply layer, add Distance between gate electrode and drain electrode is to realize high withstanding voltage；But, gate electrode and drain electrode it The increase of spacing causes the increase of conducting resistance.Thus, the second technology is for making it possible at normal off Operate under pattern and make it possible to realize low on-resistance and high withstanding voltage is unaccommodated.

In the 3rd technology, owing to interpolation to 2DEG reduces the p-type dopant of layer in electronics supply Electron supply layer or electron transit layer is diffused to during the crystal growth of layer or electron transit layer, thus the Three technology for make it possible to operate under normal off pattern and make it possible to realize low on-resistance and High withstanding voltage is unpractical.In the 3rd technology, such as, even if adding electron supply layer Distance between thickness and gate electrode and drain electrode is to realize high withstanding voltage and low on-resistance, so Method can not run well to keep low-level conducting resistance.Further, since the 3rd technology Layer and the structure of conductive formation is reduced including the most only stacking 2DEG, so electron mobility is low, And channel resistance is high；Therefore, conducting resistance is the most successfully reduced.

In the 4th technology, add the p-type dopant of the part to electron transit layer in electron transit Other parts of electron transit layer are diffused to during the crystal growth of layer.Therefore, for making it possible to Operate and be capable of low on-resistance under normal off pattern and high withstanding voltage is unpractical.? In four technology, such as, even if increasing between thickness and gate electrode and the drain electrode of electron supply layer Distance is to realize high withstanding voltage and low on-resistance, and such method can not be run to protect well Hold low-level conducting resistance.

The following is list of references:

[document 1] Japanese Laid-Open Patent Publication the 2009-76845th,

[document 2] Japanese Laid-Open Patent Publication the 2007-19309th,

[document 3] International Publication the WO2010/016564th, and

[document 4] Japanese Laid-Open Patent Publication the 2004-260140th.

Summary of the invention

According to an aspect of the present invention, semiconductor device include the first transistor, transistor seconds and P-type dopant diffusion impervious layer: described the first transistor include first gate electrode, the first source electrode, First drain electrode and the first nitride semiconductor layers, described first nitride semiconductor layers includes One electron transit layer and the first electron supply layer；Described transistor seconds include second gate electrode, second Source electrode, the second drain electrode and the second nitride semiconductor layers, described second nitride-based semiconductor is folded Layer include the second electron transit layer and the second electron supply layer, described second drain electrode be also serve as described The public electrode of the first source electrode, described second electron transit layer have be positioned at described second gate electrode it The part descended and comprise p-type dopant；In described p-type dopant diffusion impervious layer, described second Nitride semiconductor layers is disposed above described first nitride semiconductor layers, wherein said p Type doping agent diffusion blocking layer is folded between the first nitride semiconductor layers and the second nitride-based semiconductor Between Ceng, and described first gate electrode and described second source electrode electrically coupled to each other brilliant to set up first Body pipe is connected (cascode connection) with the cascade of transistor seconds.

Element by being particularly pointed out in the claims and combination are realized and obtain the present invention's Purpose and advantage.

Should be appreciated that both foregoing general description and detailed description below are for claimed The present invention be all exemplary and explanat rather than restrictive.

Accompanying drawing explanation

Fig. 1 is the diagrammatic cross-sectional of the structure showing the semiconductor device according to the first embodiment Face view；

Fig. 2 A to 2D is to show the side being used for producing the semiconductor devices according to the first embodiment The schematic cross-sectional view of method；

Fig. 3 A to 3C is to show partly leading for manufacturing of change programme according to the first embodiment The schematic schematic cross-sectional view of the method for body device；

Fig. 4 A and 4B is to show partly leading for manufacturing of change programme according to the first embodiment The method of body device and the schematic cross-sectional view of the structure of semiconductor device；

Fig. 5 A and 5B be show the first change programme according to the first embodiment for manufacturing The method of semiconductor device and the schematic cross-sectional view of the structure of semiconductor device；

Fig. 6 A and 6B be show the second change programme according to the first embodiment for manufacturing The method of semiconductor device and the schematic cross-sectional view of the structure of semiconductor device；

Fig. 7 is the structure showing the semiconductor device (semiconductor package part) according to the second embodiment The schematic plan view made；

Fig. 8 schematically shows in the power factor included according to the power supply of the second embodiment The configuration of correction (PFC) circuit；And

Fig. 9 schematically shows the structure of the high frequency amplifier according to the 3rd embodiment.

Detailed description of the invention

Will be described with reference to the accompanying drawings the semiconductor device according to embodiment below, for manufacturing this The method of semiconductor device, power supply and high frequency amplifier.

[the first embodiment]

Now with reference to Fig. 1 to Fig. 4 B describe the semiconductor device according to the first embodiment and for The method manufacturing this semiconductor device.

The semiconductor device of the first embodiment is compound semiconductor device, specifically, wherein uses Nitride semi-conductor material and there is high withstanding voltage and high-power device.Also partly lead such Body device is referred to as nitride compound semiconductor device.The semiconductor device of the first embodiment includes wherein using The field-effect transistor of nitride semi-conductor material.Also such field-effect transistor is referred to as nitride Semiconductor field effect transistor.Especially, the semiconductor device of the first embodiment is for wherein to use The GaN device of GaN semi-conducting material；With reference to Fig. 1, this semiconductor device includes for normal open type brilliant Body pipe GaN-HEMT1 and be nomal closed type transistor GaN-HEMT2.In FIG, dotted line table Show that 2DEG, arrow represent current path.

Also normal open transistor npn npn GaN-HEMT is referred to as normal open type HEMT, normal open type HEMT Region or the first transistor.Also nomal closed type transistor GaN-HEMT is referred to as nomal closed type HEMT, Nomal closed type HEMT region or transistor seconds.In the semiconductor device of the first embodiment, will Normal open type HEMT1 and nomal closed type HEMT2 are disposed over identical Semiconductor substrate, will be often Disconnected type HEMT2 is positioned higher than normal open type HEMT1, and by normal open type HEMT1 with often Disconnected type HEMT2 cascade each other connects.

Normal open type HEMT1 includes the first nitride semiconductor layers 5, gate electrode 6, source electrode 7 With drain electrode 8, described first nitride semiconductor layers 5 includes being formed to cover Semiconductor substrate I-GaN the electron transit layer 3 and n-AlGaN electron supply layer 4 of (not shown).Real first Execute in scheme, the n-AlGaN electron supply layer 4 part immediately below source electrode 7 and i-GaN electricity The sub-transit layer 3 part immediately below source electrode 7 is doped with n-type dopant, and these N-shapeds are mixed Hetero moiety is used as N-shaped contact area 9A.Source electrode 7 be formed on N-shaped contact area 9A ( In first embodiment, on the N-shaped contact area of n-AlGaN electron supply layer 4).Similarly, Another part immediately below drain electrode 8 of n-AlGaN electron supply layer 4 and i-GaN electron transit Layer 3 another part immediately below drain electrode 8 are doped with n-type dopant, and the doping of these N-shapeds Part is used as N-shaped contact area 9B.Drain electrode 8 is formed on N-shaped contact area 9B ( In one embodiment, on the N-shaped contact area of n-AlGaN electron supply layer 4).Can pass through The such as ion implanting of n-type dopant such as Si forms N-shaped contact area 9A and 9B.This In the case of, N-shaped contact area 9A and 9B is the district being filled with n-type dopant ion the most wherein Territory.AlN impurity diffusion impervious layer 10 is arranged on the first nitride semiconductor layers 5, and AlN The surface of impurity diffusion impervious layer 10 be coated with such as SiN film 11(passivating film, gate insulator, Or dielectric film).Gate electrode 6 is arranged on SiN film 11.Such structure is that metal insulator is partly led Body (MIS) structure and can be the most to have removed SiN film 11 immediately below gate electrode 6 Schottky (Schottky) structure of part.Although N-shaped contact area 9A in the first embodiment It is separately positioned on immediately below source electrode 7 and drain electrode 8 with 9B, but N-shaped contact area can be omitted The formation of territory 9A and 9B.Furthermore, it is possible to treating shape remove n-AlGaN electron supply layer 4 Source electrode 7 and drain electrode 8 is formed after becoming the part immediately below the position of source electrode 7 and drain electrode 8.

First nitride semiconductor layers 5 also known as compound semiconductor lamination, GaN-HEMT knot Structure, AlGaN/GaN-HEMT structure or GaN-HEMT crystal.First nitride-based semiconductor Lamination 5 can include at least electron transit layer and electron supply layer, and can include other quasiconductors Layer.First nitride semiconductor layers 5 can be such as make it possible to formed field-effect transistor (as Wherein use the field-effect transistor of nitride-based semiconductor) nitride semiconductor layers.I-GaN electricity Sub-transit layer 3 also known as the first electron transit layer.N-AlGaN electron supply layer 4 also known as first Electron supply layer.Gate electrode 6 also known as first gate electrode.Source electrode 7 also known as the first source electrode. Drain electrode 8 also known as the first drain electrode.

In the semiconductor device of the first embodiment, AlN impurity diffusion impervious layer 10 is arranged on On mononitride semiconductor laminated 5.AlN impurity diffusion impervious layer 10 is used for stopping p-type dopant From formation during the crystal growth of n-AlGaN electron supply layer 4 and i-GaN electron transit layer 3 P-GaN electron transit layer 12 on this AlN impurity diffusion impervious layer 10 is diffused into n-AlGaN Electron supply layer 4 and i-GaN electron transit layer 3.Therefore, AlN impurity diffusion impervious layer 10 is also It is referred to as p-type dopant diffusion impervious layer.

In the first embodiment, p-type dopant diffusion impervious layer 10 be AlN layer but the present invention not It is limited to this；Such as, p-type dopant diffusion impervious layer 10 can be AlGaN layer.In other words, P-type dopant diffusion impervious layer 10 can be random layer, as long as this layer comprises AlGaN or AlN i.e. Can.P-type dopant diffusion impervious layer 10 preferably comprise AlGaN that Al content is at least 0.5 or AlN.Specifically, be formed at the n-AlGaN below p-type dopant diffusion impervious layer 10 electricity Sub-supplying layer 4 is compared, Al content (the Al content in p-type dopant diffusion impervious layer 10 Ratio) the biggest.In the first embodiment, such as, p-type dopant diffusion resistance it is formed at The Al content of the n-AlGaN electron supply layer 4 below barrier 10 is 0.3；Due to p-type dopant Diffusion impervious layer 10 is AlN layer, thus be formed at p-type dopant diffusion impervious layer 10 times The n-AlGaN electron supply layer 4 of side is compared, Al in p-type dopant diffusion impervious layer 10 Content is bigger.Therefore, this structure makes it possible to effectively further stop the diffusion of p-type dopant. Additionally, have the p-type dopant diffusion of bigger Al content compared with n-AlGaN electron supply layer 4 Barrier layer 10 presents piezoelectricity and spontaneous polarization largely, and this also gives increase normal open type The effect of the amount of the 2DEG generated in HEMT1.In this case, the amount of 2DEG can be with Increase to the proportional mode that increases of Al content in p-type dopant diffusion impervious layer 10.

Nomal closed type HEMT2 is configured to cover a part for AlN impurity diffusion impervious layer 10.Often Disconnected type HEMT2 includes having p-GaN electron transit layer 12 and n-AlGaN electron supply layer 13 The second nitride semiconductor layers 14 of hierarchy.Second nitride semiconductor layers 14 is determined Position becomes the first nitride semiconductor layers 5, the wherein AlN included higher than normal open type HEMT1 Impurity diffusion impervious layer 10 is folded between the second nitride semiconductor layers 14 and the first nitride-based semiconductor Between layer 5.

Gate electrode 15 and source electrode 16 are configured to cover the second nitride semiconductor layers 14, and And drain electrode 17 is arranged on the side of the second nitride semiconductor layers 14.Drain electrode 17 is for also Public electrode 18 as the source electrode 7 of normal open type HEMT1.In this case, normal open type The source electrode 7 of HEMT1 and the drain electrode 17(of nomal closed type HEMT2 they be public electrode 18) By with for forming the drain electrode 8 of normal open type HEMT1 and the source electrode 16 of nomal closed type HEMT2 The metal that the metal that used is identical is formed.

In the first embodiment, n-AlGaN electron supply layer 13 is immediately below source electrode 16 Part and the p-GaN electron transit layer 12 part immediately below source electrode 16 are adulterated doped with N-shaped Agent, and these N-shaped doped portions are as N-shaped contact area 9C.Source electrode 16 is formed at n (in the first embodiment, at the n of n-AlGaN electron supply layer 13 on type contact area 9C On type contact area).N-AlGaN electron supply layer 13 and p-GaN electron transit layer 12 and electric leakage The part of pole 17 contact is doped with n-type dopant, and these N-shaped doped portions are used as N-shaped and connect Touch region 9D.Drain electrode 17 is formed to contact with N-shaped contact area 9D.Can be by such as The ion implanting of n-type dopant (such as Si) forms N-shaped contact area 9C and 9D.This In the case of, N-shaped contact area 9C and 9D is the region being filled with n-type dopant ion wherein. The surface of the second nitride semiconductor layers 14 (is i.e. included in the second nitride semiconductor layers 14 In the surface of n-AlGaN electron supply layer 13) be coated with such as SiN film 11(passivating film, grid Pole insulator or dielectric film).Gate electrode 15 is arranged on SiN film 11.Such structure is MIS structure and can be that the part immediately below gate electrode 15 of wherein SiN film 11 is removed Schottky junction structure.

In such a configuration, the part in source electrode 16 side of p-GaN electron transit layer 12 is n Type, another part immediately below gate electrode 15 of p-GaN electron transit layer 12 is p-type, p-GaN Another part in drain electrode 17 side of electron transit layer 12 is N-shaped；Therefore, nomal closed type HEMT 2 have npn structure.Both N-shaped contact area 9C and 9D are just preferably extending to gate electrode 15 The region of lower section.In this way, the electron transit layer 12 of nomal closed type HEMT2 can have at grid The part containing p-type dopant immediately below electrode 15.

Second nitride semiconductor layers 14 also known as compound semiconductor lamination, GaN-HEMT Structure, AlGaN/GaN-HEMT structure or GaN-HEMT crystal.Second nitride-based semiconductor Lamination 14 can include at least electron transit layer and electron supply layer, and can include that other are partly led Body layer.Second nitride semiconductor layers 14 can be such as to make it possible to form field-effect transistor The nitride semiconductor layers of (wherein using the field-effect transistor of nitride-based semiconductor). P-GaN electron transit layer 12 also known as the second electron transit layer.N-AlGaN electron supply layer 13 Also known as the second electron supply layer.Gate electrode 15 also known as second gate electrode.Source electrode 16 is also known as Second source electrode.Drain electrode 17 also known as the second drain electrode.

In the first embodiment, specifically, p-GaN layer is used to make as electron transit layer 12 Can operate under normal off pattern.Specifically, p-GaN layer is used to cause as electron transit layer 12 Can raise by band immediately below gate electrode 15.Can band raise make p-GaN electron transit layer 12 with The energy level of the conductive strips of the interface between n-AlGaN electron supply layer 13 is higher than fermi level, because of This inhibits the generation of 2DEG, is enable under normal off pattern operation.In this situation Under, and the conventional p-GaN grid of p-GaN layer is wherein set between gate electrode and electron supply layer Structure is compared, and p-GaN electron transit layer 12 is oriented to closer to channel region that (electronics is wherein The region of movement), therefore the first embodiment is easier to make it possible to operate under normal off pattern.Separately Outward, due to nomal closed type HEMT2 threshold voltage size with add to p-GaN electron transit layer The concentration of the p-type dopant of 12 is proportional, so based on adding to p-GaN electron transit layer 12 The concentration of p-type dopant can control threshold voltage.Therefore, with conventional p-GaN grid structure Comparing, the first embodiment makes it possible to easily control threshold voltage.

In the first embodiment, the transistor owing to operating under normal off pattern includes that comprising p-type mixes The electron transit layer 12 of miscellaneous dose, simultaneously this transistor have include electron transit layer 12 and electronics supply The HEMT-structure of layer 13, so electron mobility is high, this makes it possible to obtain and common metal Oxide semiconductor field effect transistor (MOSFET) is compared operation and comparatively fast and is had superior performance Nomal closed type transistor.In the first embodiment, p-GaN electron transit layer 12 is adulterated promising p Type adulterant Mg.P-type dopant to be added to p-GaN electron transit layer 12 is not limited to Mg； It is, for example possible to use Be, Fe and C.Specifically, p-GaN electron transit layer 12 can comprise GaN and any p-type dopant selected from Be, Mg, Fe and C.In the first embodiment, AlGaN is used for electron supply layer 13, but the material of electron supply layer 13 is not limited to AlGaN； Such as, electron supply layer 13 can comprise any one in AlGaN, InAlN and AlInGaN.

In the first embodiment, such as, except being formed at the first nitridation of normal open type HEMT1 The surface of the AlN impurity diffusion impervious layer 10 formed on thing semiconductor laminated 5 and nomal closed type HEMT Outside the surface of second nitride semiconductor layers 14 of 2, as the source electricity of normal open type HEMT1 The surface of the public electrode 18 of the drain electrode 17 of pole 7 and nomal closed type HEMT2 is also covered with such as SiN film 11(passivating film, gate insulator or dielectric film).

In the first embodiment, the drain electrode 8 of normal open type HEMT1 and nomal closed type HEMT2 Gate electrode 15 and source electrode 16 be connected to such as wire and weld pad.The grid of normal open type HEMT1 Electrode 6 is electrically connected to the source electrode 16 of nomal closed type HEMT2 to set up normal open type HEMT1 with often The cascade of disconnected type HEMT2 connects.In this case, the source electricity of nomal closed type HEMT2 Pole 16 ground connection, and the gate electrode 6 of normal open type HEMT1 is electrically connected to nomal closed type HEMT2 Source electrode 16.In other words, common source nomal closed type HEMT2 and common gate normal open type HEMT 1 is connected in series to set up normal open type HEMT1 is connected with the cascade of nomal closed type HEMT2.

In the semiconductor device of the first embodiment with this spline structure, owing to mixing doped with p-type The electron transit layer 12 of the nomal closed type HEMT2 of miscellaneous dose is arranged on the electronics of normal open type HEMT1 Above supplying layer 4 and electron transit layer 3, wherein p-type dopant diffusion impervious layer 10 is between this electricity Between sub-transit layer 12 and this electron supply layer 4 and this electron transit layer 3, it is possible at normal open Nomal closed type is stopped during the electron supply layer 4 of type HEMT1 and the crystal growth of electron transit layer 3 The p-type dopant comprised in the electron transit layer 12 of HEMT2 is diffused into this electron supply layer 4 He This electron transit layer 3.Have relatively compared with n-AlGaN electron supply layer 4 as it has been described above, use The p-type dopant diffusion impervious layer 10 of big Al content causes generation in normal open type HEMT1 The amount of 2DEG increases.Thus, enabling operate under normal off pattern make it possible to obtain simultaneously low Conducting resistance and high withstanding voltage.

Nomal closed type HEMT2 includes the electron transit layer 12 of the p-GaN layer comprising p-type dopant, Nomal closed type HEMT2 has and includes electron transit layer 12 and the HEMT of electron supply layer 13 simultaneously Structure.Therefore, electron mobility is high, and channel resistance is low, and this makes it possible to obtain low conducting Resistance.Thus, enabling operate under normal off pattern and make it possible to obtain high withstanding voltage simultaneously.

Nomal closed type HEMT2 is not damaged by etching as described below.The most do not occur to produce because of etching Raw infringement and conducting resistance and leakage current are increased.Therefore, enabling stably at normal off mould Operate under formula and make it possible to obtain low conducting resistance.In nomal closed type HEMT2, electronics Transit layer 12 is p-GaN layer.In this case, due to the threshold value electricity of nomal closed type HEMT2 The size of pressure is proportional to the concentration adding the p-type dopant to p-GaN electron transit layer 12, institute Can control threshold value electricity based on the concentration adding the p-type dopant to p-GaN electron transit layer 12 Pressure.Thus, the first embodiment makes it possible to easily control threshold voltage.With such as routine P-GaN grid structure is compared, enabling easily controllable threshold voltage and operation under normal off pattern.

From be wherein formed as covering the Si-MOSFET of different Semiconductor substrate and GaN-HEMT cascade each other connects the structure of (mixing cascade connects) and compares, wherein Be formed as covering normal open type HEMT1 of identical Semiconductor substrate and nomal closed type HEMT2 is total to each other The structure of source common gate connection makes it possible to reduce the length interconnected；Therefore, it can reduce circuit Reactance, this makes the speed of circuit operation improve.

In the semiconductor device of the first embodiment with said structure, due to separately through normal off Type HEMT2 makes it possible to operate under normal off pattern, it is possible to separate configurations normal open type HEMT1 and do not consider the operation under normal off pattern.Specifically, can due to normal open type HEMT1 To be configured to the operation under normal off pattern not contributed, it is possible to independently determined 2DEG The amount i.e. thickness of electron supply layer 4 to reduce conducting resistance.Thus, in normal open type HEMT1 In, the thickness amount with increase 2DEG of electron supply layer 4 can be increased, thus reduce electric conduction Resistance.In other words, the electron supply layer 4 of normal open type HEMT1 preferably have big thickness with Reduce conducting resistance.Preferably, such as, the thickness of the electron supply layer 4 of normal open type HEMT1 The thickness of the degree electron supply layer 13 more than nomal closed type HEMT2.Electricity in normal open type HEMT1 In the case of sub-supplying layer 4 is configured to have big thickness, contact area 9A and 9B is excellent for N-shaped Selection of land is respectively formed at the underface of source electrode 7 and drain electrode 8 to reduce due to electron supply layer 4 The resistance generated.But, owing to the increase of the thickness of electron supply layer 4 causes the amount of 2DEG to increase Add, it is possible to omit the formation of N-shaped contact area 9A and 9B.In normal open type HEMT1, The increase of the distance between gate electrode 6 and drain electrode 8 makes it possible to increase withstanding voltage.In other words, In normal open type HEMT1, preferably increase the distance between gate electrode 6 and drain electrode 8 to increase Add withstanding voltage.In normal open type HEMT1, for example, it is preferred to form gate electrode 6, drain electrode 8 and source electrode 7 make distance between gate electrode 6 and drain electrode 8 more than gate electrode 6 and source electrode Distance between 7.

In normal open type HEMT1, in the distance increased between gate electrode 6 and drain electrode 8 to increase In the case of adding withstanding voltage, increase the thickness of electron supply layer 4 to suppress by the distance so increased The increase of caused conducting resistance.In other words, withstanding voltage can be increased make it possible to obtain simultaneously Conducting resistance that must be low.Therefore, normal open type HEMT1 is also known as the function of high withstanding voltage Region.

As it has been described above, normal open type HEMT1 of the functional area of high withstanding voltage with in normal off pattern The nomal closed type HEMT2 combination of the functional area of lower operation, this makes it possible to grasp under normal off pattern Make and make it possible to obtain low conducting resistance and high both withstanding voltages.Specifically, at normal off mould The functional area of operation and and each other common source separated from one another for the functional area of high withstanding voltage under formula Common gate connection, this makes it possible to manufacture to operate under normal off pattern make it possible to obtain low conducting simultaneously Resistance and the device of high both withstanding voltages.

Specifically, can cross at the electron supply layer 4 of normal open type HEMT1 and electronics as mentioned above More stop, during the crystal growth of layer 3, the p comprised in the electron transit layer 12 of nomal closed type HEMT2 Type adulterant is diffused into this electron supply layer 4 and this electron transit layer 3, and this makes normal open type HEMT The conducting resistance of 1 can be maintained at low-level.Is described now with reference to Fig. 2 A to Fig. 4 B The method manufacturing semiconductor device of one embodiment.

As shown in Figure 2 A, the i-GaN layer 3 as the first electron transit layer is formed, as the first electricity The n-AlGaN layer 4 of sub-supplying layer, the AlN layer 10 as p-type dopant diffusion impervious layer, use Make the p-GaN layer 12 of the second electron transit layer and be used as the n-AlGaN layer of the second electron supply layer 13 are formed to cover Semiconductor substrate (not shown).In this case, Semiconductor substrate can be Such as semi-insulation SiC substrate 20(is shown in Fig. 3 A).Additionally, such as, nucleating layer 21 and cushion 22 Can be formed between Semiconductor substrate 20 and the i-GaN layer 3 being used as the first electron transit layer (see Fig. 3 A).Thickness as the i-GaN layer 3 of the first electron transit layer can be e.g., from about 3 μm. Additionally, the i-AlGaN layer 23 being used as the first wall can be formed at as the first electron transit layer I-GaN layer 3 and be used as the first electron supply layer n-AlGaN layer 4 between (see Fig. 3 A). In this case, the thickness as the i-AlGaN layer 23 of the first wall can be e.g., from about 5 nm.As in the n-AlGaN layer 4 of the first electron supply layer, such as, its thickness can be about 30nm, Al content can be 0.3, specifically, in formula Al_xGa_1-xIn N, x is 0.3, waits to add The n-type dopant adding to this n-AlGaN layer 4 can be Si, and concentration of dopant can be about 5×10¹⁸cm^-3.As the AlN layer 10(of p-type dopant diffusion impervious layer in formula Al_xGa_1-xIn N, X is 1) can have the thickness of e.g., from about 5nm.Such as, as the second electron transit layer In p-GaN layer 12, its thickness can be about 100nm, adds the p-type to this p-GaN layer 12 Adulterant can be Mg, and concentration of dopant can be about 1 × 10²¹cm^-3.Additionally, be used as the The i-AlGaN layer 24 of two walls can be formed at the p-GaN layer as the second electron transit layer Between 12 and the n-AlGaN layer 13 being used as the second electron supply layer (see Fig. 3 A).In this situation Under, the thickness as the i-AlGaN layer 24 of the second wall can be e.g., from about 5nm.It is being used as In the n-AlGaN layer 13 of the second electron supply layer, such as, its thickness can be about 30nm, treats Interpolation can be Si to the n-type dopant of this n-AlGaN layer 13, and concentration of dopant can be About 5 × 10¹⁸cm^-3.The example of growing method is gas phase epitaxy of metal organic compound (MOVPE). Can be trimethyl aluminium (TMA), trimethyl for forming the source gas of each nitride semiconductor layer Gallium (TMG) and ammonia (NH₃) mixed gas, and can be according to nitride to be formed half The type of conductor layer suitably adjusts the TMA as Al source or the confession of the TMG as Ga source Give and flow.

Semi-insulation SiC substrate 20 is prepared as Semiconductor substrate, and by nucleating layer 21, cushion 22, the i-GaN layer 3 as the first electron transit layer, the i-AlGaN layer as the first wall 23, as the n-AlGaN layer 4 of the first electron supply layer, as p-type dopant diffusion impervious layer AlN layer 10, as the p-GaN layer 12 of the second electron transit layer, as the second wall I-AlGaN layer 24 and the n-AlGaN layer 13 as the second electron supply layer are formed as covering partly leads Body substrate, thus form the structure shown in Fig. 3 A.

As the p-type dopant comprised in the p-GaN layer 12 of the second electron transit layer (such as, Mg) it is high diffusion during the crystal growth of this p-GaN layer 12.But, as p The AlN layer 10 of type doping agent diffusion blocking layer is arranged on the p-GaN layer as the second electron transit layer Below 12, and it is used as the n-AlGaN layer 4 of the first electron supply layer and is used as the first electron transit The i-GaN layer 3 of layer is positioned under as the AlN layer 10 of p-type dopant diffusion impervious layer, in order to It is coated with AlN layer 10.Therefore, the p-GaN layer 12 as the second electron transit layer is being formed During crystal growth, can stop as p contained in the p-GaN layer 12 of the second electron transit layer Type adulterant (such as, Mg) diffuses to the n-AlGaN layer 4 as the first electron supply layer and use Making the i-GaN layer 3 of the first electron transit layer, n-AlGaN layer 4 and i-GaN layer 3 is positioned at p-GaN Under layer 12.Such structure can be with the impaired performance of abatement device, the such as increase of conducting resistance. It addition, the AlN layer 10 being used as p-type dopant diffusion impervious layer also allows for increasing normal open type The amount of the 2DEG generated in HEMT1.

In the first embodiment, although AlN layer is formed p-type dopant diffusion impervious layer 10, But p-type dopant diffusion impervious layer 10 is not limited to this；Such as, p-type dopant diffusion impervious layer 10 can be AlGaN layer.In other words, p-type dopant diffusion impervious layer 10 can be by AlGaN Or AlN is formed.Specifically, p-type dopant diffusion impervious layer 10 is preferably by having no less than 0.5 Al content AlGaN or AlN formed.In the first embodiment, the second electron transit layer 12 is doped with the p-GaN layer as p-type dopant Mg, but the invention is not restricted to this；Second Electron transit layer 12 can be doped with alternative p-type dopant such as Be, Fe or C P-GaN layer.In other words, the p-GaN layer 12 as the second electron transit layer can be to comprise GaN and the layer of any one in the p-type dopant of Be, Mg, Fe and C.? In one embodiment, the second electron supply layer is n-AlGaN layer 13 but is not limited to this；Can be formed Comprise the layer of any one in AlGaN, InAlN and AlInGaN.First electron supply layer 4 is preferred Ground has big thickness.Make it have than the second electronics for example, it is preferred to form the first electron supply layer 4 The thickness that the thickness of supplying layer 13 is bigger.This structure makes it possible to increase the amount of 2DEG, causes The reduction of energising resistance.Preferably, gate electrode 6 and drain electrode 8 are arranged to each other with big distance interval Open.This structure makes it possible to obtain high withstanding voltage.Gate electrode 6, drain electrode 8 and source electrode 7 are excellent Selection of land is formed as such as making the distance between gate electrode 6 and drain electrode 8 more than gate electrode 6 and source electricity Distance between pole 7.

Then, as shown in Figure 2 B, n-AlGaN layer 13 He is removed by the etching of such as photoetching process P-GaN layer 12 such as lower part: corresponding in addition to the region of nomal closed type HEMT to be formed Region, in other words corresponding to the region (in Fig. 2 B right side) of normal open type HEMT to be formed. In the process, the AlGaN layer 10 of p-type dopant diffusion impervious layer is used as etching stopping layer. Therefore, protection is used as the n-AlGaN layer 4 of the first electron supply layer and is used as the first electron transit layer I-GaN layer 3 i.e. channel region (passage area) avoid because of etching produce infringement, wherein N-AlGaN layer 4 and i-GaN layer 3 is included in normal open type HEMT1.Additionally, by such as Photoetching process etching removes the part of the AlN layer 10 as p-type dopant diffusion impervious layer, these Correspond partly to source electrode and the region of drain electrode of normal open type HEMT1 the most to be formed.

By this technique, there is i-GaN electron transit layer 3(the first electron transit layer) and n-AlGaN Electron supply layer 4(the first electron supply layer) the nitride semiconductor layers of hierarchy formed The first nitride semiconductor layers 5 included for normal open type HEMT1.There is p-GaN electronics Transit layer 12(the second electron transit layer) and the supply of n-AlGaN electron supply layer 13(the second electronics Layer) the nitride semiconductor layers of hierarchy be formed to comprise in nomal closed type HEMT2 The second nitride semiconductor layers 14 so that be located higher than in normal open type HEMT1 and comprise The first nitride semiconductor layers 5, wherein as the AlN impurity of p-type dopant diffusion impervious layer Diffusion impervious layer 10 is between the second nitride semiconductor layers 14 and the first nitride semiconductor layers 5 Between.

In the case of semi-insulation SiC substrate 20 is prepared to Semiconductor substrate, and at nucleating layer 21, cushion 22, as the i-GaN layer 3 of the first electron transit layer, as the first wall I-AlGaN layer 23, as the n-AlGaN layer 4 of the first electron supply layer, as p-type dopant The AlN layer 10 of diffusion impervious layer, as the p-GaN layer 12 of the second electron transit layer, as second The i-AlGaN layer 24 of wall and the n-AlGaN layer 13 as the second electron supply layer are formed In the case of covering Semiconductor substrate, remove n-AlGaN layer 13, i-AlGaN by etching Region outside the region corresponding to nomal closed type HEMT to be formed of layer 24 and p-GaN layer 12 Part, and remove p-type dopant diffusion impervious layer AlN layer 10 by etching and treat wherein Form the part that in the region of normal open type HEMT, source electrode to be formed is corresponding with the part of drain electrode, Thus the structure shown in Fig. 3 B is provided.

In this case, will have nucleating layer 21, cushion 22, i-GaN electron transit layer 3 (the first electron transit layer), i-AlGaN the first wall 23 and n-AlGaN electron supply layer 4 The nitride semiconductor layers of the hierarchy of (the first electron supply layer) is formed as being included in normal open type The first nitride semiconductor layers 5 in HEMT1.It addition, p-GaN electron transit will be had Layer 12(the second electron transit layer), i-AlGaN the second wall 24 and n-AlGaN electronics supply Layer 13(the second electron supply layer) the nitride semiconductor layers of hierarchy be formed as being included in The second nitride semiconductor layers 14 in nomal closed type HEMT2 so that it is be positioned higher than normal open type The first nitride semiconductor layers 5 that HEMT1 includes, wherein as p-type dopant diffusion resistance The AlN impurity diffusion impervious layer 10 of barrier is between the second nitride semiconductor layers 14 and the first nitrogen Between compound semiconductor laminated 5.

Then, as shown in Figure 2 C, by n-type dopant (such as Si) ion implanting to region below: The region contacted with the drain electrode 8 of normal open type HEMT1 and the source electrode of nomal closed type HEMT2 The regions of 16 contacts and with as the source electrode 7 of normal open type HEMT1 and nomal closed type HEMT The region of public electrode 18 contact of the drain electrode 17 of 2, then makes product experience activation processing such as Heat treatment, thus form the N-shaped contact area 9A to 9D as n doped region.

In the process, n-type dopant (such as Si) ion implanting to n-AlGaN electronics is supplied The part under the drain electrode 8 of normal open type HEMT1 of layer 4 and i-GaN electron transit layer 3 In.It addition, by n-type dopant (such as Si) ion implanting to n-AlGaN electron supply layer 13 With in the part under the source electrode 16 of nomal closed type HEMT2 of p-GaN electron transit layer 12. And, by n-type dopant (such as Si) ion implanting to n-AlGaN electron supply layer 4 and i-GaN Electron transit layer 3 as the source electrode 7 of normal open type HEMT1 and nomal closed type HEMT2 In part under the public electrode 18 of drain electrode 17, and it is injected into n-AlGaN electron supply layer 13 and p-GaN electron transit layer 12 as the source electrode 7 of normal open type HEMT1 and normal off In the part of public electrode 18 side of the drain electrode 17 of type HEMT2.Then, activate Processing such as heat treatment and being formed is the N-shaped contact area 9A to 9D of n doped region.By this Technique, gives nomal closed type HEMT2 with npn structure.

In the case of semi-insulation SiC substrate 20 is prepared as Semiconductor substrate, and at nucleating layer 21, cushion 22, as the i-GaN layer 3 of the first electron transit layer, as the first wall I-AlGaN layer 23, as the n-AlGaN layer 4 of the first electron supply layer, as p-type dopant The AlN layer 10 of diffusion impervious layer, as the p-GaN layer 12 of the second electron transit layer, as second The i-AlGaN layer 24 of wall and the n-AlGaN layer 13 as the second electron supply layer are formed In the case of covering Semiconductor substrate, by n-type dopant (such as Si) ion implanting to n-AlGaN Electron supply layer 4, i-AlGaN the first wall 23 and i-GaN electron transit layer 3 at normal open In part under the drain electrode 8 of type HEMT1.By n-type dopant (such as Si) ion implanting To n-AlGaN electron supply layer 13, i-AlGaN the second wall 24 and p-GaN electron transit In the part under the source electrode 16 of nomal closed type HEMT2 of layer 12.By n-type dopant (as Si) ion implanting is to n-AlGaN electron supply layer 4, i-AlGaN the first wall 23 and i-GaN Electron transit layer 3 as the source electrode 7 of normal open type HEMT1 and nomal closed type HEMT2 In part under the public electrode 18 of drain electrode 17, and it is injected into n-AlGaN electron supply layer 13, i-AlGaN the second wall 24 and p-GaN electron transit layer 12 as normal open type Public electrode 18 side of the source electrode 7 of HEMT1 and the drain electrode 17 of nomal closed type HEMT2 Part in.Then, carry out activation processing such as heat treatment and formed being that the N-shaped of n doped region connects Touch region 9A to 9D.By this technique, give nomal closed type HEMT2 with npn structure.At this In the case of Zhong, it is provided that the structure shown in Fig. 3 C.

In the case of being formed without N-shaped contact area 9A and 9B, for example, it is possible to remove n-AlGaN Electron supply layer 4 formed normal open type HEMT1 drain electrode position immediately below part, And the part immediately below the position forming public electrode 18 of n-AlGaN electron supply layer 4, Wherein public electrode 18 is used as source electrode 7 and the leakage of nomal closed type HEMT2 of normal open type HEMT1 Electrode 17.

Though not shown, formed by such as photoetching process have corresponding with device isolation regions The Etching mask of opening, and by such as utilizing chlorine-based gas to carry out dry etching or by against corrosion Agent mask carries out ion implanting to carry out device isolation.Then, as shown in Figure 2 D, normal open is defined The drain electrode 8 of type HEMT1, the source electrode 16 of nomal closed type HEMT2 and be used as normal open type HEMT The source electrode 7 of 1 and the public electrode 18 of the drain electrode 17 of nomal closed type HEMT2.Specifically, often The drain electrode 8 of flow-through HEMT1 is formed at the first nitride-based semiconductor of normal open type HEMT1 and folds On layer 5, the source electrode 16 of nomal closed type HEMT2 is formed at second nitridation of nomal closed type HEMT2 On thing semiconductor laminated 14, and it is used as source electrode 7 and the nomal closed type of normal open type HEMT1 The public electrode 18 of the drain electrode 17 of HEMT2 is formed at the first nitridation of normal open type HEMT1 On thing semiconductor laminated 5 so that it is the second nitride-based semiconductor being positioned at nomal closed type HEMT2 is folded The side of layer 14.

In region below, tantalum and aluminum it is sequentially deposited by such as photoetching process and deposition and lift-off technology: The region of the drain electrode 8 of normal open type HEMT1 the most to be formed, nomal closed type HEMT the most to be formed The region of the source electrode 16 of 2 and the source electrode 7 as normal open type HEMT1 the most to be formed With the region of the public electrode 18 of the drain electrode 17 of nomal closed type HEMT2, thus form respectively The drain electrode 8 of tantalum/aluminum, source electrode 16 and public electrode 18.Specifically, drain electrode 8, source electrode 16 and public electrode 18 formed by tantalum/aluminum so that contact the N-shaped contact area of above-mentioned formation respectively 9B, 9C and 9A and 9D.In this case, such as, tantalum is deposited to the thickness of about 20nm, And aluminum is deposited to the thickness of about 200nm.Then, such as, with about 400 DEG C in blanket of nitrogen Hot product is added to produce ohm property to 1000 DEG C (such as, 550 DEG C).In the first embodiment In, in this way, public electrode 18 by be used for forming drain electrode 8 and the second source electrode 16 is made The identical metal of metal formed.

In the case of semi-insulation SiC substrate 20 is prepared as Semiconductor substrate, and at nucleating layer 21, cushion 22, as the i-GaN layer 3 of the first electron transit layer, as the first wall I-AlGaN layer 23, as the n-AlGaN layer 4 of the first electron supply layer, as p-type dopant The AlN layer 10 of diffusion impervious layer, as the p-GaN layer 12 of the second electron transit layer, as second The i-AlGaN layer 24 of wall and the n-AlGaN layer 13 as the second electron supply layer are formed In the case of covering Semiconductor substrate, define the drain electrode 8 of normal open type HEMT1, nomal closed type The source electrode 16 of HEMT2 and be used as source electrode 7 and the nomal closed type HEMT of normal open type HEMT1 The public electrode 18 of the drain electrode 17 of 2, thus provide the structure shown in Fig. 4 A.Often it is used as The source electrode 7 of flow-through HEMT1 and the public electrode 18 of the drain electrode 17 of nomal closed type HEMT2 There is the shape shown in Fig. 2 D or the shape shown in Fig. 4 A.In other words, as normal open type The public electrode 18 of the source electrode 7 of HEMT1 and the drain electrode 17 of nomal closed type HEMT2 is permissible It is formed only on its side surface or on its side surface with both upper surfaces, to contact nomal closed type The N-shaped contact area 9D of HEMT2.

Then, as shown in Figure 2 D, such as, SiN film 11(passivating film, gate insulator or exhausted Velum) formed on the surface of the product, and the gate electrode 6 of normal open type HEMT1 and nomal closed type The gate electrode 15 of HEMT2 is subsequently formed on SiN film 11.In this case, define MIS structure.Specifically, the gate electrode 6 of normal open type HEMT1 is formed at normal open type HEMT1 The first nitride semiconductor layers 5 on, and the gate electrode 15 of nomal closed type HEMT2 is formed at On second nitride semiconductor layers 14 of nomal closed type HEMT2.In this case, nomal closed type The gate electrode 15 of HEMT2 is formed at second nitride semiconductor layers 14 of nomal closed type HEMT2 The overlying regions comprising p-type dopant of the p-GaN electron transit layer 12 included, i.e. except mixing Overlying regions outside the miscellaneous region having n-type dopant.

Come by such as photoetching process and deposition and lift-off technology in the region of gate electrode the most to be formed It is sequentially deposited nickel and gold, thus forms the gate electrode 6 and 15 of ni au.In this case, such as, Nickel is deposited to the thickness of about 30nm, and gold is deposited to the thickness of about 400nm.Half absolutely In the case of edge SiC substrate 20 is prepared as Semiconductor substrate, and at nucleating layer 21, cushion 22, the i-GaN layer 3 as the first electron transit layer, the i-AlGaN layer as the first wall 23, as the n-AlGaN layer 4 of the first electron supply layer, as p-type dopant diffusion impervious layer AlN layer 10, as the p-GaN layer 12 of the second electron transit layer, as the second wall I-AlGaN layer 24 and the n-AlGaN layer 13 as the second electron supply layer are formed to cover half In the case of conductor substrate, in the case of being formed without SiN film 11, define normal open type HEMT The gate electrode 6 of 1 and the gate electrode 15 of nomal closed type HEMT2, in other words, Schottky junction structure Formed and provide the structure shown in Fig. 4 B.

Then, the drain electrode 8 of normal open type HEMT1 and the gate electrode 15 of nomal closed type HEMT2 It is connected to such as wire and weld pad with source electrode 16.It addition, the gate electrode 6 of normal open type HEMT1 It is electrically connected to the source electrode 16 of nomal closed type HEMT2 to set up normal open type HEMT1 and nomal closed type The cascade of HEMT2 connects.

In this way, the manufacture of the semiconductor device of the first embodiment, wherein, nomal closed type are completed HEMT2 is set above normal open type HEMT1 p-type dopant diffusion impervious layer 10 simultaneously and is situated between Between nomal closed type HEMT2 and normal open type HEMT1, and normal open type HEMT1 is with often Disconnected type HEMT2 cascade connects.In the first embodiment, SiC substrate 20 conduct is used The example of Semiconductor substrate, but Semiconductor substrate is not limited to this；It is, for example possible to use other lining The end, such as includes Sapphire Substrate, Si substrate and the Semiconductor substrate of GaN substrate.Additionally, In one embodiment, substrate 20 is for SI-substrate but is not limited to this；Such as, substrate 20 can be N-shaped conductive substrates or p-type electric-conducting substrate.

Above-mentioned including source electrode 16, drain electrode 8, public electrode 18 and gate electrode 6 and 15 Hierarchy is example, and can use other hierarchy and unrestricted.Including source electrode 16, the above-mentioned hierarchy of drain electrode 8, public electrode 18 and gate electrode 6 and 15 can be Such as single layer structure or multiple structure.For formed source electrode 16, drain electrode 8, public electrode 18, And the technique of gate electrode 6 and 15 is only example, and can be formed by other technique.

Although having carried out heat treatment to develop source electrode 16, drain electrode 8 and ohm of public electrode 18 Characteristic, but can be by any other technology to develop ohm property；Developing without heat treatment In the case of ohm property, it is convenient to omit be used for developing source electrode 16, drain electrode 8 and public electrode The heat treatment of the ohm property of 18.Although the most not making gate electrode 6 and 15 warp Go through heat treatment, but gate electrode 6 and 15 can be made to experience heat treatment.

Semiconductor device according to the first embodiment and the method being used for producing the semiconductor devices provide Wherein make it possible to operate under normal off pattern and make low conducting resistance and high withstanding voltage increase simultaneously Strong beneficial effect.Can partly leading according to the first embodiment the most modified as described below Body device and the method being used for producing the semiconductor devices.Is described now with reference to Fig. 5 A and 5B One change programme.

First change programme is the source as normal open type HEMT1 with the difference of the first embodiment The public electrode 18 of the drain electrode 17 of electrode 7 and nomal closed type HEMT2 be not metal electrode but N doped region 9E as shown in Figure 5 B.In the first embodiment, such as, semi-insulation SiC Substrate 20 is prepared as Semiconductor substrate, and nucleating layer 21, cushion 22, as the first electronics The i-GaN layer 3 of transit layer, as the i-AlGaN layer 23 of the first wall, as the first electronics The n-AlGaN layer 4 of supplying layer, as p-type dopant diffusion impervious layer AlN layer 10, be used as The p-GaN layer 12 of the second electron transit layer, as the i-AlGaN layer 24 of the second wall with use The n-AlGaN layer 13 making the second electron supply layer is formed to cover Semiconductor substrate.

In the first change programme, n doped region 9E(its be public electrode 18) can be as got off Formed: obstructed overetch removes the as follows of the AlN layer 10 as p-type dopant diffusion impervious layer Part, described in partly belong in the region in source electrode to be formed, described source electrode treats shape wherein Become in the region of normal open type HEMT；N-type dopant (such as Si) ion implanting is arrived to be formed As the source electrode 7 of normal open type HEMT1 and the common electrical of the drain electrode 17 of nomal closed type HEMT2 In region in pole 18, as shown in Figure 5A；And carry out activation processing such as heat treatment.Change sentence Talk about, as the n doped region 9E(implant n-type dopant ion the most wherein of public electrode 18 Region) can be such as formation of getting off: to be formed to as the source electrode 7 of normal open type HEMT1 With in the region in the public electrode 18 of the drain electrode 17 of nomal closed type HEMT2, N-shaped is adulterated The ion implanting of agent such as SiC to nomal closed type HEMT2 n-AlGaN electron supply layer 13, In the part of i-AlGaN the second wall 24 and p-GaN electron transit layer 12；And n-AlGaN Electron supply layer 4, i-AlGaN the first wall 23 and i-GaN electron transit layer 3 part in； Then activation processing such as heat treatment is carried out.In this way, public electrode 18 can be from nomal closed type The surface of second nitride semiconductor layers 14 of HEMT2 is (in the first embodiment, The surface of n-AlGaN electron supply layer 13) extend to the first nitride of normal open type HEMT1 partly I-GaN electron transit layer 3(the first electron transit layer that conductor lamination 5 includes) n doped region Territory 9E.In other words, the surface from the second nitride semiconductor layers 14 extends to normal open type I-GaN electron transit layer 3(first that first nitride semiconductor layers 5 of HEMT1 includes Electron transit layer) n doped region 9E can be formed public electrode 18.As shown in Figure 5A, Shape can be treated on the region of the drain electrode 8 of normal open type HEMT1 the most to be formed and its The region of the source electrode 16 of one-tenth nomal closed type HEMT2 forms N-shaped contact area 9B's and 9C During formed be used as public electrode 18 n doped region 9E.In this case, it is used for being formed The technique of the drain electrode 8 of normal open type HEMT1 and the source electrode 16 of nomal closed type HEMT2 be used for Formation is used as the source electrode 7 of normal open type HEMT1 and the public affairs of the drain electrode 17 of nomal closed type HEMT2 The technique of common electrode 18 is different.By contrast, in the first embodiment, by identical technique Form these electrodes.Then, as shown in Figure 5 B, the electric leakage of normal open type HEMT1 can be formed The source electrode 16 of pole 8 and nomal closed type HEMT2, and the grid of normal open type HEMT1 can be formed The gate electrode 15 of electrode 6 and nomal closed type HEMT2.Other parts of this structure and manufacture method Details is identical with other parts in the first embodiment and details.

Now with reference to Fig. 6 A and 6B, the second change programme is described.Second change programme and first The difference of embodiment is to form n-type semiconductor layer 25A to 25C as n-contact layer not N doped region 9A to 9D is as N-shaped contact area, as shown in Figure 6B in formation.Become second In change scheme, such as, semi-insulation SiC substrate 20 is prepared as Semiconductor substrate；Nucleating layer 21, Cushion 22, the i-GaN layer 3 as the first electron transit layer, the i-AlGaN as the first wall Layer 23, as the n-AlGaN layer 4 of the first electron supply layer, as p-type dopant diffusion barrier Layer AlN layer 10, as the p-GaN layer 12 of the second electron transit layer, as the second wall I-AlGaN layer 24 and the n-AlGaN layer 13 as the second electron supply layer are formed to cover half Conductor substrate；And n-GaN layer is formed n-type semiconductor layer 25A to 25C.N-shaped is partly led Body layer 25A to 25C is not limited to n-GaN layer, and can be such as n-InGaN layer.

In the second change programme, replace in the first embodiment for forming N-shaped contact area Technique (see Fig. 2 C and 3C), as shown in Figure 6A, can grow (regrowth) at following location The position of n-GaN: the drain electrode 8 of normal open type HEMT1 to be formed, nomal closed type HEMT to be formed The position of the source electrode 16 of 2 and the source electrode 7 as normal open type HEMT1 to be formed and often The position of the public electrode 18 of the drain electrode 17 of disconnected type HEMT2, thus define and connect for N-shaped The n-GaN layer 25A to 25C of contact layer.In the second change programme, from nomal closed type HEMT2's The surface of the second nitride semiconductor layers 14 extends to first nitride half of normal open type HEMT1 The n-GaN layer 25B(n type semiconductor layer on the surface of conductor lamination 5) can be formed to be arranged on The n-contact layer of the position of public electrode to be formed.Formation of can the most such as getting off connects as N-shaped The n-GaN layer 25A to 25C of contact layer: by photoetching and thermal chemical vapor deposition (CVD) method Form the SiO with the opening corresponding with following region₂Film 26: normal open type the most to be formed The region of the drain electrode 8 of HEMT1, nomal closed type HEMT2 to be formed source electrode 16 region, And the source electrode 7 as normal open type HEMT1 to be formed and the drain electrode of nomal closed type HEMT2 The region of the public electrode 18 of 17；And by such as MOVPE method based on wherein GaN not Too may be at SiO₂The characteristic the most optionally epitaxial growth n-GaN of growth on film 26. Then, as shown in Figure 6B, nomal closed type HEMT2 source electrode 16, as normal open type HEMT1 Source electrode 7 and the public electrode 18 of drain electrode 17 of nomal closed type HEMT2 and normal open type HEMT The drain electrode 8 of 1 is respectively formed at as on the n-GaN layer 25A to 25C of n-contact layer；It is used as The SiO of mask₂Film 26 can be retained for use as dielectric film (passivating film or gate insulator)；With And the gate electrode 15 of the gate electrode 6 of normal open type HEMT1 and nomal closed type HEMT2 can be formed at SiO₂On film 26.In this case, MIS structure is defined.Other parts of this structure and The details of manufacture method is identical with other parts in the first embodiment and details.

N doped region it is formed without as n-contact layer forming n-type semiconductor layer 25A to 25C In the case of territory 9A to 9D is as N-shaped contact area, often slightly it is used as in this way, it is possible to save The source electrode 7 of flow-through HEMT1 and the public electrode 18 of the drain electrode 17 of nomal closed type HEMT2 The formation of metal electrode.In this case, n-type semiconductor layer 25B replaces as normal open type The source electrode 7 of HEMT1 and the public electrode 18 of the drain electrode 17 of nomal closed type HEMT2.Change sentence Talk about, extend to the first nitride semiconductor layers from the surface of the second nitride semiconductor layers 14 N-type semiconductor layer 25B on the surface of 5 is used as source electrode 7 and the drain electrode 17 of public electrode 18. In this case, for forming drain electrode 8 and the nomal closed type HEMT2 of normal open type HEMT1 Source electrode 16 technique be used as the source electrode 7 of normal open type HEMT1 and nomal closed type for being formed The technique of the public electrode 18 of the drain electrode 17 of HEMT2 is different.In other words, by be used for Form the technique of the drain electrode 8 of normal open type HEMT1 and the source electrode 16 of nomal closed type HEMT2 not Same technique, defines as public electrode 18 and from the surface of the second nitride semiconductor layers 14 Extend to n-type semiconductor layer 25B on the surface of the first nitride semiconductor layers 5.

In the second change programme, although being used as the SiO of mask₂Film 26 is retained for use as dielectric film Form MIS structure, but the structure of the second change programme is not limited to this；For example, it is possible to remove SiO as mask₂Film 26, then can form gate electrode 6 and the normal off of normal open type HEMT1 The gate electrode 15 of type HEMT2.In this case, it is provided that Schottky junction structure.Additionally, example As, the SiO as mask can be removed₂Film 26, can subsequently form other dielectric film (such as SiN film, passivating film or gate insulator), and often can be formed on the dielectric film that this is other The gate electrode 6 of flow-through HEMT1 and the gate electrode 15 of nomal closed type HEMT2.In this case, Provide MIS structure.

[the second embodiment]

Now with reference to accompanying drawing 7 and 8 describe the semiconductor device according to the second embodiment, for Manufacture method and the power supply of semiconductor device.

The semiconductor device of the second embodiment is the semiconductor package part including semiconductor chip, should be partly Conductor chip is that in the first embodiment and change programme thereof, the semiconductor device of any one (includes having Each other cascade connect normal open type HEMT1 and the transistor circuit of nomal closed type HEMT2). This semiconductor chip is also known as HEMT chip or transistor chip.To describe as example now Discrete package part.

With reference to Fig. 7, the semiconductor device of the second embodiment includes as the first embodiment and change thereof In change scheme, the semiconductor device of any one (includes having the normal open type that cascade connects each other HEMT1 and the transistor circuit of nomal closed type HEMT2) semiconductor chip 34, semiconductor core Platform 30, grid lead 37, source lead 39, drain lead 38 that sheet 34 is disposed thereon, connect Zygonema 36(is hereinafter referred to as Al line) and encapsulant resin 40.This encapsulant resin 40 also claims For moulded resin.

The semiconductor chip 34 being arranged on platform 30 has and is respectively connecting to grid by Al line 36 and draws The gate pad 31 of line 37, source lead 39 and drain lead 38, source pad 32 and drain electrode weldering Pad 33, and use resin to seal these weld pads.In semiconductor chip 34, nomal closed type HEMT The gate electrode 15 of 2 and the drain electrode 8 of source electrode 16 and normal open type HEMT1 are respectively connecting to Gate pad 31, source pad 32 and drain bonding pad 33.The gate electrode 6 of nomal closed type HEMT2 It is electrically connected to the source electrode 16 of nomal closed type HEMT2.Thus, the gate electrode of nomal closed type HEMT2 15 and source electrode 16 and normal open type HEMT1 drain electrode 8 respectively by gate pad 31, Source pad 32 and drain bonding pad 33 are connected to grid lead 37, source lead 39 and drain lead 38。

Using tube core attachment material (die-attach material) 35(is solder in this case) The rear surface of the substrate of semiconductor chip 34 is fixed to platform 30, and platform 30 is electrically connected to Lou Pole lead-in wire 38.Second embodiment is not limited to such structure, and platform 30 can be electrically connected to source electrode Lead-in wire 39.Be used for producing the semiconductor devices (discrete envelope according to second embodiment be will now be described Piece installing) method.

Such as use wafer attachment material 35(in this case for solder) will be the first enforcement In scheme and change programme thereof, the semiconductor chip 34 of the semiconductor device of any one is fixed to platform 30 On, wherein platform 30 is lead frame.Then, the gate pad 31 of semiconductor chip 34, drain electrode weldering Pad 33 and source pad 32 such as by be combined with Al line 36 be respectively connecting to grid lead 37, Drain lead 38 and source lead 39.

Then, by such as transmit molding process use resin carry out sealed product.Remove lead frame subsequently. Semiconductor device (discrete package part) can be manufactured in this way.Wherein make although there is described herein With the pad 31 to 33 of semiconductor chip 34 as the discrete package part of the joint sheet for wire bonding Example, but embodiment is not limited to this, and the semiconductor package part with other configurations can be used. It is, for example possible to use wherein use the pad of semiconductor chip as without wire bonding such as flip-chip The semiconductor package part of the joint sheet engaged.In addition it is possible to use wafer-level packaging part.And, can To use the semiconductor package part in addition to discrete package part.

The above-mentioned semiconductor package part including having semiconductor chip 34 is described now with reference to Fig. 8, This semiconductor chip 34 includes that wherein normal open type HEMT1 and nomal closed type HEMT2 common source each other are altogether The transistor circuit that grid connect.It is described below being included in above-mentioned semiconductor package part based on wherein using In and there is the transistor circuit of normal open type HEMT1 and nomal closed type HEMT2 as being included in use Power factor correcting (PFC) circuit in power supply in the server.

With reference to Fig. 8, the pfc circuit of the second embodiment include diode bridge 56, choking-winding 52, First capacitor 54, the transistor circuit 51 being included in above-mentioned semiconductor package part, diode 53 With the second capacitor 55.Owing to wherein normal open type HEMT1 and nomal closed type HEMT2 are described above Each other cascade connect transistor circuit 51 have include normal open type HEMT1 drain electrode 8, And the source electrode 16 of nomal closed type HEMT2 and three terminals of gate electrode 15, so at Fig. 8 Middle transistor circuit 51 is shown as having respectively drain electrode D, source electrode S and gate electrode G Three terminals.

In the pfc circuit of the second embodiment, diode bridge 56, choking-winding the 52, first electricity Container 54, the transistor circuit 51 being included in above-mentioned semiconductor package part, diode 53 and second Capacitor 55 is mounted on circuit boards.In this second embodiment, above-mentioned semiconductor package part Drain lead 38, source lead 39 and grid lead 37 are inserted respectively into the drain lead of circuit board Entrance, source lead entrance and grid lead entrance, and use such as solder to fix.Formed In pfc circuit on circuit boards, establish in this way and be included in above-mentioned semiconductor package part The connection of transistor 51.

In the pfc circuit of the second embodiment, a terminal of choking-winding 52 and diode The anode terminal of 53 is connected to the drain electrode D(of transistor 51 in this case for normal open type The drain electrode 8 of HEMT1, is shown in Fig. 1).Other terminals of choking-winding 52 are connected to the first electric capacity One terminal of device 54, and the cathode terminal of diode 53 is connected to the one of the second capacitor 55 Individual terminal.Other terminals of first capacitor 54, transistor 51 source electrode S(in the case For the source electrode 16 of nomal closed type HEMT2, see Fig. 1) and other terminals of the second capacitor 55 connect Ground.Both terminals of the first capacitor 54 are additionally coupled to the pair of terminal of diode bridge 56, and two The another pair of terminal of pole pipe bridge 56 is connected to the input terminal applying to exchange (AC) voltage to it.The Both terminals of two capacitors 55 are additionally coupled to the lead-out terminal from its output direct current (DC) voltage. The gate electrode G(of transistor 51 is the gate electrode 15 of nomal closed type HEMT2 in this case, sees Fig. 1) it is connected to gate driver (not shown).In the pfc circuit of the second embodiment, pass through Gate driver drive transistor 51 so that the AC applied from input terminal voltage is converted into D/C voltage, Thus from lead-out terminal output dc voltage.

Thus the power supply of the second embodiment has the beneficial effect that stability strengthens.Specifically, at electricity Use in source is partly the leading of the semiconductor device of any one in the first embodiment and change programme thereof Body chip 34.This advantageously enables to give power supply high stability.In this second embodiment, Describe and wherein above-mentioned partly lead with the pfc circuit in power supply in the server uses being included in The example of body device (semiconductor chip or semiconductor package part)；But, the second embodiment does not limits In this.Can make in such as electronics (electronic installation) such as computer in addition to server With above-mentioned semiconductor device (semiconductor chip or semiconductor package part).Furthermore, it is possible to be included in Any other circuit (such as, dc-dc) in power supply uses above-mentioned semiconductor device Part (semiconductor chip or semiconductor package part).

[the 3rd embodiment]

The high frequency amplifier of the 3rd embodiment is described now with reference to Fig. 9.

The high frequency amplifier of the 3rd embodiment is for including appointing in the first embodiment and change programme thereof The high frequency amplifier of the semiconductor device of meaning one.With reference to Fig. 9, the High frequency amplification of the 3rd embodiment Device includes digital predistortion circuit 41, frequency mixer 42a and 42b and power amplifier 43.Power is put Big device is also referred to as amplifier.

The non-linear distortion of digital predistortion circuit 41 compensated input signal.Frequency mixer 42a and 42b The input signal of experience nonlinear distortion compensation is mixed with AC signal.Power amplifier 43 The input signal amplification being mixed with ac signal, and include the first embodiment and change side thereof The semiconductor device of any one in case, i.e. includes wherein normal open type HEMT and nomal closed type HEMT The semiconductor chip of the transistor circuit that cascade connects the most each other.Semiconductor chip is also known as HEMT chip or transistor chip.

In the structure that figure 9 illustrates, such as, handover operation makes frequency mixer 42b will export Signal mixes with AC signal, then blended signal is sent to digital predistortion circuit 41.In the high frequency amplifier of the 3rd embodiment, in the first embodiment and change programme thereof arbitrarily The semiconductor device of one is applied to power amplifier 43, and this advantageously enables to give high frequency Amplifier is with high stability.

The all examples enumerated herein and conditional language are intended to help reader's reason for teaching purpose Solution is contributed the present invention with promotional technique and design by the present inventor, and should be to be construed as being without limitation of this Example that sample is specifically enumerated and condition, the such example being also not necessarily limited in description with the present invention is shown Advantage or the relevant tissue of inferior position.Although the invention has been described in detail embodiment, so And it should be understood that can be without departing from the spirit and scope of the present invention to the present invention's Various changes can be made for embodiment, replace and replace.

Claims

1. a semiconductor device, including:

The first transistor, described the first transistor includes first gate electrode, the first source electrode, the first leakage Electrode and the first nitride semiconductor layers, described first nitride semiconductor layers includes the first electronics Transit layer and the first electron supply layer；

Transistor seconds, described transistor seconds includes second gate electrode, the second source electrode, the second leakage Electrode and the second nitride semiconductor layers, described second nitride semiconductor layers includes the second electronics Transit layer and the second electron supply layer, described second electric leakage extremely also serves as the public affairs of described first source electrode Common electrode, described second electron transit layer has to be positioned under described second gate electrode and comprise p-type mixes The part of miscellaneous dose；And

P-type dopant diffusion impervious layer,

Wherein

Described second nitride semiconductor layers is disposed above described first nitride semiconductor layers, Wherein said p-type dopant diffusion impervious layer between described first nitride semiconductor layers with described Between second nitride semiconductor layers, and

Described first gate electrode and described second source electrode are electrically coupled to each other to set up described first crystal Pipe connects to the cascade of described transistor seconds.

Semiconductor device the most according to claim 1, wherein

Described first electron supply layer is thicker than described second electron supply layer.

Semiconductor device the most according to claim 1, wherein

Distance between described first gate electrode and described first drain electrode is more than described first gate electrode And the distance between described first source electrode.

Semiconductor device the most according to claim 1, wherein

Described p-type dopant diffusion impervious layer comprises the Al content AlGaN and AlN not less than 0.5 In any one.

Semiconductor device the most according to claim 1, wherein

As described first source electrode and described second drain electrode described public electrode by with form institute State the first drain electrode metal identical with the metal that described second source electrode is used to be formed.

Semiconductor device the most according to claim 1, wherein

Described public electrode as described first source electrode and described second drain electrode is from described The semiconductor laminated surface of diammine extends to the n doped region of described first electron transit layer.

Semiconductor device the most according to claim 1, wherein

Described public electrode as described first source electrode and described second drain electrode is from described The semiconductor laminated surface of diammine extends to the surface of described first nitride semiconductor layers N-type semiconductor layer.

Semiconductor device the most according to claim 1, wherein

Described first electron transit layer comprises GaN,

Described first electron supply layer comprises AlGaN,

Described p-type dopant diffusion impervious layer comprises any one in AlGaN and AlN,

Described second electron transit layer comprises GaN and Be, Mg, Fe as p-type dopant With any one in C, and

Described second electron supply layer comprises any one in AlGaN, InAlN and AlInGaN.

9. a power supply, including:

Transistor chip, described transistor chip includes:

The first transistor, described the first transistor include first gate electrode, the first source electrode, One drain electrode and the first nitride semiconductor layers, described first nitride semiconductor layers includes first Electron transit layer and the first electron supply layer；

Transistor seconds, described transistor seconds include second gate electrode, the second source electrode, Two drain electrodes and the second nitride semiconductor layers, described second nitride semiconductor layers includes second Electron transit layer and the second electron supply layer, described second electric leakage extremely also serves as described first source electrode Public electrode, described second electron transit layer has and is positioned under described second gate electrode and comprises p The part of type adulterant；And

P-type dopant diffusion impervious layer,

Wherein

Described second nitride semiconductor layers is disposed above described first nitride-based semiconductor Lamination, wherein said p-type dopant diffusion impervious layer between described first nitride semiconductor layers with Between described second nitride semiconductor layers, and

Described first gate electrode and described second source electrode are electrically coupled to each other to set up described first Transistor connects to the cascade of described transistor seconds.

10. a high frequency amplifier, including:

The amplifier being amplified input signal, described amplifier includes transistor chip, described crystalline substance Body die includes:

P-type dopant diffusion impervious layer,

Wherein

11. 1 kinds of methods being used for producing the semiconductor devices, described method includes:

Form the first nitride semiconductor layers, p-type dopant diffusion impervious layer and the second nitride Semiconductor laminated, described first nitride semiconductor layers includes the first electron transit layer and the first electronics Supplying layer, described second nitride semiconductor layers includes the second electron transit layer and the supply of the second electronics Layer, each layer is respectively positioned on Semiconductor substrate, and described second electron transit layer comprises p-type dopant；

Remove described second nitride semiconductor layers corresponding to the first transistor the most to be formed The part in region, described the first transistor includes first gate electrode, the first source electrode, the first drain electrode With described first nitride semiconductor layers；

Form described first drain electrode and make described first drain electrode described first crystalline substance the most to be formed The region of body pipe covers described first nitride semiconductor layers, and forms the second source electrode and make The region of described second source electrode transistor seconds the most to be formed covers described second nitride Semiconductor laminated, described transistor seconds includes second gate electrode, the second source electrode, the second drain electrode With described second nitride semiconductor layers；

Formed and be used as described first source electrode and the public electrode of described second drain electrode；

Forming described first gate electrode makes described first gate electrode described first nitride of covering partly lead Body lamination, and formed described second gate electrode make described second gate electrode cover described second nitridation Thing is semiconductor laminated；And

By described first gate electrode with described second source electrode electric coupling to set up described the first transistor Cascade to described transistor seconds connects.

12. methods according to claim 11, wherein

Described first electron supply layer is formed thicker than described second electron supply layer.

13. methods according to claim 11, wherein

Described first gate electrode, described first drain electrode and described first source electrode are formed to make described Distance between first gate electrode and described first drain electrode is more than described first gate electrode and described the Distance between one source electrode.

14. methods according to claim 11, wherein

Described p-type dopant diffusion impervious layer is not less than in AlGaN and AlN of 0.5 by Al content Any one formed.

15. methods according to claim 11, wherein

16. methods according to claim 11, wherein

Described first electron transit layer is extended to from the surface of described second nitride semiconductor layers It is described public that n doped region is formed as described first source electrode and described second drain electrode Electrode.

17. methods according to claim 11, wherein

Described first nitride-based semiconductor is extended to from the surface of described second nitride semiconductor layers The n-type semiconductor layer on the surface of lamination is formed as described first source electrode and described second leakage The described public electrode of electrode.

18. methods according to claim 11, wherein

Described first electron transit layer comprises GaN,

Described first electron supply layer comprises AlGaN,