CN103871469A - Nonvolatile memory apparatus, operating method thereof, and data processing system having the same - Google Patents

Nonvolatile memory apparatus, operating method thereof, and data processing system having the same Download PDF

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Publication number
CN103871469A
CN103871469A CN201310206540.0A CN201310206540A CN103871469A CN 103871469 A CN103871469 A CN 103871469A CN 201310206540 A CN201310206540 A CN 201310206540A CN 103871469 A CN103871469 A CN 103871469A
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data
programming
verification operation
marking signal
pnv
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CN103871469B (en
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李仁秀
裴智慧
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SK Hynix Inc
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Hynix Semiconductor Inc
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
    • G06F12/023—Free address space management
    • G06F12/0238—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
    • G06F12/0246—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory in block erasable memory, e.g. flash memory
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3436—Arrangements for verifying correct programming or erasure
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/72—Details relating to flash memory management
    • G06F2212/7209—Validity control, e.g. using flags, time stamps or sequence numbers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3436—Arrangements for verifying correct programming or erasure
    • G11C16/3454—Arrangements for verifying correct programming or for detecting overprogrammed cells
    • G11C16/3459—Circuits or methods to verify correct programming of nonvolatile memory cells

Abstract

Provided is a nonvolatile memory apparatus which writes data into a memory cell according to a program and verify (PNV) operation, wherein the nonvolatile memory apparatus performs the PNV operation for first data during a first time, and performs a plurality of PNV operations for second data during the first time.

Description

Nonvolatile memory devices, method of operating and there is its data handling system
The cross reference of related application
The application requires the right of priority of the korean patent application that on Dec 12nd, 2012 is 10-2012-0144310 to the application number of Department of Intellectual Property of Korea S submission, and its full content is incorporated herein by reference.
Technical field
The present invention relates to semiconductor device in general, more specifically, relates to the method for operating of Nonvolatile memory devices, Nonvolatile memory devices, and has the data handling system of Nonvolatile memory devices.
Background technology
Nonvolatile memory devices can comprise flash memory, phase transformation RAM(PCRAM), resistive RAM(ReRAM), magnetic ram (MRAM) etc.Particularly, PCRAM or MRAM write and the Nonvolatile memory devices of sense data according to current driving method.
During the programming operation of Nonvolatile memery unit, carry out programming and checking (PNV) operation with data writing exactly.
Particularly, in the Nonvolatile memory devices based on current driving method, due to the inconsistent distribution of resistance of the various factors existing in program path and each unit, after programming operation, the distribution of resistance of each unit may depart from the scope of expectation.In the time that distribution of resistance departs from the scope of expectation, sensing surplus may reduce.In the case, can not ensure the reliability of reading out data.Therefore, the programming operation of Nonvolatile memory devices is followed proof procedure, by proof procedure, the distribution of resistance of each unit is adjusted in the scope of expectation.
Usually, in period of data write operation by PNV(programming and checking) pulse (a) enables, in the part of PNV period, programming pulse (b) is enabled with by data write unit.In addition, after programming pulse (b) is prohibited, will verifies and compare pulse (c) and enable to check that data are written in unit whether accurately, judge whether thus to need extra programming operation.
Nonvolatile memory devices develops into multi-level-cell (MLC) method from single level-cell (SLC) method.No matter Nonvolatile memory devices is based on SLC method or MLC method realizes, all to carry out the PNV process for each data level according to predetermined timing.
Referring to Fig. 2, the pulse (t101 to t108) being enabled while (a) being illustrated in all data programings to memory cell array, for example, write-enable pulse WE.Here, t101 to t108 can be the timing period.In addition, (b1), (b2) and (b3) represent to write there is longer programming time data (for example, the first data) time PNV pulse, (c1), (c2) and (c3) represent for example, PNV pulse while writing the data (, the second data) with shorter programming time.
Referring to (b1) and (c1), at time point t101, be enabled at the same time being enabled with pulse (a) for the PNV pulse that writes the first data and the second data.In the case, because the PNV time for the second data is shorter, be prohibited at time point t102 for the PNV pulse of the second data, and be prohibited at time point t103 for the PNV pulse of the first data.
Therefore, after being prohibited, the PNV pulse for the second data till be prohibited during required time Δ t1 for the PNV pulse of the first data, carries out device for the programming operation of the second data in waiting status.
Referring to (b2) and (c2), be enabled to carry out PNV operation for the PNV pulse of the first data at time point t101.Now, be prohibited for the PNV pulse of the second data.When the PNV pulse for the first data is after time point t103 is prohibited, be enabled to carry out the PNV operation for the second data from time point t104 to time point t105 for the PNV pulse of the second data.Then, be again enabled at time point t106 for the PNV pulse of the first data.
In the case, in the time carrying out the PNV operation (Δ t2) that is used for the first data, carry out the device operating for the PNV of the second data in waiting status, and in the time carrying out the PNV operation (Δ t3) that is used for the second data, carry out the device of the PNV operation that is used for the first data in waiting status.
Referring to (b3) and (c3), after the PNV operation (t101～t107) for the first data completes, carry out the PNV operation (t107～t108) for the second data.Therefore, during time Δ t4, carry out the device operating for the PNV of the second data in waiting status, during time Δ t5, carry out the device of the PNV operation that is used for the first data in waiting status.
In this PNV method, after the programming operation for all data all completes, carry out once verification operation or programming data (b1 and c1) again.Corresponding data level is alternately carried out to PNV operation (b2 and c2).Alternatively, after having operated for the PNV of any one data level, carry out the PNV operation (b3 and c3) for another data level.
Therefore,, in the time programming and checking has the data of short programming time, after finishing, just carries out the programming operation of the long data of programming time next PNV operation.Therefore the time that, programming operation needs is long.For data writing exactly, the number of times of PNV operation inevitably increases.Because the number of times of PNV operation increases, thereby stand-by period accumulation has increased the overall PNV time.Therefore, may reduce the performance of whole system.
Summary of the invention
In one embodiment of the invention, proposed a kind of according to PNV method by the Nonvolatile memory devices of writing data into memory unit, wherein, described Nonvolatile memory devices is carried out the PNV operation for the first data during the very first time, and during the very first time, carries out the multiple PNV operations for the second data.
In one embodiment of the invention, a kind of Nonvolatile memory devices comprises: memory cell array, and described memory cell array comprises the multiple memory cells that are connected between multiple word lines and multiple bit line; Code translator, described code translator is configured to word line and the bit line that selection is connected with the memory cell that will choose; Write driver/sensing amplifier (WD/SA) circuit, said write driver/sensing amplifier (WD/SA) circuit is configured to data to write the memory cell of choosing, and memory cell reading out data from choosing; Judging unit, described judging unit is configured to: during programming mode, judge whether the PNV operation of each level that will be recycled and reused for the data that will programme, and produce marking signal; And controller, described controller is configured to: control code translator and WD/SA circuit in response to marking signal, optionally to access the memory cell for each level of data.
In one embodiment of the invention, a kind of method of operating of Nonvolatile memory devices comprises the following steps: when from main frame transfer address, data and program command, enter programming mode; During the very first time, carry out the PNV operation of the first data for programming; And the multiple PNV that carry out the second data for programming during the very first time operate.
In one embodiment of the invention, a kind of data handling system comprises: Nonvolatile memory devices; And Memory Controller, described Memory Controller is configured to visit Nonvolatile memory devices in response to the request of main frame, wherein, Nonvolatile memory devices operates and during the very first time, carries out for multiple PNV of the second data for the PNV of the first data by writing data into memory unit, in execution during the very first time according to PNV method and operates.
In one embodiment of the invention, a kind of data handling system comprises: processor, and described processor is configured to control integrated operation; Working storage, described working storage is configured to store for the required application of Operation Processor, data and control signal; Nonvolatile memory devices, described Nonvolatile memory devices is accessed by processor; And user interface, described user interface is configured to carry out the data I/O between processor and user, wherein, Nonvolatile memory devices operates and during the very first time, carries out for multiple PNV of the second data for the PNV of the first data by writing data into memory unit, in execution during the very first time according to PNV method and operates.
Brief description of the drawings
Feature of the present invention, aspect and embodiment are described by reference to the accompanying drawings, wherein:
Fig. 1 is the sequential chart for explaining general PNV pulse;
Fig. 2 is the sequential chart for explaining general PNV process;
Fig. 3 is the sequential chart for explaining PNV process according to an embodiment of the invention;
Fig. 4 is the block diagram of Nonvolatile memory devices according to an embodiment of the invention;
Fig. 5 is the block diagram of the judging unit of Fig. 4;
Fig. 6 is the block diagram of the PNV control module of Fig. 4;
Fig. 7 is for explaining the process flow diagram of the method for operating of Nonvolatile memory devices according to an embodiment of the invention;
Fig. 8 is the sequential chart for explaining the PNV process occurring based on mark according to an embodiment of the invention;
Fig. 9 is the block diagram of data handling system according to an embodiment of the invention; And
Figure 10 is the block diagram of data handling system according to another embodiment of the invention.
Embodiment
Hereinafter, describe according to the method for operating of Nonvolatile memory devices of the present invention, Nonvolatile memory devices via exemplary embodiment with reference to the accompanying drawings, and there is the data handling system of Nonvolatile memory devices.
Referring to Fig. 3, Nonvolatile memory devices can be configured to: under programming mode, carry out twice or more times operation of PNV for the second data at the PNV time durations for the first data.
For convenience of description, suppose that the first data programme with low speed, the second data are with high speed programming.So, must be longer than the PNV time for the second data for the PNV time possibility of the first data.
Therefore, when the write-enable signal (a) for entering programming mode is enabled at t1 point, can start for the PNV operation of the first data, and can finish at t2 point for a PNV operation PNV_LD1 of the first data.Now, because the second data have high program speed, so can carry out twice during the period (t1～t2) or more times PNV operation.In Fig. 3, during the period (t1～t2), can carry out for three PNV of the second data and operate PNV_SD1, PNV_SD2 and PNV_SD3.
In addition, Nonvolatile memory devices enters for the point of the programming mode of the second data and can enter for the time point of the programming mode of the first data and synchronize or asynchronous with Nonvolatile memory devices.
Even at the 2nd PNV operation PNV_LD2(t2～t3 for the first data) during, multiple PNV operation PNV_SD4, PNV_SD5 and PNV_SD6 for the second data also can be carried out.
In the time that programming operation can pass through after the 2nd PNV operation PNV_LD2 for the first data, can finish for the PNV process of the first data.Can be after the PNV operation PNV_SD6 for the second data when failure when programming operation, carry out for the extra PNV of the second data and operate PNV_SD7 and PNV_SD8, and whole programming operation finishes.
So, (for example under programming mode, need the data of long programming time, logic level is 0 data, and all bits are all 0 data in MLC situation) the PNV period during, can carry out need to shorter programming time data (for example, logic level is 1 data, and any one bit is all 1 data in MLC situation) multiple PNV operations.Therefore, can ensure the reliability of the data that need short programming time.Particularly, when the programming reliability of data that need to long programming time is during lower than the programming reliability of the data of the short programming time of needs, can improve programming reliability and program speed.
Referring to Fig. 4, Nonvolatile memory devices 10 can comprise: memory cell array 110, Overall word line's switch (GXSW) 120, line decoder 130, column decoder 140, write driver/sensing amplifier (WD/SA) circuit 150, judging unit 160 and controller 170.
Memory cell array 110 can comprise multiple unit memory cells, for example, be connected electrically in respectively the multiple Nonvolatile memery units between multiple word lines and multiple bit line.In addition, memory cell array 110 can be configured to one or more piece, and each memory cell may be implemented as SLC or MLC.
GXSW(Overall word line switch) 120 can be electrically connected with corresponding word line, and control by the block selection signal providing from Block decoder (not shown), to be provided for, default word line voltage is offered to the path of choosing memory cell and not choosing memory cell.
Line decoder 130 and column decoder 140 can be configured to select respectively word line and bit line according to the address signal providing from controller 170.
WD/SA circuit 150 can be configured to: during the programming operation of programming mode, receive the data that provide from controller 170 via input circuit (not shown), and by the writing data into memory cell array 110 receiving.In addition, WD/SA circuit 150 can be configured to: during the verification operation of read mode or programming mode, read the data from memory cell array 110.
Judging unit 160 can be configured to: during programming mode, in response to verification command read the data that are written in memory cell array 110, by the data that read and the data (hereinafter, being called data writing) that will write compare, result produces marking signal (flag signal) and the marking signal of generation is offered to controller 170 based on the comparison.Whether marking signal can comprise with each level of the data that will programme needs extra PNV to operate relevant information.
Controller 170 can be configured to: during read mode, receive the address from main frame (not shown), and Control peripheral circuit 120 to 150 is to be sent to main frame by the data that read from memory cell array 110.
In addition, controller 170 can be configured to: during programming mode, receive address and data from main frame.Controller 170 can comprise PNV control module 172, and the peripheral circuit 120 to 160 that described PNV control module 172 is configured to control store cell array 110 is with by writing data into memory cell array 110.Especially,, during the verification operation of programming mode, PNV control module 172 can be carried out the programming operation for each level of data writing independently in response to the marking signal receiving from judging unit 160.
More specifically, in the time need to repeating PNV operation to each level of the data that will programme according to the marking signal providing from judging unit 160, PNV control module 172 can be controlled PNV and operate to carry out in the memory cell that will write corresponding data.In the time not needing repetition PNV operation, PNV control module 172 can be controlled and no longer carry out PNV operation.For this operation, PNV control module 172 with reference to offering address and the data of controller 170, is carried out independently for the PNV of corresponding memory cell and is operated according to operating relevant information (being represented by marking signal) with the PNV that whether will be recycled and reused for each data level during programming mode.
Referring to Fig. 5, judging unit 160 can comprise comparing unit 162 and marking signal generating unit 164.
In the time that Nonvolatile memory devices enters programming mode, WD/SA circuit 150 can be written to the specified memory cells memory cell array 110 by the data that provide from controller 170.Now, the data that provide from controller 170 are data writing WD.Then,, in the time that verification command is enabled, comparing unit 162 can receive the data RD being written in memory cell array 110 via WD/SA circuit 150.In addition, comparing unit 162 can receive data writing WD from controller 170, and data writing WD and the data RD receiving are compared.
Marking signal generating unit 164 can be configured to produce the marking signal F of the comparative result that comprises comparing unit 162.
Comparing unit 162 can come for each level of data writing WD from memory cell array 110 reading out datas according to the control of controller 170, and the data RD reading and data writing WD are compared.For example, suppose that the data of the first level will be written in the first module group of memory cell array 110, the data of second electrical level will be written in the second unit group of memory cell array 110.After being written to respectively first module group and second unit group according to program command and by the first data and the second data, comparing unit 162 can receive the first data, compare from the first module group reading out data of memory cell array 110 and by the first data and the data that read from controller 170.Comparing unit 162 can receive the second data, compare from second unit group reading out data and by the second data and the data that read from controller 170.
Marking signal generating unit 164 can produce marking signal F according to the comparative result of comparing unit 162, and described marking signal F has the information relevant with whether needing extra PNV operation and program directions.
,, when the comparative result of comparing unit 162 is reading out data RD and data writing WD when mutually the same, marking signal generating unit 164 produces marking signal F to represent not need repetition PNV.When the comparative result of comparing unit 162 is need to repeat PNV time, marking signal generating unit 164 produces marking signal F and need to repeat PNV or whether will increase or reduce the curtage that will apply representing.Because general PNV operation can be carried out in the time increasing step by step or reduce curtage, so whether will increase or reduce curtage determine according to the level of reading out data RD.
In addition, marking signal generating unit 164 can produce the marking signal F for each level of data writing WD., marking signal generating unit 164 can produce respectively for the marking signal of the first data with for the marking signal of the second data.Therefore, for example can produce multiple marking signal F(, the first marking signal and the second marking signal), and each in these marking signals F can comprise the signal with one or more bit.In addition, marking signal generating unit 164 can produce a marking signal for all data.In the case, marking signal F can comprise the individual signals of many bits.
Referring to Fig. 6, PNV control module 172 can comprise switch control part 1721 and WD/SA control part 1723.
During the first programming operation entering after programming mode, switch control part 1721 and WD/SA control part 1723 can be controlled so as to according to the address and the data that provide from controller 170 and carry out the programming operation for corresponding memory cell.
Then, when comprising that when whether repeating marking signal F that PNV operates relevant information and offer PNV control module 172, switch control part 1721 can drive in response to marking signal F the word line being connected with the memory cell that will carry out PNV operation.In addition, WD/SA control part 1723 can drive in response to marking signal F the WD/SA being connected with the memory cell that will carry out PNV operation.
As described in reference to Fig. 5, marking signal F comprises with the PNV that whether will be recycled and reused for each level of data writing WD and operates relevant information.Therefore, can data writing WD be accessed independently according to marking signal to the corresponding memory cell of wanting data writing, repeatedly carry out thus PNV operation.
In other words, when being recycled and reused for PNV when operation of data of the first level, switch control part 1721 can be controlled GXSW120, and WD/SA control part 1723 can control WD/SA circuit 150, to access the first module group of the data that will write the first level.In the time need to being recycled and reused for the PNV operation of data of second electrical level, switch control part 1721 can be controlled GXSW120, and WD/SA control part 1723 can be controlled WD/SA circuit 150, to access the second unit group of the data that will write second electrical level and to carry out PNV operation.
In addition,, after corresponding data level is repeated to PNV operation, judging unit 160 can not considered to operate for the PNV operation of different pieces of information level, and judges whether to be recycled and reused for the PNV operation of corresponding data level.
Referring to Fig. 7, in the time that Nonvolatile memory devices enters programming mode WRITE, can carry out independently the PNV operation for the first data WD1 and the second data WD2.
First, describe the situation of the first data WD1 programming.In the time that address and data are sent to controller 170, in step S101, according to the control of PNV control module 172, can access the memory cell corresponding with the address that will write the first data WD1 to carry out programming operation.After carrying out programming operation, can in step S103, carry out the read operation for verifying.Now, PNV control module 172 can be controlled GXSW120 and WD/SA circuit 150 only to access memory cell the reading out data that will write the first data.
Therefore,, in the time of reading out data, in step S105, the comparative result between the data RD1 that judging unit 160 can read according to the first data WD1 and the WD/SA circuit 150 of controlling via PNV control module 172 produces mark.When comparative result is data writing WD and reading out data RD each other when inconsistent (WD1 ≠ RD1), judging unit 160 can produce failure flags in step S107.Therefore the memory cell that, PNV control module 172 can be controlled writing the first data repeats PNV operation.
In the time that comparative result is data writing WD and reading out data RD (WD1=RD1) consistent with each other, judging unit 160 can produce successfully mark in step S109.In addition, in step S111, check and whether each unit of program (for example, page or piece) has successfully been carried out to the programming operation for the first data.In the time each unit of program successfully having been carried out to the programming operation for the first data, program enters waiting status in step S113.Otherwise, to occurring that failed storage block repeats PNV operation.
Second data of programming for being independent of the first data, carry out similar process.
,, in the time that address and data are sent to controller 170, in step S201, according to the control of PNV control module 172, can access the memory cell corresponding with the address that will write the second data WD2 to carry out programming operation.After carrying out programming operation, can in step S203, carry out the read operation for verifying.Now, PNV control module 172 can be controlled GXSW120 and WD/SA circuit 150 only to access memory cell and the reading out data that will write the second data.
Therefore,, in the time of reading out data, in step S205, the comparative result between the data RD2 that judging unit 160 can read according to the second data WD2 and the WD/SA circuit 150 of controlling via PNV control module 172 produces mark.When comparative result is data writing WD and reading out data RD each other when inconsistent (WD2 ≠ RD2), judging unit 160 can produce failure flags in step S207.Therefore the memory cell that, PNV control module 172 can be controlled writing the second data repeats PNV operation.
In the time that comparative result is data writing WD and reading out data RD (WD2=RD2) consistent with each other, judging unit 160 produces successfully mark in step S209.In addition, in step S211, check and whether each unit of program (for example, page or piece) has successfully been carried out to the programming operation for the second data.In the time each unit of program successfully having been carried out to the programming operation for the second data, program enters waiting status in step S213.Otherwise, to occurring that failed piece repeats PNV operation.
In addition, in step S30, check the programming operation of whether successfully having carried out for the first data and the second data.When successfully carried out for the first data and the second data programming operation time, programming mode finishes.Otherwise program enters waiting status in step S113 and S213.
Hereinafter with reference to Fig. 8, this programming operation is described.
For example, suppose the first data be need to longer programming time data, the second data be need to shorter programming time data.
In the time that write-enable signal (a) is enabled to enter programming mode, carry out the programming operation for the first data by the control of PNV control module 172, and judging unit 160 can produce according to the comparative result in the step S105 of Fig. 7 successfully mark in step S109.Then, owing to not needing that corresponding unit of program is repeated to PNV, so can write the first data at the time durations based on a PNV pulse <1>, and not produce the 2nd PNV pulse <2>.
Be independent of for the programming operation of the first data and carry out for the programming operation of the second data.Particularly, during producing the time (t11～t12) of the PNV pulse that is used for the first data, can produce for PNV pulse to the three PNV pulses of the second data 1., 2. and 3., to increase number of times for the PNV operation of the second data until data writing and reading out data are consistent with each other.Even if when data writing and reading out data are still inconsistent each other after the 3rd PNV pulse 3. of the PNV operation for the second data, can produce PNV pulse 4., 5. and 6., operate until two data are consistent with each other to repeat PNV.In addition,, when PNV when operation of successfully having carried out for the second data, do not produce follow-up PNV pulse 7. and 8. after the 6th PNV pulse 6..
In the time carrying out for the PNV operation of the first data in existing mode and operate for the PNV of the second data, only can carry out the once PNV operation for the second data in the PNV operating period for the first data.Therefore, the in the situation that of Fig. 8, be, to carry out PNV operation for the time durations of at least six times of the PNV pulse generating times of the first data.
But, in the present embodiment of the present invention, owing to can carry out the multiple PNV operations for the second data in the PNV operation of carrying out for the first data, so can reduce significantly to operate the required time for PNV.
Along with the number of times of PNV operation increases, the accuracy that can improve programming operation.Particularly, can improve the programming reliability of the data with high level.
In addition, Fig. 8 has illustrated for the end time point of a PNV pulse <1> of the first data and has put consistent situation with the 6th PNV pulse end time 6. for the second data.This is only an example.That is, carry out independently due to the PNV operation for the first data with for the PNV operation of the second data, institute is for the end time point of the PNV pulse of data writing WD and put for the end time of the PNV pulse of reading out data RD can be inconsistent each other.
Referring to Fig. 9, data handling system 20 can comprise the Memory Controller 210 being connected between main frame and Nonvolatile memory devices 10.
Memory Controller 210 can be configured to visit Nonvolatile memory devices 10 in response to the request of main frame, and can comprise processor 211, working storage 212, host interface 213 and memory interface 214.
Processor 211 can control store controller 210 integrated operation, working storage 212 can store the application required for operational store controller 210, data, control signal etc.
Host interface 213 can be for the agreement of conversion swap data/control signal between main frame and Memory Controller 210, and memory interface 214 is for changing the agreement of swap data/control signal between Memory Controller 210 and Nonvolatile memory devices 10.
Nonvolatile memory devices 10 can comprise that example installs as shown in Figure 4.Therefore, under programming mode, can carry out independently PNV operation to each data level, make to improve program speed and reliability.
In an embodiment of the present invention, the data handling system shown in Fig. 9 can comprise storage card, but the present invention is not limited to this.
Referring to Figure 10, data handling system 30 can comprise: Nonvolatile memory devices 10, processor 301, working storage 303 and I/O device 305.If necessary, data handling system 30 can also comprise communication module 307.
Processor 301 can comprise CPU (central processing unit) (CPU), and working storage 303 can store the application program required for operating data processing system 30, data, control signal etc.I/O device 305 provides user environment that can visit data disposal system 30, and the data handling procedure of data handling system 30 and result are offered to user.
Nonvolatile memory devices 10 can comprise that example installs as shown in Figure 4.Therefore, under programming mode, can carry out independently PNV operation to each data level, make to improve program speed and reliability.
Data handling system shown in Fig. 9 and Figure 10 can be used as disc apparatus, is used as the internal/external storage card of mobile electronic device or is used as image processor and other application chip.
Although below described some embodiment, those skilled in the art will appreciate that, the embodiment of description is only exemplary.Therefore, should not limit Nonvolatile memory devices described herein based on described embodiment.Or rather, should only limit Nonvolatile memory devices described herein according to claims and in conjunction with above description and accompanying drawing.

Claims (20)

  1. Via programming and verification operation by a Nonvolatile memory devices for writing data into memory unit, comprising:
    Circuit arrangement, described circuit arrangement is configured to: during the very first time, carry out programming and the verification operation for the first data, and during the described very first time, carry out multiple programmings and the verification operation for the second data.
  2. 2. Nonvolatile memory devices as claimed in claim 1, wherein, described circuit arrangement comprises:
    Judging unit, described judging unit is configured to: during programming mode, produce marking signal according to programming and the verification operation that whether will be recycled and reused for each level of the data that will programme; And
    Controller, described controller is configured to: control the memory cell that will optionally access for each level of described data in response to described marking signal.
  3. 3. Nonvolatile memory devices as claimed in claim 2, wherein, described controller is configured to: in response to repeating the programming of described the first data and the marking signal of verification operation, control will write the memory cell of described the first data by selectivity accessing.
  4. 4. Nonvolatile memory devices as claimed in claim 2, wherein, described controller is configured to: in response to repeating the programming of described the second data and the marking signal of verification operation, control will write the memory cell of described the second data by selectivity accessing.
  5. 5. a Nonvolatile memory devices, comprising:
    Memory cell array, described memory cell array comprises the multiple memory cells that are connected between multiple word lines and multiple bit line;
    Code translator, described code translator is configured to word line and the bit line that selection is connected with the memory cell that will choose;
    Write driver/sense amplifier, said write driver/sense amplifier is configured to: data are write to the memory cell of choosing, and memory cell reading out data from choosing;
    Judging unit, described judging unit is configured to: during programming mode, judge whether programming and the verification operation of each level that will be recycled and reused for the data that will programme, and produce marking signal; And
    Controller, described controller is configured to: control described code translator and said write driver/sense amplifier in response to described marking signal, optionally to access the memory cell for each level of described data.
  6. 6. Nonvolatile memory devices as claimed in claim 5, wherein, the described data that will programme comprise the first data and the second data, and
    Described controller is configured to: during the very first time, carry out programming and the verification operation for described the first data in response to described marking signal, and during the described very first time, carry out multiple programmings and the verification operation for described the second data.
  7. 7. Nonvolatile memory devices as claimed in claim 5, wherein, the described data that will programme comprise the first data and the second data, and
    Described judging unit is configured to produce for the first marking signal of described the first data with for the second marking signal of described the second data.
  8. 8. Nonvolatile memory devices as claimed in claim 7, wherein, described controller is configured to: control described code translator and said write driver/sense amplifier in response to described the first marking signal, to select to write the memory cell of described the first data.
  9. 9. Nonvolatile memory devices as claimed in claim 7, wherein, described controller is configured to: control described code translator and said write driver/sense amplifier in response to described the second marking signal, to select to write the memory cell of described the second data.
  10. 10. a data handling system, comprising:
    Nonvolatile memory devices; And
    Memory Controller, described Memory Controller is configured to visit described Nonvolatile memory devices in response to the request of main frame,
    Wherein, described Nonvolatile memory devices is configured to: according to programming and verification operation by writing data into memory unit, during the very first time, carrying out for the programming of the first data and verification operation and during the described very first time, carrying out the multiple programmings and the verification operation that are used for the second data.
  11. 11. data handling systems as claimed in claim 10, wherein, described Nonvolatile memory devices comprises:
    Judging unit, described judging unit is configured to: during programming mode, produce marking signal according to programming and the verification operation that whether will be recycled and reused for each level of the data that will programme; And
    Controller, described controller is configured to: control the memory cell that will optionally access for each level of described data in response to described marking signal.
  12. 12. data handling systems as claimed in claim 11, wherein, described controller is configured to: in response to repeating the programming of described the first data and the marking signal of verification operation, control will write the memory cell of described the first data by selectivity accessing.
  13. 13. data handling systems as claimed in claim 11, wherein, described controller is configured to: in response to repeating the programming of described the second data and the marking signal of verification operation, control will write the memory cell of described the second data by selectivity accessing.
  14. 14. 1 kinds of data handling systems, comprising:
    Processor, described processor is configured to control integrated operation;
    Working storage, described working storage is configured to store for operating the required application of described processor, data and control signal;
    Nonvolatile memory devices, described Nonvolatile memory devices is by described processor access; And
    User interface, described user interface is configured to carry out the data I/O between described processor and user,
    Wherein, described Nonvolatile memory devices is configured to: according to programming and verification operation by writing data into memory unit, during the very first time, carrying out for the programming of the first data and verification operation and during the described very first time, carrying out the multiple programmings and the verification operation that are used for the second data.
  15. 15. data handling systems as claimed in claim 14, wherein, described Nonvolatile memory devices comprises:
    Judging unit, described judging unit is configured to: during programming mode, produce marking signal according to programming and the verification operation that whether will be recycled and reused for each level of the data that will programme; And
    Controller, described controller is configured to: control the memory cell that will optionally access for each level of described data in response to described marking signal.
  16. 16. data handling systems as claimed in claim 15, wherein, described controller is configured to: in response to repeating the programming of described the first data and the marking signal of verification operation, control will write the memory cell of described the first data by selectivity accessing, and
    Wherein, described controller is configured to: in response to repeating the programming of described the second data and the marking signal of verification operation, control will write the memory cell of described the second data by selectivity accessing.
  17. The method of operating of 17. 1 kinds of Nonvolatile memory devices, comprises the following steps:
    When from main frame transfer address, data and program command, enter programming mode;
    During the very first time, carry out programming and the verification operation of the first data for programming; And
    During the described very first time, carry out multiple programmings and the verification operation of the second data for programming.
  18. 18. methods of operating as claimed in claim 17, wherein, for programming and the verification operation of described the first data with carry out concurrently for programming and the verification operation of described the second data.
  19. 19. methods of operating as claimed in claim 18, further comprising the steps of:
    Produce the first marking signal according to the result of described the first data; And
    According to described the first marking signal, optionally access will write the memory cell of described the first data, and repeats described programming and verification operation.
  20. 20. methods of operating as claimed in claim 19, further comprising the steps of:
    Produce the second marking signal according to the result of described the second data; And
    According to described the second marking signal, optionally access will write the memory cell of described the second data, and repeats described programming and verification operation.
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