CN103856202A - Output buffer circuit capable of improving stability - Google Patents
Output buffer circuit capable of improving stability Download PDFInfo
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- CN103856202A CN103856202A CN201410091393.1A CN201410091393A CN103856202A CN 103856202 A CN103856202 A CN 103856202A CN 201410091393 A CN201410091393 A CN 201410091393A CN 103856202 A CN103856202 A CN 103856202A
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Abstract
The invention discloses an output buffer circuit capable of improving stability. The output buffer circuit comprises an operational amplifier and an output control unit, wherein the operational amplifier is provided with an output end, the output control circuit is connected between the output end of the operational amplifier and a capacitive load in a coupled mode and used for generating a signal output path between the output end of the operational amplifier and the capacitive load, and the signal output path has adjustable impedance. The operational amplifier outputs a time phase to charge the capacitive load and enables the output control unit to generate first impedance. When the capacitive load is charged to a preset level, the output control unit generates second impedance larger than the first impedance.
Description
This case is to be the divisional application of the application for a patent for invention that on 03 04th, 2010, application number are 201010126909.3, denomination of invention is " can improve the output buffer of stability " applying date.
Technical field
The present invention relates to a kind of output buffer that improves stability, relate in particular to a kind of signal path output impedance of passing through to adjust operational amplifier, improve the output buffer of the phase margin of operational amplifier.
Background technology
Output buffer (Output Buffer) is usually used in various electronic installation, is used for isolation signals input and output, to avoid signal input part to be subject to load effect, and strengthens the ability that promotes load.For example, in liquid crystal indicator, source electrode driver is, by output buffer, the each pixel on liquid crystal panel is charged to corresponding voltage levvl, drives the corresponding liquid crystal molecule of each pixel.Therefore, there are very large relation in the driving force of output buffer and the display quality of liquid crystal indicator and reaction time.
Please refer to Fig. 1, Fig. 1 is the schematic diagram of a known sources driver 10.Source electrode driver 10 includes displacement Huan Cun Qi ﹙ shift register ﹚ 11, data bolt lock device (or being called line buffer) 12, digital analog converter 13, output buffer 14 and output switch 15.Wherein, offset buffer 11 is used for, according to frequency signal CLK, sequentially receiving image data DATA.When after the image data receiving corresponding to horizontal scanning line, the data load signal LOAD that data bolt lock device 12 can produce according to time schedule controller (not shown), temporary data in acquisition offset buffer 11, so that offset buffer 11 can continue to receive the image data of next horizontal scanning line.Then, digital pixel data stored data bolt lock device 12 is converted to analog voltage by digital analog converter 13, to export output buffer 14 to.Output buffer 14 is used to provide enough driving forces, and output switch 15 is sequentially coupled to output buffer 14 corresponding data wire DL, to drive corresponding data wire DL.
In Fig. 1, output buffer 14 and output switch 15 are called as the output buffer of source electrode driver 10.Specifically, as shown in Figure 2, output buffer 14 includes operational amplifier 110, and output switch 15 includes switch SW, sets up signal transmission path in order to the output pad P via source electrode driver 10 with corresponding data wire DL.Operational amplifier 110 has positive input IN+, reverse input end IN-and output OUT.Positive input IN+ is used for receiving analog voltage; Output OUT is coupled to reverse input end IN-, forms negative feedback loop.The analog voltage that operational amplifier 110 receives according to positive input IN+, is urged to a certain voltage levvl by the voltage of data wire DL of the output pad P that is connected in source electrode driver 10.But in order to drive pixels different on same data wire at different time points, source electrode driver 10 must usually upgrade this analog voltage.Therefore, when upgrading when this analog voltage, source electrode driver 10 can make switch SW present off state, until when preparation driving data lines DL, just can make switch SW open (turned on), to export the analog voltage after upgrading to corresponding data wire DL.
In the time that switch SW is opened, the output OUT of operational amplifier 110 is electrically connected to data wire DL via output pad P.In general, determined by capacitive load CLOAD, the conduction resistance value of switch SW and the output resistance of operational amplifier 110 of corresponding data wire DL the stabilization time of output voltage.But known source electrode driver, in order to reduce power loss, constantly reduces the direct current of output buffer output stage, cause the phase margin of operational amplifier constantly to decline, cause rise stabilization time.In this case, the test Selecting time of output voltage also has to extend backward, and testing cost is constantly improved.
Summary of the invention
The present invention discloses a kind of output buffer that improves stability.Described output buffer includes operational amplifier, has output; And output control unit, be coupled between this output and capacitive load of this operational amplifier, be used for being created in the signal path output between this output and the capacitive load of this operational amplifier, this signal path output has adjustable impedance magnitude; When wherein this operational amplifier is exported, so that this is discharged and recharged capacitive load, make this output control unit produce the first impedance; And in the time that this capacitive load is charged to preset level, this output control unit produces the second impedance that is greater than this first impedance.
The present invention separately discloses a kind of output buffer that improves stability.Described output buffer includes operational amplifier, has output; And output control unit, be coupled between this output and capacitive load of this operational amplifier, be used for being created in the signal path output between this output and the capacitive load of this operational amplifier, this signal path output has the impedance of resettable size; When wherein this operational amplifier is exported, so that this is discharged and recharged capacitive load, make this output control unit produce the first impedance; And Preset Time after starting mutually in the time of the output of this operational amplifier, this output control unit produces the second impedance that is greater than this first impedance.
The present invention separately discloses a kind of output buffer that improves stability.Described output buffer includes operational amplifier, has output; And output control unit, be coupled between this output and capacitive load of this operational amplifier, be used for being created in the signal path output between this output and the capacitive load of this operational amplifier, this signal path output has the impedance of resettable size; When wherein this operational amplifier is exported, so that this is discharged and recharged capacitive load, make this output control unit produce the first impedance; And in the time that the level that discharges and recharges of this capacitive load reaches stable state, this output control unit produces the second impedance that is greater than this first impedance.
Main purpose of the present invention is to provide a kind of output buffer that improves stability.Output buffer of the present invention, by the outgoing route impedance magnitude of control algorithm amplifier, is adjusted the dead-center position of operational amplifier, to shorten stabilization time and testing time.
Therefore, the testing cost of source electrode driver can be lowered effectively, and promotes its competitiveness.
Brief description of the drawings
Fig. 1 is the schematic diagram of a known sources driver.
Fig. 2 is the schematic diagram of an output buffer of the source electrode driver of Fig. 1.
Fig. 3 is the schematic diagram of an output buffer of the embodiment of the present invention.
Fig. 4 is the signal timing diagram of the output buffer of Fig. 3.
Fig. 5 is the schematic diagram of an output buffer of another embodiment of the present invention.
Fig. 6 is the signal timing diagram of the output buffer of Fig. 5.
Fig. 7 is the schematic diagram of an output buffer of further embodiment of this invention.
Wherein, description of reference numerals is as follows:
10 source electrode drivers
11 offset buffers
12 data bolt lock devices
13 digital analog converters
14 output buffers
15 output switchs
CLK frequency signal
DATA image data
LOAD data load signal
110,31,51,71 operational amplifiers
SW, SW1 switch
P exports pad
DL data wire
IN+ positive input terminal
The anti-input of IN-
OUT output
CLOAD capacitive load
30,50,70 output buffers
32,52,72 output control units
PSW1～PSW6 PMOS switch
NSW1～NSW6 nmos switch
OPC, OPC1～OPC6, OPCB1～OPCB6 control signal
33,53,73 control signal generation units
LS1～LSn level conversion device
MUX multiplexer
LG logical signal
GND, VDD1～VDDn voltage levvl
Embodiment
Please refer to Fig. 3, Fig. 3 is the schematic diagram of an output buffer 30 of the embodiment of the present invention.Output buffer 30 includes operational amplifier 31, capacitive load CLOAD and output control unit 32.Operational amplifier 31 has positive input terminal IN+, anti-input IN-and output OUT.Positive input terminal IN+ is used for receiving analog voltage; Output OUT is coupled to reverse input end IN-, forms negative feedback loop.The analog voltage that operational amplifier 31 receives according to positive input terminal IN+, produces the output voltage with corresponding level to output OUT.Output control unit 32 is coupled between the output OUT and capacitive load CLOAD of operational amplifier 31, the electric connection being used between output OUT and the capacitive load CLOAD of control algorithm amplifier 31, to form signal path output, and in the time that this signal path output forms, adjust the impedance magnitude of this signal path output.
Therefore, in the time that operational amplifier 31 charges to capacitive load CLOAD, the embodiment of the present invention can be by adjusting the impedance magnitude of its signal path output, and the dead-center position of control algorithm amplifier, to improve the phase margin of operational amplifier.Thus, can make total system stability improve, and effectively reduce stabilization time and testing cost.
In embodiments of the present invention, output control unit 32 can include multiple output switchs, be used for respectively conducting or close the electric connection between output OUT and the capacitive load CLOAD of operational amplifier 31, to form this signal path output, and the impedance magnitude of this signal path output is to be determined by the number of switches of conducting.
Taking Fig. 3 as example, output control unit 32 includes two groups of CMOS transmission lock switches, respectively by PMOS switch P SW1 and nmos switch NSW1, and PMOS switch P SW2 and nmos switch NSW2 form, in order to operate according to control signal OPC1, OPC2 and inversion signal OPCB1, OPCB2.Relate to the principle of CMOS transmission lock switch and be operating as well known to those of ordinary skill in the artly, do not add to repeat at this.Please refer to Fig. 4, Fig. 4 is the signal timing diagram of output buffer 30 in Fig. 3.First, phase in the time that data load, operational amplifier 31 receives the analog voltage that front stage circuits is exported.Then,, in the time that output buffer 30 wishs utilize the output voltage of operational amplifier 31 to charge to capacitive load CLOAD (phase when operational amplifier output), PMOS switch P SW1, PSW2 and nmos switch NSW1, NSW2 can all open.Now, the signal path impedance between operational amplifier 31 and capacitive load CLOAD is minimum value, and operational amplifier 31 can be discharged and recharged capacitive load CLOAD rapidly.In the time that capacitive load CLOAD is charged to a preset level (or after charging one Preset Time), part CMOS transmission lock switch can cut out, for example: switch NSW2 and PSW2, to improve the impedance magnitude of signal path between operational amplifier 31 and capacitive load CLOAD.
Thus, the embodiment of the present invention can, by adjusting the impedance magnitude of signal path output, be carried out the dead-center position of control algorithm amplifier, to improve the phase margin of operational amplifier, total system stability is improved, and effectively reduce stabilization time and testing cost.
In addition, control signal OPC1, OPC2 and inversion signal OPCB1, OPCB2 are produced by control signal generation unit 33, when its level that discharges and recharges at capacitive load CLOAD reaches stable state, for example: be charged to a preset level at capacitive load CLOAD, an or Preset Time after starting mutually in the time that operational amplifier is exported, adjust the logical level of control signal OPC1, OPC2 and inversion signal OPCB1, OPCB2, with the CMOS transmission lock switch of closed portion.
Note that in embodiments of the present invention, multiple output switchs that output control unit 32 comprises are to be realized by CMOS transmission lock switch, in order to meet the demand of the various output voltage level of operational amplifier.But in other embodiments, each output switch also can be realized by the transistor switch of arbitrary form, such as PMOS switch, nmos switch or double carrier transistor switch etc., and be not limited to this.
Certainly, the output switch quantity that output control unit 32 comprises also can be adjusted according to the actual requirements, and is not limited to this.Please refer to Fig. 5, Fig. 5 is the schematic diagram of an output buffer 50 of another embodiment of the present invention.Compared to the output buffer 30 of Fig. 3, output control unit 52 includes four groups of CMOS transmission lock switches that PMOS switch P SW3～PSW6 and nmos switch NSW3～NSW6 form, and it operates according to control signal OPC3～OPC6 and inversion signal OPCB3～OPCB6 thereof respectively.Please refer to Fig. 6, Fig. 6 is the signal timing diagram of output buffer 50.Similarly, phase in the time that data load, operational amplifier 51 receives the analog voltage that front stage circuits is exported.Then,, in the time that output buffer 50 wishs utilize the output voltage of operational amplifier 51 to charge to capacitive load CLOAD (phase when operational amplifier output), PMOS switch P SW3～PSW6 and nmos switch NSW3～NSW6 can all open.Now, the signal path impedance between operational amplifier 51 and capacitive load CLOAD is minimum value, and operational amplifier 51 can be discharged and recharged fast to capacitive load CLOAD.In the time that capacitive load CLOAD is charged to a preset level (or after charging one Preset Time), CMOS transmission lock switch time sharing segment sequentially cuts out, little by little to improve the impedance magnitude of signal path between operational amplifier 51 and capacitive load CLOAD.
Thus, in the process of sequentially closing at part output switch, the impedance meeting specific output switch of seeing on the outgoing route of operational amplifier is greater while unlatching totally, and can increase operation amplifier phase margin, total system stability is improved, effectively reduce stabilization time and reduce testing cost.
On the other hand, please refer to Fig. 7, Fig. 7 is the schematic diagram of an output buffer 70 of further embodiment of this invention.Output buffer 70 includes operational amplifier 71, capacitive load CLOAD and output control unit 72.Compared to above-described embodiment, output control unit 72 only comprises output switch SW1, is used for according to control signal OPC, and conducting or close the electric connection between output OUT and the capacitive load CLOAD of operational amplifier 71, to form signal path output.Wherein, control signal OPC is produced by control signal generation unit 73, when its level that discharges and recharges at capacitive load CLOAD reaches stable state, for example: be charged to a preset level at capacitive load CLOAD, an or Preset Time after starting mutually in the time that operational amplifier is exported, adjust the voltage levvl of control signal OPC, to control the conducting degree of output switch SW1.Thus, the embodiment of the present invention can be adjusted by the conducting degree of output switch SW1 the impedance magnitude of the signal path output of operational amplifier 71.
That is to say, in the time that output buffer 70 wishs utilize the output voltage of operational amplifier 71 to charge to capacitive load CLOAD, output switch SW1 can complete conducting, now, signal path impedance between operational amplifier 71 and capacitive load CLOAD is minimum value, and operational amplifier 71 can be discharged and recharged capacitive load CLOAD rapidly.In the time that capacitive load CLOAD is charged to stable state, for example reach a preset level, or after charging one Preset Time, output switch SW1 can change according to the level of control signal OPC, switch to incomplete conducting state, to improve the impedance magnitude of signal path between operational amplifier 71 and capacitive load CLOAD.
In general, the control signal of output switch produces the logical circuit from low pressure, therefore needs, through level conversion device (Level Shifter), to reach the level of high potential assembly, to control the unlatching of output switch or to close.In the present embodiment, control signal generation unit 73 includes level conversion device LS1～LSn and multiplexer MUX.Level conversion device LS1～LSn is used for according to logical signal LG, produces supply voltage levvl VDD1～VDDn.Multiplexer MUX is coupled to level conversion device LS1～LSn, is used for according to the level that discharges and recharges of capacitive load CLOAD, and switches output supply voltage levvl VDD1～VDDn, to produce the control signal OPC of output switch SW1.Wherein, the pass of supply voltage levvl VDD1～VDDn is VDD1>VDD2> ... >VDDn>GND.
In embodiments of the present invention, output switch SW1 can complete conducting in the time that the level of control signal OPC is VDD1, and closes completely in the time that the level of control signal OPC is GND.Because output switch SW1 is realized by CMOS transmission lock, therefore, when the level of control signal OPC is during lower than supply voltage levvl VDD1, can be learnt by the on state characteristic of cmos component, now the resistance value of the resistance value of output switch SW1 when higher than the complete conducting of output switch SW1.Produce position the zero point that the raising of this resistance value will affect operational amplifier, and improve the phase margin of operational amplifier, and shorten the stabilization time of output buffer.
In brief, the embodiment of the present invention is the extreme voltage of transistor gates by changing output switch, and the outgoing route impedance magnitude of control algorithm amplifier, to shorten the stabilization time of output buffer.Certainly, the spirit of this embodiment is not limited in listed diagram, and any output buffer that improves stability by adjusting the impedance magnitude of signal path output, all belongs to scope of the present invention.
In sum, output buffer of the present invention, by the outgoing route impedance magnitude of control algorithm amplifier, is adjusted the dead-center position of operational amplifier, to shorten stabilization time and testing time.Therefore, the testing cost of source electrode driver can be lowered effectively, and promotes its competitiveness.
The foregoing is only preferred embodiment of the present invention, all equalizations of doing according to the claims in the present invention change and modify, and all should belong to covering scope of the present invention.
Claims (33)
1. the output buffer that can improve stability, is characterized in that, includes:
Operational amplifier, has output; And
Output control unit, is coupled between this output and capacitive load of this operational amplifier, is used for being created in the signal path output between this output and the capacitive load of this operational amplifier, and this signal path output has adjustable impedance magnitude; When wherein this operational amplifier is exported, so that this is discharged and recharged capacitive load, make this output control unit produce the first impedance; And in the time that this capacitive load is charged to preset level, this output control unit produces the second impedance that is greater than this first impedance.
2. output buffer circuit as claimed in claim 1, is characterized in that, is applied to circuit of display driving.
3. output buffer circuit as claimed in claim 2, is characterized in that, this circuit of display driving is source electrode driver.
4. output buffer circuit as claimed in claim 1, is characterized in that, this output control unit includes multiple output switchs, and in the plurality of output switch, the number of switches of conducting determines the impedance magnitude of this signal path output.
5. output buffer circuit as claimed in claim 4, it is characterized in that, the plurality of output switch phase time in the time that this operational amplifier starts to export is all opened, and is charged to this preset level time part is closed detecting this capacitive load, to improve the impedance magnitude of this signal path output.
6. output buffer circuit as claimed in claim 5, is characterized in that, part this output switch of closing detect this capacitive load while being charged to this preset level time sharing segment sequentially close, little by little to improve the impedance magnitude of this signal path output.
7. output buffer circuit as claimed in claim 4, is characterized in that, each output switch of the plurality of output switch is to be realized by PMOS switch, nmos switch or CMOS transmission lock.
8. output buffer circuit as claimed in claim 4, it is characterized in that, also include control signal generation unit, be coupled to the plurality of output switch, be used for detecting the level that discharges and recharges of this capacitive load, and produce the control signal of the plurality of output switch, with according to the level that discharges and recharges of this capacitive load, control the number of switches of conducting in the plurality of output switch.
9. output buffer circuit as claimed in claim 4, is characterized in that, this output control unit is charged to after this preset level detecting this capacitive load, little by little improves the impedance magnitude of this signal path output.
10. output buffer circuit as claimed in claim 1, is characterized in that, this output control unit includes output switch, is used for conducting or close the electric connection between this output and this capacitive load of this operational amplifier, to form this signal path output; Wherein, the conducting degree of this output switch determines the impedance magnitude of this signal path output.
11. output buffer circuits as claimed in claim 10, is characterized in that, also include control signal generation unit, be coupled to this output switch, be used for detecting the level that discharges and recharges of this capacitive load, and produce the control signal of this output switch, to control the conducting degree of this output switch.
12. output buffer circuits as claimed in claim 11, is characterized in that, this control signal generation unit includes:
Multiple level conversion devices, are used for according to logical signal, produce respectively multiple supply voltage levvls; And
Multiplexer, is coupled to the plurality of level conversion device, is used for switching the plurality of supply voltage levvl of output, to produce this control signal.
13. output buffer circuits as claimed in claim 10, it is characterized in that, this output switch is the complete conducting of phase time in the time that this operational amplifier starts to export, and is charged to this preset level time part is closed detecting this capacitive load, to improve the impedance magnitude of this signal path output.
14. output buffer circuits as claimed in claim 13, is characterized in that, part this output switch of closing detect this capacitive load while being charged to this preset level time sharing segment close, little by little to improve the impedance magnitude of this signal path output.
15. 1 kinds can be improved the output buffer of stability, it is characterized in that, include:
Operational amplifier, has output; And
Output control unit, is coupled between this output and capacitive load of this operational amplifier, is used for being created in the signal path output between this output and the capacitive load of this operational amplifier, and this signal path output has the impedance of resettable size; When wherein this operational amplifier is exported, so that this is discharged and recharged capacitive load, make this output control unit produce the first impedance; And Preset Time after starting mutually in the time of the output of this operational amplifier, this output control unit produces the second impedance that is greater than this first impedance.
16. output buffer circuits as claimed in claim 15, is characterized in that, this output control unit includes multiple output switchs, and in the plurality of output switch, the number of switches of conducting determines the impedance magnitude of this signal path output.
17. output buffer circuits as claimed in claim 15, it is characterized in that, the plurality of output switch phase time in the time that this operational amplifier starts to export is all opened, and part is closed when this Preset Time after starting mutually in the time detecting the output of this operational amplifier, to improve the impedance magnitude of this signal path output.
18. output buffer circuits as claimed in claim 17, it is characterized in that, when this Preset Time after part this output switch of closing starts mutually in the time detecting this operational amplifier output, time sharing segment is sequentially closed, little by little to improve the impedance magnitude of this signal path output.
19. output buffer circuits as claimed in claim 15, is characterized in that, each output switch of the plurality of output switch is to be realized by PMOS switch, nmos switch or CMOS transmission lock.
20. output buffer circuits as claimed in claim 15, it is characterized in that, also include control signal generation unit, be coupled to the plurality of output switch, this Preset Time after starting mutually while being used for detecting this operational amplifier output, and producing the control signal of the plurality of output switch, this Preset Time after starting mutually when according to this operational amplifier output, controls the number of switches of conducting in the plurality of output switch.
21. output buffer circuits as claimed in claim 15, is characterized in that, are applied to circuit of display driving.
22. output buffer circuits as claimed in claim 21, is characterized in that, this circuit of display driving is source electrode driver.
23. output buffer circuits as claimed in claim 15, is characterized in that, after this Preset Time after this output control unit starts mutually in the time detecting this operational amplifier output, little by little improve the impedance magnitude of this signal path output.
24. output buffer circuits as claimed in claim 15, is characterized in that, this output control unit includes output switch, are used for conducting or close the electric connection between this output and this capacitive load of this operational amplifier, to form this signal path output; Wherein, the conducting degree of this output switch determines the impedance magnitude of this signal path output.
25. output buffer circuits as claimed in claim 24, is characterized in that, also include control signal generation unit, be coupled to this output switch, be used for detecting the level that discharges and recharges of this capacitive load, and produce the control signal of this output switch, to control the conducting degree of this output switch.
26. output buffer circuits as claimed in claim 25, is characterized in that, this control signal generation unit includes:
Multiple level conversion devices, are used for according to logical signal, produce respectively multiple supply voltage levvls; And
Multiplexer, is coupled to the plurality of level conversion device, is used for switching the plurality of supply voltage levvl of output, to produce this control signal.
27. output buffer circuits as claimed in claim 15, it is characterized in that, this output switch is the complete conducting of phase time in the time that this operational amplifier starts to export, and is charged to this preset level time part is closed detecting this capacitive load, to improve the impedance magnitude of this signal path output.
28. output buffer circuits as claimed in claim 27, is characterized in that, part this output switch of closing detect this capacitive load while being charged to this preset level time sharing segment close, little by little to improve the impedance magnitude of this signal path output.
29. 1 kinds can be improved the output buffer of stability, it is characterized in that, include:
Operational amplifier, has output; And
Output control unit, is coupled between this output and capacitive load of this operational amplifier, is used for being created in the signal path output between this output and the capacitive load of this operational amplifier, and this signal path output has the impedance of resettable size; When wherein this operational amplifier is exported, so that this is discharged and recharged capacitive load, make this output control unit produce the first impedance; And in the time that the level that discharges and recharges of this capacitive load reaches stable state, this output control unit produces the second impedance that is greater than this first impedance.
30. output buffer circuits as claimed in claim 29, is characterized in that, this output control unit includes multiple output switchs, and in the plurality of output switch, the number of switches of conducting determines the impedance magnitude of this signal path output.
31. output buffer circuits as claimed in claim 30, it is characterized in that, the plurality of output switch phase time in the time that this operational amplifier starts to export is all opened, and time sharing segment is sequentially closed after the level that discharges and recharges of this capacitive load reaches stable state, little by little to improve the impedance magnitude of this signal path output.
32. output buffer circuits as claimed in claim 29, is characterized in that, this output control unit includes output switch, are used for conducting or close the electric connection between this output and this capacitive load of this operational amplifier, to form this signal path output; Wherein, the conducting degree of this output switch determines the impedance magnitude of this signal path output.
33. output buffer circuits as claimed in claim 32, it is characterized in that, this output switch is the complete conducting of phase time in the time that this operational amplifier starts to export, and reach stable state rear section in the level that discharges and recharges that detects this capacitive load and close, little by little to improve the impedance magnitude of this signal path output.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410091393.1A CN103856202A (en) | 2010-03-04 | 2010-03-04 | Output buffer circuit capable of improving stability |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410091393.1A CN103856202A (en) | 2010-03-04 | 2010-03-04 | Output buffer circuit capable of improving stability |
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| Application Number | Title | Priority Date | Filing Date |
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| CN2010101269093A Division CN102195635A (en) | 2010-03-04 | 2010-03-04 | Output buffer circuit capable of improving stability |
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| CN103856202A true CN103856202A (en) | 2014-06-11 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112069768A (en) * | 2020-09-08 | 2020-12-11 | 天津飞腾信息技术有限公司 | Method for optimizing input and output delay of dual-port SRAM (static random Access memory) |
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| US20060044007A1 (en) * | 2004-08-31 | 2006-03-02 | Semtech Corporation | Method and system for adaptively controlling output driver impedance |
| US20070139021A1 (en) * | 2005-12-21 | 2007-06-21 | Tomokazu Kojima | Power supply circuit |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3659190A (en) * | 1970-10-06 | 1972-04-25 | Venus Scient Inc | Switching high-voltage power supply |
| US20050264510A1 (en) * | 2004-05-25 | 2005-12-01 | Nec Electronics Corporation | Drive circuit, operation state detection circuit, and display device |
| US20060044007A1 (en) * | 2004-08-31 | 2006-03-02 | Semtech Corporation | Method and system for adaptively controlling output driver impedance |
| US20070139021A1 (en) * | 2005-12-21 | 2007-06-21 | Tomokazu Kojima | Power supply circuit |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN112069768A (en) * | 2020-09-08 | 2020-12-11 | 天津飞腾信息技术有限公司 | Method for optimizing input and output delay of dual-port SRAM (static random Access memory) |
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Application publication date: 20140611 |
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