CN103853220A - Power supply circuit, electronic equipment and corresponding method - Google Patents
Power supply circuit, electronic equipment and corresponding method Download PDFInfo
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- CN103853220A CN103853220A CN201210528454.7A CN201210528454A CN103853220A CN 103853220 A CN103853220 A CN 103853220A CN 201210528454 A CN201210528454 A CN 201210528454A CN 103853220 A CN103853220 A CN 103853220A
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Abstract
The invention relates to a power supply circuit, electronic equipment and a corresponding method. The power supply circuit comprises a first chip and a power supply management module, wherein the first chip comprises a first terminal, a second terminal and a power supply management signal generating circuit; the power supply management signal generating circuit generates a corresponding analog control signal according to a logic state of a digital signal on a public lead connected with the first terminal, and outputs the analog control signal through the second terminal; the public lead is connected with the first terminal of the first chip, and is connected with a corresponding first terminal of at least one second chip, and the second chip comprises or does not comprise a corresponding second terminal; the power supply management module comprises a control terminal and a power supply terminal, receives the analog control signal from the control terminal, and controls the output voltage of the power supply terminal based on the analog control signal. The invention also discloses corresponding electronic equipment and method.
Description
Technical field
Embodiments of the invention relate generally to circuit field, more specifically, relate to feed circuit, electronic equipment and the correlation method of sharing power management module.
Background technology
In modern circuit, be responsible for (for example controlling target device, light emitting diode LED) chip usually need to for example, regulate the driving voltage of its target device of controlling by means of power management module (, stepup transformer boost, reducing transformer buck or buck-boost device buck-boost).Usually, chip is connected with power management module, and controls the operation of power management module by control signal.Power management module then be connected to target device.In common configuration, between target device and chip, also set up and have backfeed loop, for the information such as current voltage are returned to chip.As fruit chip determines that by the information that backfeed loop was fed to the current voltage of target device is too high or too low, it can correspondingly utilize control signal control power management module to promote or reduce the driving voltage of equipment.
In the prior art, common circuit structure is to be equipped with a special power management module for each chip.Can guarantee that so each chip can accurately control the voltage of target device.But be understandable that, this will cause higher cost.And each chip must have the pin (pin) for being connected with power management module.For the less chip of some pin, this may be inconvenient.
Because the problems referred to above need a kind of solution of supporting to be shared by multiple chips same power management module in this area.
Summary of the invention
For the problem solving the aforementioned problems in the prior and other are potential, embodiments of the invention provide a kind of feed circuit, electronic equipment and correlation method of shared power management module.
In one aspect of the invention, provide a kind of feed circuit.These feed circuit comprise: the first chip, there is the first terminal, the second terminal and power managing signal circuit for generating, wherein said power managing signal circuit for generating operation is to produce corresponding analog control signal according to the logic state of the digital signal in the common lead being connected with described the first terminal, and export described analog control signal through described the second terminal, wherein said common lead is connected with the first terminal of described the first chip, and operation is being connected with the corresponding the first terminal of at least one the second chip, and wherein said the second chip has or does not have corresponding the second terminal, and power management module, there is control terminal and power supply terminal, and operate to receive described analog control signal from described control terminal, and based on described analog control signal, the output voltage of described power supply terminal is controlled.
In another aspect of this invention, provide a kind of electronic equipment.This electronic equipment comprises: multiple chips, each described chip has the first terminal separately, and operation can provide independently digital signal on the first terminal separately, and a selected chip in wherein said multiple chips also has the second terminal and power managing signal circuit for generating; , a common lead, is connected with described multiple chips the first terminal separately; And power management module, there is power supply terminal and control terminal, described power supply terminal is connected to the target device being associated with described multiple chips, described control terminal is connected to described second terminal of described selected chip, and the described power managing signal circuit for generating of wherein said selected chip operates to control the output voltage of described power management module via described the second terminal according to the described digital signal in described common lead.
In still another aspect of the invention, provide a kind of method of supplying power to.This method of supplying power to comprises: in the first chip, detect the logic state of the digital signal on the first terminal of described the first chip, the first terminal of wherein said the first chip is connected with a common lead, and described common lead operates to be also connected with the corresponding the first terminal of at least one the second chip; In described the first chip, based on the logic state of described digital signal, produce corresponding analog control signal, and export described analog control signal through the second terminal of described the first chip; And in a power management module, receive described analog control signal, to the output voltage of described power management module is controlled accordingly.
By below describing and will be understood that, utilize embodiments of the invention, multiple chips can be shared a power management module effectively.Each chip operation regulates the output voltage of power management module with the digital signal of the lead-in wire output particular logic state to public, thereby realizes the adjusting to target device operating voltage.
Accompanying drawing explanation
Read detailed description below by reference to accompanying drawing, above-mentioned and other objects of the embodiment of the present invention, feature and advantage will become easy to understand.In the accompanying drawings, show some embodiment of the present invention in exemplary and nonrestrictive mode, wherein:
Fig. 1 shows the schematic block diagram of the electronic equipment that comprises feed circuit according to an illustrative embodiment of the invention;
Fig. 2 shows the schematic block diagram of the electronic equipment that comprises feed circuit according to an illustrative embodiment of the invention;
Fig. 3 and Fig. 4 show according to the schematic block diagram of the chip the first terminal of exemplary embodiment of the present invention;
Fig. 5 shows the exemplary operations sequential chart of the feed circuit of describing in conjunction with Fig. 2; And
Fig. 6 shows the indicative flowchart of method of supplying power to according to an illustrative embodiment of the invention.
Embodiment
Some exemplary embodiments are below with reference to the accompanying drawings described principle of the present invention and spirit.Should be appreciated that providing these embodiment is only used to make those skilled in the art can understand better and then realize the present invention, and not limit the scope of the invention by any way.
First with reference to figure 1, it shows the schematic diagram of the electronic equipment that comprises feed circuit according to an illustrative embodiment of the invention.As shown in Figure 1, electronic equipment comprises feed circuit 100, and feed circuit 100 comprise the first chip 103 and power management module 108.The first chip 103 has the first terminal 106, the second terminal 114 and power managing signal circuit for generating 115.The first terminal 106 is connected with a common lead 107, and this common lead 107 operates to be connected with the corresponding the first terminal 104,105 of at least one the second chip 101,102 in electronic equipment.The first chip 103 and the second chip 101,102 can be any special or general chips of developing known or future at present, and it operates to control the operating voltage of corresponding target device.Target device for example can comprise multi-group light-emitting diode, and every group of light emitting diode is associated with in chip 101,102 and 103 one.
In operation, each in the first chip 103 and the second chip 101,102 all can be via its corresponding the first terminal independently to lead-in wire 107 output digit signals (or claiming numerical control word), thereby realize the control to target device operating voltage, this will be explained below.Although note that and only show in the drawings two the second chips 101 and 102, this is only schematic.Can comprise the second chip of arbitrary number according to the electronic equipment of the embodiment of the present invention.
Especially, according to embodiments of the invention, the second chip 101,102 can comprise that the second terminal also can not comprise the second terminal.Particularly, the second chip 101,102 can be the chip identical with the first chip 103,, comprises the first terminal and the second terminal that is simultaneously.In this case, any one in multiple chips 101,102,103 that electronic equipment comprises can be selected to serve as the first chip.Alternatively, the second chip 101,102 also can not have the second terminal, but the chip more simple for the first chip 103, cost is lower.
The control terminal 109 of power management module 108 is connected to the second terminal 114 of the first chip 103.According to embodiments of the invention, the first chip 103 operates to produce corresponding analog control signal according to the logic state of the digital signal on lead-in wire 107, and export these analog control signals via the second terminal 114 to power management module 108, to regulate the output voltage of power management module 108.Correspondingly, power management module operates the output voltage at power supply terminal 110 places is controlled based on analog control signal.
In addition, between each target device chip associated with it, can there is backfeed loop (not illustrating in the drawings), to the operating voltage of this target device is fed back to chip.This feedback can be in real time, termly or in response to the request of chip, scope of the present invention is unrestricted in this regard.
In operation, if the first chip 103 or any one the second chip 101,102 detect that the operating voltage of the target device of associated does not meet predetermined condition (normally lower than predetermined threshold voltage), this chip can produce the digital signal of a particular logic state and export these digital signals via the first terminal to lead-in wire 107, to indicate it to wish to regulate the operating voltage of target device.Power managing signal circuit for generating in the first chip 103 and power management module 108 can be in response to the digital controlled signals that this particular logic state detected at lead-in wire on 107, and correspondingly promote or reduce the operating voltage of target device.Concrete regulative mode also will be explained below.
If all chip 101,102 ..., the operating voltage of 103 associated objects equipment (for example all conforms to a predetermined condition, all higher than predetermined threshold voltage), go between and can not have the digital signal of the particular logic state of indication booster tension on 107.In this case, according to some embodiment of the present invention, the power managing signal circuit for generating 115 of the first chip 103 operates to control power management module 108 and reduces the output voltage at power supply terminal 110 places,, reduces the output voltage that outputs to target device that is.Do be like this conducive to energy-conservation.Once the output voltage of power management module 108 has been reduced under the normal working voltage of certain target device, corresponding chip will detect this situation and indication booster tension.In such embodiments, the first chip 103 for example can be controlled the regularly output voltage of reduction power supply terminal 110 of power management module 108.For example, power management module 108 can regularly reduce the output voltage of power supply terminal 110 cycle based on 320ms.This is only exemplary, and other any suitable cycles all likely.
And according to some embodiment of the present invention, the speed of output voltage that power management module 108 reduces power supply terminal 110 is slower than the speed of booster tension.In other words,, in the time that all chips are not all indicated booster tension, power management module 108 operates to reduce lentamente the output voltage of power supply terminal 110.But if detect that any chip sends the digital signal for booster tension at lead-in wire on 107, the first chip 103 operates to control power management module 108 and promptly promotes the output voltage of power supply terminal 110.
Below with reference to Fig. 2, it shows the schematic block diagram of the electronic equipment that comprises feed circuit according to an illustrative embodiment of the invention.Be appreciated that the feed circuit of describing in conjunction with Fig. 2 are exemplary specific implementations of one of the feed circuit described with reference to figure 1 above.
As shown in Figure 2, in this embodiment, electronic equipment comprises at least one resistor 201, and it is connected between the first chip 103 and each the second chip 101,102 and power supply (VDD) via lead-in wire 107.Resistor 201 can be called " pull-up resistor ".In the embodiment shown in Figure 2, the first terminal of each chip can be the pin of open drain, for example, realize by means of devices such as MOS (metal oxide) transistor, diodes.For example, in the embodiment shown in Figure 2, the first terminal can adopt N-type MOS (NMOS) transistor to realize, and this is not necessarily certainly.Fig. 3 shows the schematic diagram of the first terminal of each chip in the first chip 103 and the second chip 101,102, and this first terminal utilizes N-type MOS transistor 301 to realize.The annexation of N-type MOS transistor 301 with lead-in wire 107 and pullup resistor 201 that Fig. 3 has gone back depicted in greater detail.Be appreciated that in such embodiments, the logic state of the digital signal in common lead 107 is the "AND" of chip 101-103 to the logic state signal of lead-in wire 107 outputs.In an example, can be logic low or zero-signal (as, low level signal) to the digital signal of particular logic state of lead-in wire 107 outputs.Usually, the resistance value of resistor 201 is fully greater than the resistance value of the first terminal of chip.For example, in certain embodiments, the resistance value of resistor 201 can be 100 kilo-ohms of left and right, and this is only exemplary certainly.
In the embodiment shown in Figure 2, each chip 101,102 ..., 103 operations with the operating voltage in response to the target device being associated with this chip higher than predetermined threshold not to described lead-in wire output digit signals.It will be appreciated by those skilled in the art that, in this case, between chip and lead-in wire 107 in fact in electric blocking state, and the digital signal of lead-in wire on 107 due to the pulling efficient of resistor 201 should and for example, in logic high (, logical one) state.
When the first chip 103 is in the time that lead-in wire detects logic high signal on 107, it can determine all chips all indication promote the output voltage of power management module 108.Now, according to some embodiment, power managing signal circuit for generating 115 in the first chip 103 and power management module 108 operate the digital signal of the particular logic state indication booster tension not detected in common lead 107, keep the output voltage of power supply terminal 110 constant.Alternatively, as mentioned above, power managing signal circuit for generating 115 and power management module 108 also operate the digital signal of the particular logic state indication booster tension not detected in common lead 107, reduce the output voltage of power supply terminal 110.For example, power managing signal circuit for generating 115 and power management module 108 operate regularly slowly reduce in this case the output voltage of power supply terminal 110, thereby reach energy-conservation object.
On the other hand, if any chip detection in the first chip 103 and the second chip 101,102 to the operating voltage of the target device of associated lower than predetermined threshold voltage, this chip operation, with to lead-in wire 107 output low level signals, drags down the signal logic of lead-in wire 107.It will be understood by those skilled in the art that the signal on whole lead-in wire 107 will for example, in logic low (, logical zero) state when any one chip is to lead-in wire when 107 output logic low signal.Correspondingly, the first chip 103 operates to control power management module 108 in response to logic low signal detected on lead-in wire 107 and promotes output voltage.Especially, for the reduction of certain target device operating voltage, power management module 108 can more promptly promote the output voltage of power supply terminal 110.
Particularly, in the embodiment shown in Figure 2, the power management module 108 in feed circuit comprises resistor 202,205 and 206, amplifier 203 and electric power management circuit 204.Electric power management circuit 204 can be for example one of following: stepup transformer, reducing transformer and buck-boost device.In operation, in the time that the first chip 103 need to improve the output voltage of power management module 108 according to the logic state of the digital signal on lead-in wire 107 is definite, operation is to produce the analog control signal lower than reference signal (in figure " ref ").For example, power managing signal circuit for generating 115 can comprise voltage digital analog converter (DAC) and/or capacitive element (not shown), its operation for example, with by particular logic state (, digital signal 0-31) is converted to corresponding analog control signal (for example, 0-250mA).Thus, power managing signal circuit for generating 115 operates to produce the analog control signal lower than reference signal ref.Digital-to-analog conversion technology is known in the art, does not repeat them here its details.Analog control signal is exported to the control terminal 109 of power management module 108 via the second terminal 114, and after the resistor 202 of flowing through, is fed to the inverting input of amplifier 203.Amplifier 203 offers electric power management circuit 204 via output terminal by its output, so that electric power management circuit 204 promotes the output voltage of supply node 110.According to embodiments of the invention, electric power management circuit 204 can be realized the adjusting to output voltage by the parameter such as pulsed modulation width (PWM), dutycycle of controlling voltage, and these are known in the art.
Otherwise, in the time of the definite output voltage without raising power management module 108 of the first chip 103, power managing signal circuit for generating 115 operates to produce the analog control signal that is not less than reference signal ref, so that voltage management circuitry keeps or reduction output voltage.
Should be appreciated that to be only a kind of possible embodiments of power management module 108 shown in Fig. 2, be not intended to limit scope of the present invention.For example, in alternative, the analog control signal that the first chip 103 is exported can be fed to the normal phase input end of amplifier 203, and reference signal is fed to the inverting input of amplifier 203.Now, when the first chip 103 determines that need to promote output voltage time, power managing signal generating means 115 operates to produce the analog control signal higher than reference signal; Vice versa.
In addition, embodiments of the invention are not limited to use the first terminal of N-type MOS transistor as the first chip and each the second chip, and P type MOS transistor is applicable equally.For example, Fig. 4 shows an embodiment who utilizes P type MOS transistor 401 to serve as the first terminal of the first chip and each the second chip.Fig. 4 depicted in greater detail the P type MOS transistor 401 feasible annexation of one with power vd D, resistor 402 (can be described as " pull-down-resistor ") and ground VSS.Be appreciated that in such embodiments, the signal logic in common lead 107 is the "or" of each chip to the logic state signal of common lead output.In an example, it can be high or one signal of logic (as, high level signal) to the digital signal of particular logic state of lead-in wire 107 outputs.Correspondingly, in the time that any one chip in the first chip 103 and the second chip 101,102 wishes to promote the operating voltage of its target device, this chip is high level signals to the digital signal of the particular logic state of lead-in wire 107 outputs.
Should also be understood that above-described is only the exemplary embodiment of power management module 108.Any circuit that can realize voltage-regulation or device known or exploitation in the future at present all can be combined with embodiments of the invention, and scope of the present invention is unrestricted in this regard.
With reference to figure 5, it shows the time sequential routine figure of the feed circuit of describing in conjunction with Fig. 2 above.As shown in the figure, the waveform of the line 501-503 digital signal that the chip 101,102 and 103 shown in presentation graphs 2 is exported to lead-in wire 107 respectively, line 504 represents the logic state of the digital signal on lead-in wire 107, and line 505 represents the output voltage waveforms of power management module 108.Be appreciated that in the circuit shown in Fig. 2, in the time adopting NMOS as the first terminal of chip, the signal logic on lead-in wire 107 is the logical “and” of each chip to the signals of lead-in wire application 107 application.
As shown in Figure 3, before moment T1, chip 101-103 all detects that the operating voltage of its corresponding target device is lower than threshold voltage, and therefore chip 101-103 is to lead-in wire 107 output logic low signals (line 501-503).Signal logic on lead-in wire 107 is dragged down (line 504).As response, the first chip (being chip 103 in this example) operation promotes its output voltage (line 505) to control power management module 108.
Next, at moment T1, chip 101 detects that the operating voltage of its target device has reached predetermined threshold, and therefore it stops to lead-in wire 107 output signals.In other words,, after moment T1, chip 101 and lead-in wire 107 are in electric blocking state (line 501).But because chip 102 and 103 is still to lead-in wire 107 output logic low signals (line 502 and 503), therefore the signal logic going between on 107 is still low (line 504), and continuations control power management module 108 is promoted output voltage (line 505) by the first chip.
At moment T2, the operating voltage of the target device being associated with chip 103 has also reached predetermined threshold subsequently, chip 103 thereupon with lead-in wire 107 resistance disconnected (line 503).Similarly, at moment T3, after the operating voltage of the target device of chip 102 is also higher than predetermined threshold voltage, chip 102 and lead-in wire 107 resistance disconnected (line 502).Now, all chips are not all to lead-in wire applied logic low signal, and the signal logic of lead-in wire 107 becomes height (line 504), thereby make the first chip power management module 108 of ceasing and desisting order promote output voltage (line 505).
Especially, as mentioned above, in certain embodiments, in the time that all chips are not all indicated lifting output voltage, power management module 108 can periodically reduce its output voltage (line 505).In the example depicted in fig. 3, the output voltage of voltage management module 108 drops under the required operating voltage of the target device of chip 102 at moment T4.In response to this, the signal logic (line 502 and 504) that chip 102 drags down lead-in wire 107 again since moment T4, promotes its output voltage (line 505) again so that the first chip 103 is controlled supercharging module 108.At moment T5 subsequently, the operating voltage of the target device of chip 102 returns to the proper level on threshold voltage.Correspondingly, chip 102 stops dragging down lead-in wire 107 (lines 502) again, and 107 the signal logic of making to go between becomes height (line 504).Thus, power management module 108 stops promoting output voltage (line 505) since moment T5.Follow-up sequential by that analogy.
Below with reference to Fig. 6, it shows the indicative flowchart of method of supplying power to according to an illustrative embodiment of the invention.
After method starts, at step S601, in the first chip, detect the logic state of the digital signal on the first terminal of described the first chip, the first terminal of wherein said the first chip is connected with a common lead, and described common lead operates to be also connected with the corresponding the first terminal of at least one the second chip.
Next, at step S602, the logic state based on described digital signal in described the first chip produces corresponding analog control signal, and exports described analog control signal through the second terminal of described the first chip.According to some embodiment, in response to described digital signal, in a particular logic state, described analog control signal is raised the output voltage of described power management module.Alternatively or additionally, in response to described digital signal, not in a particular logic state, described analog control signal is lowered the output voltage of described power management module.And according to some embodiment of the present invention, in response to described digital signal, not in a particular logic state, described analog control signal is regularly reduced the output voltage of described power management module.
Method proceeds to step S603 then, at this, in a power management module, receives described analog control signal, to the output voltage of described power management module is controlled accordingly.
Method finishes after step S603.Be appreciated that the feed circuit of the method for describing in conjunction with Fig. 6 based on describing in conjunction with Fig. 1-Fig. 5 and respective electronic equipment above and realize.Thus, each feature of above describing in conjunction with Fig. 1-Fig. 5 is equally applicable to the method for describing in conjunction with Fig. 6, does not repeat them here.
Some embodiments of the invention have above been described.Can see, utilize embodiments of the invention, multiple chips can be shared a power management module effectively.Each chip can send logical signal to public lead-in wire and regulate the output voltage of power management module, thereby realizes the adjusting to target device operating voltage.
Note, term is only not intended as restriction disclosure in order to describe specific embodiment as used herein.For example, unless context separately has and expresses, singulative "/one " and " being somebody's turn to do " are intended to also comprise plural form as used herein.Also " comprise " in the time being used in this instructions specifying and have the feature, whole, step, operation, unit of statement and/or parts and do not get rid of and exist or add one or more other features, whole, step, operation, unit, parts and/or its combination understanding word.
Although some embodiment of the present invention have been described with reference to the drawings above, should be appreciated that, the present invention is not limited to disclosed specific embodiment.The present invention is intended to contain interior included various modifications and the equivalent arrangements of spirit and scope of claims.The scope of claims meets the most wide in range explanation, thereby comprises all such modifications and equivalent structure and function.
Claims (20)
1. feed circuit, comprising:
The first chip, there is the first terminal, the second terminal and power managing signal circuit for generating, wherein said power managing signal circuit for generating operation is to produce corresponding analog control signal according to the logic state of the digital signal in the common lead being connected with described the first terminal, and export described analog control signal through described the second terminal
Wherein said common lead is connected with the first terminal of described the first chip, and operates being connected with the corresponding the first terminal of at least one the second chip, and wherein said the second chip has or do not have corresponding the second terminal; And
Power management module, has control terminal and power supply terminal, and operates to receive described analog control signal from described control terminal, and based on described analog control signal, the output voltage of described power supply terminal is controlled.
2. feed circuit according to claim 1, each in wherein said the first chip and described at least one second chip all operates with the digital signal producing a particular logic state described in hope power management module boosted output voltages in the situation that on the corresponding the first terminal at this chip; And
The operation of wherein said power managing signal circuit for generating and described power management module is with in response to the digital signal of described particular logic state, the output voltage of the described power supply terminal that raises detected in described common lead.
3. feed circuit according to claim 2, the corresponding the first terminal of each in wherein said the first chip and described at least one second chip comprises the source electrode of a N-type metal-oxide-semiconductor, and the digital signal of described particular logic state is a low level signal.
4. feed circuit according to claim 2, the corresponding the first terminal of each in wherein said the first chip and described at least one second chip comprises the drain electrode of a P type metal-oxide-semiconductor, and the digital signal of described particular logic state is a high level signal.
5. feed circuit according to claim 2, wherein said power managing signal circuit for generating and described power management module also operate the digital signal described particular logic state not detected in described common lead, reduce the output voltage of described power supply terminal.
6. feed circuit according to claim 2, wherein said power managing signal circuit for generating and described power management module also operate the digital signal described particular logic state not detected in described common lead, regularly reduce the output voltage of described power supply terminal.
7. according to the feed circuit described in any one in claim 1 to 6, wherein said power managing signal circuit for generating comprises a voltage digital analog converter.
8. according to the feed circuit described in any one in claim 1 to 6, wherein said power managing signal circuit for generating comprises a capacitive element.
9. according to the feed circuit described in any one in claim 1 to 6, it is one of following that wherein said power management module comprises: stepup transformer, reducing transformer and buck-boost device.
10. an electronic equipment, comprising:
Multiple chips, each described chip has the first terminal separately, and operates so that digital signal can be provided independently on the first terminal separately, and a selected chip in wherein said multiple chips also has the second terminal and power managing signal circuit for generating;
, a common lead, is connected with described multiple chips the first terminal separately; And
Power management module, there is power supply terminal and control terminal, described power supply terminal is connected to the target device being associated with described multiple chips, described control terminal is connected to described second terminal of described selected chip, and the described power managing signal circuit for generating of wherein said selected chip operates to control the output voltage of described power management module via described the second terminal according to the described digital signal in described common lead.
11. electronic equipments according to claim 10, wherein each described chip operation is not exported the digital signal of particular logic state to described common lead higher than predetermined threshold with the operating voltage in response to the target device being associated with this chip.
12. electronic equipments according to claim 10, wherein each described chip operation is exported the digital signal of particular logic state to described common lead lower than predetermined threshold with the operating voltage in response to the target device being associated with this chip.
13. electronic equipments according to claim 12, wherein said selected chip operation is with the digital signal in response to described particular logic state detected in described common lead, and via the described output voltage that raises of power management module described in described the second Terminal control.
14. electronic equipments according to claim 12, wherein said selected chip operation is with in response to the digital signal of described particular logic state do not detected in described common lead, and reduces described output voltage via power management module described in described the second Terminal control.
15. electronic equipments according to claim 12, wherein said selected chip operation is with in response to the digital signal of described particular logic state do not detected in described common lead, and regularly reduces described output voltage via power management module described in described the second Terminal control.
16. according to claim 12 to the electronic equipment described in any one in 15, and wherein said target device comprises multi-group light-emitting diode, and described in every group, light emitting diode is associated with in described multiple chips one.
17. 1 kinds of method of supplying power to, comprising:
In the first chip, detect the logic state of the digital signal on the first terminal of described the first chip, the first terminal of wherein said the first chip is connected with a common lead, and described common lead operates to be also connected with the corresponding the first terminal of at least one the second chip;
In described the first chip, based on the logic state of described digital signal, produce corresponding analog control signal, and export described analog control signal through the second terminal of described the first chip; And
In a power management module, receive described analog control signal, to the output voltage of described power management module is controlled accordingly.
18. according to the method for claim 17, wherein in response to described digital signal in a particular logic state, described analog control signal is raised the output voltage of described power management module.
19. according to the method for claim 17, wherein in response to described digital signal not in a particular logic state, described analog control signal is lowered the output voltage of described power management module.
20. according to the method for claim 17, wherein in response to described digital signal not in a particular logic state, described analog control signal is regularly reduced the output voltage of described power management module.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN113177386A (en) * | 2021-04-27 | 2021-07-27 | 北京百度网讯科技有限公司 | Integrated circuit and electronic device |
| CN114675698A (en) * | 2022-03-17 | 2022-06-28 | 北京芯格诺微电子有限公司 | Voltage regulation method of multi-load system based on single bus communication |
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| CN103853220B (en) | 2016-01-20 |
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Address after: 300457, room 2, building 19, No. 2701-2 West Ring Road, Tianjin economic and Technological Development Zone, Tianjin, Tanggu Patentee after: Dai Luo lattice integrated circuit (Tianjin) Co. Ltd. Address before: 300457, room 2, building 19, No. 2701-2 West Ring Road, Tianjin economic and Technological Development Zone, Tianjin, Tanggu Patentee before: Eyre watt integrated circuit technology (Tianjin) Co., Ltd. |