CN103839984A - InP/high kappa gate medium stack structure and preparation method thereof - Google Patents
InP/high kappa gate medium stack structure and preparation method thereof Download PDFInfo
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- CN103839984A CN103839984A CN201210485630.3A CN201210485630A CN103839984A CN 103839984 A CN103839984 A CN 103839984A CN 201210485630 A CN201210485630 A CN 201210485630A CN 103839984 A CN103839984 A CN 103839984A
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- inp
- gate medium
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- 238000002360 preparation method Methods 0.000 title claims abstract description 13
- 239000000758 substrate Substances 0.000 claims abstract description 21
- CMIHHWBVHJVIGI-UHFFFAOYSA-N gadolinium(III) oxide Inorganic materials [O-2].[O-2].[O-2].[Gd+3].[Gd+3] CMIHHWBVHJVIGI-UHFFFAOYSA-N 0.000 claims abstract description 16
- 229910001938 gadolinium oxide Inorganic materials 0.000 claims abstract description 13
- 229940075613 gadolinium oxide Drugs 0.000 claims abstract description 13
- 229910000449 hafnium oxide Inorganic materials 0.000 claims abstract description 13
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 claims abstract description 13
- 239000011224 oxide ceramic Substances 0.000 claims abstract description 13
- 229910052751 metal Inorganic materials 0.000 claims abstract description 12
- 239000002184 metal Substances 0.000 claims abstract description 12
- 239000010409 thin film Substances 0.000 claims abstract description 7
- 238000005240 physical vapour deposition Methods 0.000 claims abstract description 6
- 239000000428 dust Substances 0.000 claims abstract description 3
- 229910021645 metal ion Inorganic materials 0.000 claims abstract description 3
- 229910044991 metal oxide Inorganic materials 0.000 claims abstract description 3
- 239000010408 film Substances 0.000 claims description 16
- 238000000034 method Methods 0.000 claims description 11
- 238000000151 deposition Methods 0.000 claims description 5
- 230000008021 deposition Effects 0.000 claims description 5
- 238000005516 engineering process Methods 0.000 claims description 5
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical group [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 claims description 5
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims description 2
- 238000005229 chemical vapour deposition Methods 0.000 claims description 2
- 238000005137 deposition process Methods 0.000 claims description 2
- 229910052697 platinum Inorganic materials 0.000 claims description 2
- 238000005245 sintering Methods 0.000 claims description 2
- 239000007787 solid Substances 0.000 claims description 2
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 claims description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 2
- 229910052721 tungsten Inorganic materials 0.000 claims description 2
- 239000010937 tungsten Substances 0.000 claims description 2
- 239000004065 semiconductor Substances 0.000 abstract description 6
- 239000002957 persistent organic pollutant Substances 0.000 abstract 1
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 6
- 239000000463 material Substances 0.000 description 6
- 238000001755 magnetron sputter deposition Methods 0.000 description 5
- 238000004544 sputter deposition Methods 0.000 description 4
- 229910052786 argon Inorganic materials 0.000 description 3
- 239000003989 dielectric material Substances 0.000 description 3
- 239000007789 gas Substances 0.000 description 3
- 230000037230 mobility Effects 0.000 description 3
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 239000000919 ceramic Substances 0.000 description 2
- 238000004140 cleaning Methods 0.000 description 2
- 239000012528 membrane Substances 0.000 description 2
- 238000004377 microelectronic Methods 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 239000003595 mist Substances 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/51—Insulating materials associated therewith
- H01L29/517—Insulating materials associated therewith the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
Abstract
The invention provides an InP/high kappa gate medium stack structure and a preparation method thereof. The gate medium stack structure comprises an InP substrate, an amorphous HfO2-Gd2O3 thin film deposited on the InP substrate, and a metal gate electrode deposited through physical vapor deposition. The preparation method of the InP/high kappa gate medium stack structure comprises the following steps: (1) the InP substrate is cleaned to remove organic pollutant, dust, metal ions and oxide layers on the surface of the InP substrate; (2) the HfO2-Gd2O3 thin film is deposited on the InP substrate by adopting hafnium oxide and gadolinium oxide ceramic targets; (3) and the metal gate electrode is deposited on the HfO2-Gd2O3 thin film in the normal direction through physical vapor deposition to obtain the InP/ high kappa gate medium stack structure. The InP/high kappa gate medium stack structure of the invention has advantages of excellent electrical performances, high dielectric constant and low leakage current density. According to the invention, a basis is provided for the application of the group III-V semiconductor/high kappa gate stack structure in integrated circuits.
Description
Technical field
The present invention relates to the high κ gate medium of a kind of InP/ stack architecture and preparation method thereof, belong to microelectronics technology.
Background technology
Along with the fast development of microelectronics industry, the mos field effect transistor (MOSFET) based on Si has approached its physics limit.If further reduction of device size, can produce larger tunnelling current and cause device normally to work.For further boost device performance, adopt the new semi-conducting material with high mobility to replace traditional Si channel layer.III-V family semi-conducting material attracts wide attention as excellent properties such as the carrier mobilities of the Yin Qigao such as GaAs, InP, InGaAs.
In numerous III-V family semi-conducting materials, InP is a kind of compound semiconductor materials that is widely used in electronics, photoelectron and optics.Its energy gap is 1.34eV, and the fermi level pinning effect on surface is less than GaAs, and electron mobility is up to 5000cm
2v
-1s
-1.
Former in the report of InP base MOS structure, gate medium is mainly with Al
2o
3and SiO
2be main, these two dielectric constant is lower (being less than 10) all, limited further dwindling of MOSFET structure.If can deposit the gate dielectric material of a kind of high-k (high-κ) on InP, obtain having the InP base MOS structure of excellent electrology characteristic, in following IC circuit, InP will become a kind of very important channel material so.
Summary of the invention
The object of the present invention is to provide the high κ gate medium of the InP/ stack architecture that a kind of leakage current density is little, dielectric constant is high.
Another object of the present invention is to provide the preparation method of the high κ gate medium of a kind of described InP/ stack architecture.
For achieving the above object, the present invention takes following technical scheme:
The high κ gate medium of a kind of InP/ stack architecture, the amorphous HfO that this gate medium stack architecture comprises InP substrate, deposits on this InP substrate
2-Gd
2o
3film and the metal gate electrode that adopts physical vaporous deposition to deposit.Described metal gate electrode can be platinum (Pt), titanium nitride (TiN), tungsten (W) or tantalum nitride (TaN).
In the high κ gate medium of above-mentioned InP/ stack architecture, described amorphous HfO
2-Gd
2o
3the deposition process of film can be physical vapour deposition (PVD) or chemical vapour deposition technique.
In the high κ gate medium of above-mentioned InP/ stack architecture, described amorphous HfO
2-Gd
2o
3the thickness of film is 5～50nm.
In the high κ gate medium of above-mentioned InP/ stack architecture, described amorphous HfO
2-Gd
2o
3film is 14～30 as the dielectric constant of gate dielectric layer.
In the high κ gate medium of above-mentioned InP/ stack architecture, described amorphous HfO
2-Gd
2o
3when thin film physics thickness is 10nm, be under-1 volt in grid voltage, the leakage current density of the high κ gate medium of described InP/ stack architecture is less than or equal to 10
-4a/cm
2.
A preparation method for the high κ gate medium of above-mentioned InP/ stack architecture, the method comprises the steps:
(1) clean InP substrate, remove its surperficial organic pollution, micronic dust, metal ion and oxide layer;
(2) adopt hafnium oxide ceramic target and gadolinium oxide ceramic target to deposit HfO on InP substrate
2-Gd
2o
3film;
(3) adopt physical vaporous deposition to HfO
2-Gd
2o
3plated metal gate electrode on film, obtains the high κ gate medium of InP/ stack architecture.
In said method, the purity of described hafnium oxide, gadolinium oxide ceramic target is all greater than 99.9%.
In said method, the distance in described step (2) between InP substrate and hafnium oxide, gadolinium oxide ceramic target is respectively 20～50mm.
In said method, the hafnium oxide or the gadolinium oxide ceramic target that in described step (2), use can adopt solid sintering technology to make.
The present invention has the following advantages:
(1) gate medium HfO in the high κ gate medium of the InP/ in the present invention stack architecture
2-Gd
2o
3film is amorphous state, Stability Analysis of Structures.
(2) the high κ gate medium of the InP/ in the present invention stack architecture has less leakage current density and higher dielectric constant, HfO
2-Gd
2o
3it is under-1 volt in grid voltage that the dielectric constant of thin-film material is about this thin-film material that 14～30,10nm is thick, and its leakage current density is less than or equal to 10
-4a/cm
2.
(3) preparation method of the high κ gate medium of InP/ of the present invention stack architecture is simple, reproducible, and prepared ceramic membrane is applicable to high κ gate dielectric material and uses.
Accompanying drawing explanation
Fig. 1 is high frequency capacitance-voltage (C-V) curve chart of the high κ gate medium of the prepared InP/ of the embodiment of the present invention 1 storehouse MOS structure.
Fig. 2 is the curve chart of the leakage current characteristic (I-V) of the high κ gate medium of the prepared InP/ of the embodiment of the present invention 1 storehouse MOS structure.
Embodiment
The present invention will be further described by the following examples, but protection scope of the present invention is not subject to the restriction of these embodiment.
The preparation method of the high κ gate medium of InP/ stack architecture specifically comprises the following steps:
(1) adopting standard cleaning technique as shown in table 1 to clean resistivity is the monocrystalline InP substrate of 2～5 Ω cm, puts into magnetron sputtering apparatus, as the backing material of deposit film;
The concrete operations flow process of the standard cleaning technique of table 1 monocrystalline silicon substrate substrate
(2) in magnetron sputtering apparatus, put into hafnium oxide, the gadolinium oxide ceramic target that purity is greater than 99.9%, magnetron sputtering apparatus is evacuated to high vacuum 2 × 10
-4pa, be to pass into oxygen and argon gas mist at 5: 20 by the flow-rate ratio of oxygen and argon gas, air pressure is 2.5Pa, the sputtering power of hafnium oxide and gadolinium oxide is respectively 60W and 30W, by hafnium oxide (gadolinium oxide) ceramic target pre-sputtering 5min, hafnium oxide and gadolinium oxide ceramic target are carried out to magnetic control co-sputtering, and on monocrystalline InP substrate, deposition forms the amorphous HfO that thickness is 10nm
2-Gd
2o
3film;
(4) magnetron sputtering apparatus is evacuated to high vacuum 10
-4pa, passes into argon gas, and air pressure is 1.5Pa, and the sputtering power of W is 60W, is the metal mask template of 100 μ m by diameter, deposits the metal W round dot that 150nm is thick on above-mentioned noncrystal membrane, as metal gate electrode, thereby obtains the high κ gate medium of InP/ stack architecture.
Electrical property to the high κ gate medium of prepared InP/ stack architecture is measured, and adopts MOS structure to characterize, and at the back side of substrate monocrystal InP substrate, adopts r. f. magnetron sputtering technology, the metal Ni coating that deposit thickness is 100nm, and at the N of 350 ℃
2annealing in process 2min in atmosphere, as the back electrode of MOS structure.Adopt Keithley4200 semiconductor test system to test for this MOS structure capacitive and leakage current characteristic, as shown in the figure, Fig. 1 is high frequency capacitance-voltage (C-V) curve chart of MOS structure to result; Fig. 2 is the curve chart of the leakage current characteristic of MOS structure.The dielectric constant of deriving film from C-V curve is 16, meets the requirement (14～30) of high-K gate dielectric material to dielectric constant.In the time of-1V bias voltage, this MOS structure has less leakage current density, is only 10
-4a/cm
2.The present embodiment provides the high κ gate medium of InP/ that a kind of leakage current density is little, dielectric constant is high stack architecture, for the selection of following integrated circuit material provides a kind of possibility.
Claims (10)
1. the high κ gate medium of an InP/ stack architecture, is characterized in that: the amorphous HfO that this gate medium stack architecture comprises InP substrate, deposits on this InP substrate
2-Gd
2o
3the metal gate electrode of film and employing physical vapour deposition (PVD).
2. the high κ gate medium of amorphous according to claim 1 storehouse, is characterized in that: described metal gate electrode is platinum, titanium nitride, tungsten or tantalum nitride.
3. the high κ gate medium of InP/ according to claim 1 stack architecture, is characterized in that: described amorphous HfO
2-Gd
2o
3the deposition process of film is physical vaporous deposition or chemical vapour deposition technique.
4. the high κ gate medium of InP/ according to claim 1 stack architecture, is characterized in that: described amorphous HfO
2-Gd
2o
3the thickness of film is 5～50nm.
5. the high κ gate medium of InP/ according to claim 4 stack architecture, is characterized in that: described amorphous HfO
2-Gd
2o
3film is 14～30 as the dielectric constant of gate dielectric layer.
6. the high κ gate medium of InP/ according to claim 1 stack architecture, is characterized in that: described amorphous HfO
2-Gd
2o
3when thin film physics thickness is 10nm, be under-1 volt in grid voltage, the leakage current density of the high κ gate medium of described InP/ stack architecture is less than or equal to 10
-4a/cm
2.
7. a preparation method for the high κ gate medium of InP/ stack architecture described in claim 1, is characterized in that: the method comprises the steps:
(1) clean InP substrate, remove its surperficial organic pollution, micronic dust, metal ion and oxide layer;
(2) adopt hafnium oxide ceramic target and gadolinium oxide ceramic target to deposit HfO on InP substrate
2-Gd
2o
3film;
(3) adopt physical vaporous deposition to HfO
2-Gd
2o
3plated metal gate electrode on film, obtains the high κ gate medium of InP/ stack architecture.
8. preparation method according to claim 7, is characterized in that: the purity of described hafnium oxide, gadolinium oxide ceramic target is all greater than 99.9%.
9. preparation method according to claim 7, is characterized in that: the distance in described step (2) between InP substrate and hafnium oxide, gadolinium oxide ceramic target is respectively 20～50mm.
10. preparation method according to claim 7, is characterized in that: the hafnium oxide using in described step (2) or gadolinium oxide ceramic target adopt solid sintering technology to make.
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|---|---|---|---|
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| CN201210485630.3A CN103839984A (en) | 2012-11-26 | 2012-11-26 | InP/high kappa gate medium stack structure and preparation method thereof |
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102054858A (en) * | 2009-11-06 | 2011-05-11 | 北京有色金属研究总院 | Amorphous ternary high-K gate dielectric material and preparation method thereof |
| US20110193180A1 (en) * | 2010-02-05 | 2011-08-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method and apparatus of forming a gate |
| CN102187020A (en) * | 2009-04-20 | 2011-09-14 | 住友电气工业株式会社 | Indium phosphide substrate manufacturing method, epitaxial wafer manufacturing method, indium phosphide substrate, and epitaxial wafer |
| CN102592974A (en) * | 2012-03-20 | 2012-07-18 | 中国科学院上海微系统与信息技术研究所 | Preparation method for high-K medium film |
| CN102760657A (en) * | 2012-07-27 | 2012-10-31 | 中国科学院上海微系统与信息技术研究所 | Method for preparing high K grating medium film and MIS (Management Information System) capacitor on InP (Indium Phosphide) substrate |
-
2012
- 2012-11-26 CN CN201210485630.3A patent/CN103839984A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102187020A (en) * | 2009-04-20 | 2011-09-14 | 住友电气工业株式会社 | Indium phosphide substrate manufacturing method, epitaxial wafer manufacturing method, indium phosphide substrate, and epitaxial wafer |
| CN102054858A (en) * | 2009-11-06 | 2011-05-11 | 北京有色金属研究总院 | Amorphous ternary high-K gate dielectric material and preparation method thereof |
| US20110193180A1 (en) * | 2010-02-05 | 2011-08-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method and apparatus of forming a gate |
| CN102592974A (en) * | 2012-03-20 | 2012-07-18 | 中国科学院上海微系统与信息技术研究所 | Preparation method for high-K medium film |
| CN102760657A (en) * | 2012-07-27 | 2012-10-31 | 中国科学院上海微系统与信息技术研究所 | Method for preparing high K grating medium film and MIS (Management Information System) capacitor on InP (Indium Phosphide) substrate |
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