CN103839780A - Trenched power device and manufacturing method thereof - Google Patents
Trenched power device and manufacturing method thereof Download PDFInfo
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- CN103839780A CN103839780A CN201410098298.4A CN201410098298A CN103839780A CN 103839780 A CN103839780 A CN 103839780A CN 201410098298 A CN201410098298 A CN 201410098298A CN 103839780 A CN103839780 A CN 103839780A
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 28
- 239000004065 semiconductor Substances 0.000 claims abstract description 52
- 239000000758 substrate Substances 0.000 claims abstract description 49
- 238000000034 method Methods 0.000 claims abstract description 30
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 26
- 238000005530 etching Methods 0.000 claims abstract description 12
- 229910052751 metal Inorganic materials 0.000 claims description 25
- 239000002184 metal Substances 0.000 claims description 25
- 229920005591 polysilicon Polymers 0.000 claims description 21
- 238000002513 implantation Methods 0.000 claims description 10
- 238000005516 engineering process Methods 0.000 claims description 9
- 238000000151 deposition Methods 0.000 claims description 8
- 239000000463 material Substances 0.000 claims description 7
- 229910052710 silicon Inorganic materials 0.000 claims description 7
- 239000010703 silicon Substances 0.000 claims description 7
- 238000001465 metallisation Methods 0.000 claims description 6
- 239000004411 aluminium Substances 0.000 claims description 4
- 229910052782 aluminium Inorganic materials 0.000 claims description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 4
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical group [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 4
- 229910052721 tungsten Inorganic materials 0.000 claims description 4
- 239000010937 tungsten Substances 0.000 claims description 4
- 230000002093 peripheral effect Effects 0.000 claims description 3
- 239000011521 glass Substances 0.000 abstract description 15
- 238000010992 reflux Methods 0.000 abstract description 6
- 230000008021 deposition Effects 0.000 abstract description 5
- 238000002347 injection Methods 0.000 abstract 1
- 239000007924 injection Substances 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 47
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 6
- 238000002360 preparation method Methods 0.000 description 4
- 239000011229 interlayer Substances 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000005380 borophosphosilicate glass Substances 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000005524 hole trap Effects 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
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Abstract
The invention provides a trenched power device and a manufacturing method of the trenched power device. The manufacturing method comprises the steps that a semiconductor substrate with an active region and a terminal structure region is provided; a first trench is formed in the active region, and a second trench is formed in the terminal structure region; the grid electrode of the trenched power device is formed in the first trench, polycrystalline silicon is deposited on the side wall and the bottom, close to the active region, in the second trench at the same time, and the side, far away from the active region, of the polycrystalline silicon is of an arc shape; a dielectric layer is deposited on the semiconductor substrate, and the second trench is filled; a through hole is formed in the portion, on the active region, of the dielectric layer, ion injection is conducted twice, and a first doped region and a second doped region are formed in the portion, exposed due to the through hole, of the semiconductor substrate; the follow-up semiconductor process is conducted. By means of the trenched power device and the manufacturing method of the trenched power device, the situation that a through hole is formed in a terminal structure is avoided, as a result, the steps of deposition of boron-phosphorosilicate glass in the through hole, reflux and etching in the prior art are omitted, the complexity of the process is lowered, and the reproducibility of the trenched power device is improved.
Description
Technical field
The present invention relates to semiconductor technology and manufacture field, particularly a kind of groove power device and preparation method thereof.
Background technology
In order to dwindle the size of power device, improve the performance of power device, groove structure is introduced in power device, forms groove power device.Groove power device is the important component part of electronic circuit, and in the time of cut-off state, puncture voltage is high, leakage current is little; In the time of conducting state, conducting resistance is low, conduction pipe pressure drop is low; In the time of switch transition, switching speed is fast, and has the remarkable advantages such as on-state loss, off-state loss and switching loss be little, has become the main power device in the fields such as integrated circuit.
Groove power device has terminal structure, is enclosed in the active area of groove power device around, avoids puncturing in early days of groove power device marginal portion.
Fig. 1 is the structural representation of groove power device in prior art.As shown in Figure 1, the manufacture method of conventional groove power device comprises: the Semiconductor substrate 10 that includes source region 1 and terminal structure district 2 is provided; Form groove by exposure with being etched on the active area 1 of Semiconductor substrate 10; In described groove, form grid structure, grid structure comprises the gate oxide level 11 being formed on trenched side-wall and bottom and the grid polycrystalline silicon 12 of filling full groove; In Semiconductor substrate 10, deposit interlayer dielectric layer 13, form through hole by exposing and being etched on interlayer dielectric layer 13, described through hole includes the through hole in through hole and the terminal structure district 2 in source region 1; Then carry out Implantation for the first time taking interlayer dielectric layer 13 as mask, in the Semiconductor substrate exposing at active area through hole, form P trap, in the Semiconductor substrate exposing at terminal structure district through hole, form guard ring; Then in the through hole in active area through hole and terminal structure district, fill boron-phosphorosilicate glass 15(BPSG), reflux afterwards and carry out etching; Carry out Implantation for the second time and form N-shaped doped region in the P of active area through hole trap; Finally carry out deposition and the etching of tungsten, and the deposition of metallic aluminium and etching (not shown).
In the step of filling boron-phosphorosilicate glass 15 and reflux in active area through hole and terminal structure district through hole, only sidewall and bottom are covered by boron-phosphorosilicate glass to need active area through hole, terminal structure district through hole is sealed by boron-phosphorosilicate glass, reach above-mentioned requirement, need the strict thickness of controlling boron-phosphorosilicate glass, reflux temperature and time, the etching of boron-phosphorosilicate glass, technological parameters such as the different sizes of through hole and the design at through hole turning and reach the balance between each technological parameter, can increase thus the complexity of technique, and in terminal structure district through hole, the filling effect of boron-phosphorosilicate glass can impact follow-up Implantation, directly affect the voltage parameter of final groove power device.
Summary of the invention
The invention provides a kind of groove power device and preparation method thereof, fill to solve in the through hole of active area and terminal structure district in prior art the different-effect that boron-phosphorosilicate glass will reach, thereby increase the problem of the complexity of technique.
The manufacture method of groove power device provided by the invention, comprising:
Semi-conductive substrate is provided, and described Semiconductor substrate comprises active area and terminal structure district;
Form the first groove in the active area of described Semiconductor substrate, form the second groove in terminal structure district;
In described the first groove, form the grid of groove power device, sidewall and the bottom deposit spathic silicon of close described active area in described the second groove simultaneously, described polysilicon is curved in the side away from described active area;
Metallization medium layer in described Semiconductor substrate, described dielectric layer is filled described the second groove;
Form through hole by exposure with being etched on the dielectric layer of described active area, and carry out Implantation twice, in the Semiconductor substrate exposing at described through hole, form the first doped region, in described the first doped region, form the second doped region;
Carry out follow-up semiconductor technology, complete the making of described groove power device.
Further, described follow-up semiconductor technology comprises: the Semiconductor substrate that described through hole is exposed is carried out etching, and fills the first metal layer; On described dielectric layer, deposit the second metal level.
Further, in described the second groove, the dielectric layer of polysilicon top is curved.
Further, curved at described second metal level of described terminal structure area edge.
The thickness of the dielectric layer further, depositing in described the second groove is
Further, in described terminal structure, the second groove is 0um～3.7um near a side of active area to the outer peripheral distance of described the second metal level.
Further, offer groove power device voltage and be not less than 25V.
The first metal layer of further, filling in described through hole extends in described the first doped region.
Further, the material of described the first metal layer is tungsten, and the material of described the second metal level is aluminium.
Accordingly, the present invention also provides a kind of groove power device that uses the manufacture method of above-mentioned groove power device to make, and comprising:
Include the Semiconductor substrate in source region and terminal structure district;
In described active area, be formed with the first groove, described terminal structure is formed with the second groove in district;
In described the first groove, be formed with grid, sidewall and bottom near described active area in described the second groove are formed with polysilicon, and described polysilicon is curved in the side away from described active area;
In described Semiconductor substrate, be formed with dielectric layer, described dielectric layer is filled described the second groove;
On the dielectric layer of described active area, be formed with through hole, in the Semiconductor substrate that described through hole exposes, be formed with the first doped region and be arranged in the second doped region of the first doped region.
Compared with prior art, the present invention has the following advantages:
In the manufacture method of groove power device provided by the invention, by form the second groove in terminal structure district, sidewall and the bottom deposit spathic silicon of close active area in the second groove, polysilicon is set to arc in the one side away from active area, then in all the other position metallization medium layer of the second groove, avoid forming through hole in terminal structure, thereby in omission prior art, in through hole, deposit boron-phosphorosilicate glass, and reflux and the step of etching, reduce the complexity of technique, improved the reproducibility of groove power device.
Brief description of the drawings
Fig. 1 is the structural representation of groove power device in prior art.
Fig. 2 is the schematic flow sheet of the manufacture method of groove power device in one embodiment of the invention.
Fig. 3～9 are the structural representation of each step of the manufacture method of the groove power device in one embodiment of the invention.
Embodiment
Groove power device the present invention being proposed below in conjunction with the drawings and specific embodiments and preparation method thereof is described in further details.According to the following describes and claims, advantages and features of the invention will be clearer, it should be noted that, accompanying drawing all adopts very the form of simplifying and all uses non-ratio accurately, only for convenient, the object of the aid illustration embodiment of the present invention lucidly.
Fig. 2 is the schematic flow sheet of the manufacture method of groove power device in one embodiment of the invention, and as shown in Figure 2, the manufacture method of a kind of groove power device that the present invention proposes, comprises the following steps:
Step S01: semi-conductive substrate is provided, and described Semiconductor substrate comprises active area and terminal structure district;
Step S02: form the first groove in the active area of described Semiconductor substrate, form the second groove in terminal structure district;
Step S03: in described the first groove, form the grid of groove power device, sidewall and the bottom deposit spathic silicon of close described active area in described the second groove simultaneously, described polysilicon is curved in the side away from described active area;
Step S04: metallization medium layer in described Semiconductor substrate, described dielectric layer is filled described the second groove;
Step S05: form through hole by exposure with being etched on the dielectric layer of described active area, and carry out Implantation twice, form the first doped region in the Semiconductor substrate exposing at described through hole, form the second doped region in described the first doped region;
Step S06: carry out follow-up semiconductor technology, complete the making of described groove power device.
Fig. 3～9 are the structural representation of each step of the manufacture method of groove power device in one embodiment of the invention, please refer to shown in Fig. 2, and in conjunction with Fig. 3～Fig. 9, detailed description the present invention propose the manufacture method of groove power device:
In step S01, semi-conductive substrate 100 is provided, described Semiconductor substrate 100 includes source region 10 and terminal structure district 20, as shown in Figure 3.
Described Semiconductor substrate 100 can be silicon substrate, germanium silicon substrate or silicon-on-insulator (SOI) in the present embodiment, or well known to a person skilled in the art other Semiconductor substrate.
In step S02, form the first groove 101 in the active area 10 of described Semiconductor substrate 100, form the second groove 102 in terminal structure district 20, as shown in Figure 4.
In described Semiconductor substrate 100, apply photoresist layer, form the first groove 101 by exposure with being developed in the Semiconductor substrate of active area 10, in the Semiconductor substrate in terminal structure district 20, form the second groove 102.Described the first groove 101 is corresponding with the position of groove power device grid.
In step S03, in described the first groove 101, form the grid 103 of groove power device, sidewall and the bottom deposit spathic silicon 104 of close described active area 10 in described the second groove 102 simultaneously, described polysilicon 104 is curved in the side away from described active area 10, as shown in Figure 5.
Utilize thermal oxidation or depositing operation to form gate oxide in sidewall and the bottom of described the first groove 101, then utilize depositing operation at the full grid polycrystalline silicon of the interior filling of described the first groove 101, do not distinguish gate oxide and grid polycrystalline silicon to form in the grid 103(figure of described groove power device).In the present embodiment, fill polysilicon in described the first groove 101 in, in described the second groove 102, also fill polysilicon 104, described polysilicon 104 is filled sidewall and the bottom near described active area 10 in described the second groove 102, and its side away from described active area 10 is curved.
In step S04, metallization medium layer 105 in described Semiconductor substrate 100, described dielectric layer 105 is filled described the second groove 102, as shown in Figure 6.
In the present embodiment, described dielectric layer 105 can be silicon dioxide, phosphorosilicate glass layer or low K dielectric layer, or well known to a person skilled in the art other materials.Described dielectric layer 105 covers described Semiconductor substrate 100, and fills the place that there is no polysilicon 104 in described the second groove 102, and in described the second groove 102, the thickness of the dielectric layer 105 of deposition is
for example
due in step S03, the polysilicon 104 forming in described the second groove 102 is curved in the side away from active area, and the dielectric layer 105 of deposition is also curved thereon.
In step S05, form through hole 106 by exposure with being etched on the dielectric layer 105 of described active area 10, and carry out Implantation twice, in the Semiconductor substrate 100 exposing at described through hole 106, form the first doped region 107, in the first doped region 107 below described through hole 106, form the second doped region 108, as shown in Figure 7.
On described dielectric layer 105, apply photoresist layer, and by exposure and development, in the dielectric layer 105 of described active area 10, form through hole 106, then carry out twice Implantation, Implantation is P type ion for the first time, forms the first doped region 107 at described through hole 106 in the Semiconductor substrate 100 exposing; Implantation is N-type ion for the second time, in described the first doped region 107, forms the second doped region 108, finally anneals, and makes the ion injecting have activity.
The manufacture method of groove power device provided by the present invention, need in terminal structure district, not form through hole, thereby do not need to fill boron-phosphorosilicate glass after forming the first doped region, saved the processing step of boron-phosphorosilicate glass backflow with etching simultaneously, therefore reach boron-phosphorosilicate glass sealing through hole or the bottom of filling vias and the object of sidewall without the technological parameter such as temperature and time of adjusting hole size, backflow, compared with prior art, reduce the complexity of technique, and can improve the reproducibility of groove power device.
In step S06, carry out follow-up semiconductor technology, complete the making of described groove power device.Described follow-up semiconductor technology comprises:
The Semiconductor substrate 100 that described through hole 106 is exposed is carried out etching, and fills the first metal layer 109, as shown in Figure 8.Described etching is deep in the first doped region 107 described through hole 106 parts, guarantees that the contact hole of follow-up formation can contact with the first doped region 107 fully.Then deposit the contact hole that the first metal layer 109 filling vias 106 form described groove power device source region.
Then, on described dielectric layer 105, deposit the second metal level 110, as shown in Figure 9.Because the one side of the polysilicon 104 in the second groove is curved, the dielectric layer 105 forming is thereon also curved, and the edge of the second metal level 110 forming on described dielectric layer 105 is also curved.In the present embodiment, the material of described the first metal layer 109 is tungsten, and the material of described the second metal level 110 is metallic aluminium, in other embodiments, can be also other metals well known by persons skilled in the art.
In terminal structure district 20, the second groove is 0um～3.7um near a side of active area 10 to the outer peripheral distance of described the second metal level 110, for example: 0um, 0.4um, 0.8um, 1.2um, 1.7um, 2.2um, 2.7um, 3.2um, 3.7um, as shown in Figure 9 width W.The degree of depth T indicating in Fig. 9 is the thickness of the dielectric layer 105 that deposits in the second groove of describing in step S04.Simulate according to width W, degree of depth T and the voltage that offers groove power device, in the time that width W, degree of depth T meet above-mentioned range of condition, the voltage that offers groove power device is not less than 25V.
Accordingly, the present invention also provides a kind of groove power device that adopts the manufacture method of above-mentioned groove power device to make, and please refer to shown in Fig. 9, comprising:
Include the Semiconductor substrate 100 in source region 10 and terminal structure district 20;
In described active area 10, be formed with the first groove, in described terminal structure district 20, be formed with the second groove;
In described the first groove, be formed with grid 103, sidewall and bottom near described active area 10 in described the second groove are formed with polysilicon 104, and described polysilicon 104 is curved in the side away from described active area 10;
In described Semiconductor substrate 100, be formed with dielectric layer 105, described dielectric layer 105 is filled described the second groove;
On the dielectric layer 105 of described active area 10, be formed with through hole, in the Semiconductor substrate 100 that described through hole exposes, be formed with the first doped region 107 and be arranged in the second doped region 108 of the first doped region 107;
Described through hole extends in described the first doped region 107, is wherein filled with the first metal layer 109; On described dielectric layer 105, deposit the second metal level 110.
Described polysilicon 104 is curved in the side away from described active area 10, and the dielectric layer 105 forming is thereon also curved, and the edge of the second metal level 110 forming on described dielectric layer 105 is also curved.
In sum, in the manufacture method of groove power device provided by the invention, by form the second groove in terminal structure district, sidewall and the bottom deposit spathic silicon of close active area in the second groove, polysilicon is set to arc in the one side away from active area, then in all the other position metallization medium layer of the second groove, avoid forming through hole in terminal structure, thereby in omission prior art, in through hole, deposit boron-phosphorosilicate glass, and reflux and the step of etching, reduce the complexity of technique, improved the reproducibility of groove power device.
Foregoing description is only the description to preferred embodiment of the present invention, the not any restriction to the scope of the invention, and any change, modification that the those of ordinary skill in field of the present invention does according to above-mentioned disclosure, all belong to the protection range of claims.
Claims (10)
1. a manufacture method for groove power device, is characterized in that, comprising:
Semi-conductive substrate is provided, and described Semiconductor substrate comprises active area and terminal structure district;
Form the first groove in the active area of described Semiconductor substrate, form the second groove in terminal structure district;
In described the first groove, form the grid of groove power device, sidewall and the bottom deposit spathic silicon of close described active area in described the second groove simultaneously, described polysilicon is curved in the side away from described active area;
Metallization medium layer in described Semiconductor substrate, described dielectric layer is filled described the second groove;
Form through hole by exposure with being etched on the dielectric layer of described active area, and carry out Implantation twice, in the Semiconductor substrate exposing at described through hole, form the first doped region, in described the first doped region, form the second doped region;
Carry out follow-up semiconductor technology, complete the making of described groove power device.
2. the manufacture method of groove power device as claimed in claim 1, is characterized in that, described follow-up semiconductor technology comprises:
The Semiconductor substrate that described through hole is exposed is carried out etching, and fills the first metal layer;
On described dielectric layer, deposit the second metal level.
3. the manufacture method of groove power device as claimed in claim 2, is characterized in that, in described the second groove, the dielectric layer of polysilicon top is curved.
4. the manufacture method of groove power device as claimed in claim 3, is characterized in that, curved at described second metal level of described terminal structure area edge.
5. the manufacture method of groove power device as claimed in claim 1, is characterized in that, the thickness of the dielectric layer depositing in described the second groove is
6. the manufacture method of groove power device as claimed in claim 5, is characterized in that, in described terminal structure, the second groove is 0um～3.7um near a side of active area to the outer peripheral distance of described the second metal level.
7. the manufacture method of groove power device as claimed in claim 6, is characterized in that, the voltage that offers groove power device is not less than 25V.
8. the manufacture method of groove power device as claimed in claim 2, is characterized in that, the first metal layer of filling in described through hole extends in described the first doped region.
9. the manufacture method of groove power device as claimed in claim 8, is characterized in that, the material of described the first metal layer is tungsten, and the material of described the second metal level is aluminium.
10. right to use requires the groove power device that the manufacture method of the groove power device described in 1～9 is made, and it is characterized in that, comprising:
Include the Semiconductor substrate in source region and terminal structure district;
In described active area, be formed with the first groove, described terminal structure is formed with the second groove in district;
In described the first groove, be formed with grid, sidewall and bottom near described active area in described the second groove are formed with polysilicon, and described polysilicon is curved in the side away from described active area;
In described Semiconductor substrate, be formed with dielectric layer, described dielectric layer is filled described the second groove;
On the dielectric layer of described active area, be formed with through hole, in the Semiconductor substrate that described through hole exposes, be formed with the first doped region and be arranged in the second doped region of the first doped region.
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| CN201410098298.4A CN103839780B (en) | 2014-03-17 | 2014-03-17 | Groove power device and preparation method thereof |
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| CN201410098298.4A CN103839780B (en) | 2014-03-17 | 2014-03-17 | Groove power device and preparation method thereof |
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| US20100187605A1 (en) * | 2009-01-27 | 2010-07-29 | Infineon Technologies Austria Ag | Monolithic semiconductor switches and method for manufacturing |
| CN103441149A (en) * | 2013-08-29 | 2013-12-11 | 上海宏力半导体制造有限公司 | Groove power device and manufacturing method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN1348203A (en) * | 2000-09-22 | 2002-05-08 | 通用半导体公司 | Method for forming channel metal-oxide-semiconductor and terminal structure |
| US20100187605A1 (en) * | 2009-01-27 | 2010-07-29 | Infineon Technologies Austria Ag | Monolithic semiconductor switches and method for manufacturing |
| CN103441149A (en) * | 2013-08-29 | 2013-12-11 | 上海宏力半导体制造有限公司 | Groove power device and manufacturing method thereof |
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