CN103823707A - Hyper-threading based rebalancing method for equipment to process business - Google Patents
Hyper-threading based rebalancing method for equipment to process business Download PDFInfo
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- CN103823707A CN103823707A CN201410053329.4A CN201410053329A CN103823707A CN 103823707 A CN103823707 A CN 103823707A CN 201410053329 A CN201410053329 A CN 201410053329A CN 103823707 A CN103823707 A CN 103823707A
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Abstract
The invention relates to a hyper-threading based rebalancing method for equipment to process business. The hyper-threading based rebalancing method includes the steps of S1, performing multiple virtualization on a first CPU (central processing unit) of a chip by means of hyper threading to acquire multiple feature CPUs, S2, performing virtual encapsulation on the multiple feature CPUs, S3, using a fist feature CPU group as a protocol control CPU and using a second feature CPU group as a dataplan CPU after encapsulation. To the equipment with only one CPU on a hard disk, the one CPU is virtualized into two CPUs by means of hyper threading; to software needing multiple CPUs, the CPUs on the control plane and the dataplan plane are virtualized by means of threading and are distinguished by threading; therefore, integral equipment cost is reduced, requirements for cost of low-end equipment are met, and data forwarding and processing performance of signal-core CPUs is improved.
Description
Technical field
The present invention relates to field of computer technology, relate in particular to a kind of balance method again of hyperthread device processes business.
Background technology
Its English of hyperthread is HT technology, full HYPER THREADING by name, Hyper-Threading major function is the processor that a concurrent physical processor is fictionalized to two balance equivalences by hyperthread, now can on software forms, regard monokaryon equipment as multinuclear equipment processes, pass through Hyper-Threading, the processor device that has n core can be regarded as to 2n core and process, the results of property demonstration testing out by Intel, its overall operation efficiency has improved 15% to 30%.
In prior art, mostly adopt following two kinds of modes: one is the rmi chip that use itself just has and simplifies, even the feature of this chip is application polycaryon processor, price is also very cheap, and it is designed that this processor is multi-core network device from initial research and development, so application network software can reduce equipment cost greatly, but be mainly used in low-end market, do not there is very strong applicability, and treatment effeciency is low and length consuming time; Its two intel chip for use multinuclear x86 framework, the feature of this chip is that performance is high, can meet the multinuclear software needs of high-end forwarding unit, but shortcoming is that price is high, is not suitable for towards low-end market.
Further, for two kinds of selections of above prior art, select rmi chip, very minority, and this chip is dedicated network chip, very fast to the forward process of network message, performance is high, but for current next generation network equipment, the processing of network message is not limited to simple message repeating function, has started a large amount of uses for the processing of applied business, now extremely important to the network multi-dimensional complicated computing of processor, so concerning the rmi chip designing for forwarded specially, just seem and do not use very much; And the processor of x86, monomer framework cost is very high, along with the growth of check figure, cost also exponentially level increases, and for low side devices, does not need very high performance, so use x86 chip to there will be the high problem of cost in low side devices, there is no the market competitiveness.
Summary of the invention
Technical matters to be solved by this invention is how to overcome existing single core processor to process the poor efficiency of business, consuming time, and the high problem of cost.
For this purpose, the present invention proposes a kind of balance method again of hyperthread device processes business, comprise concrete following steps:
S1: the first processor of chip is carried out to multiple by hyperthread virtual, obtain multiple characteristic processing devices;
S2: the described multiple characteristic processing devices that obtain are carried out to virtual enclosures;
S3: the First Characteristic processor group after described encapsulation is as the protocol host processing of message, described Second Characteristic processor group is as the forward process of message, and wherein said multiple characteristic processing devices comprise described First Characteristic processor group and described Second Characteristic processor group.
Particularly, described first processor is concurrent physical processor.
Particularly, described multiple characteristic processing device is virtual logical processor.
Particularly, described First Characteristic processor group and described Second Characteristic processor group are virtual logical processor.
Further, by described multiple characteristic processing device software, described multiple characteristic processing devices are operated.
Particularly, by corresponding software by virtual described First Characteristic processor group be key-course.
Particularly, by corresponding software by virtual described Second Characteristic processor group for forward layer.
By adopting the balance method again of the disclosed a kind of hyperthread device processes business of the present invention, the present invention is by the equipment for only having a processor on hardware, fictionalize two processors by hyperthread, need the software of multiple processors from software view, multiple processors of control plane are undertaken virtual by process, distinguish by thread, multiple processors of forwarding plane are undertaken virtual by process, also distinguish by thread, now just form a processor and fictionalized two processors, on software, a virtual processor is as key-course, one as forwarding layer, play in this way and reduced overall equipment cost, meet the object of the cost demand of low side devices.
Accompanying drawing explanation
Can more clearly understand the features and advantages of the present invention by reference to accompanying drawing, accompanying drawing is schematically to should not be construed as the present invention is carried out to any restriction, in the accompanying drawings:
Fig. 1 shows the flow chart of steps of the balance method again of a kind of hyperthread device processes business in the embodiment of the present invention.
Embodiment
Below in conjunction with accompanying drawing, embodiments of the present invention is described in detail.
As shown in Figure 1, the invention provides a kind of balance method again of hyperthread device processes business, comprise concrete following steps:
Step S1: the first processor of chip is carried out to multiple by hyperthread virtual, obtain multiple characteristic processing devices.Wherein, first processor is concurrent physical processor, and multiple characteristic processing device is virtual logical processor.
Step S2: the multiple characteristic processing devices that obtain are carried out to virtual enclosures.
Step S3: the First Characteristic processor group after encapsulation is as the protocol host processing of message, and Second Characteristic processor group is as the forward process of message.Wherein, multiple characteristic processing devices comprise First Characteristic processor group and Second Characteristic processor group, and First Characteristic processor group and Second Characteristic processor group are virtual logical processor.
Further, by multiple characteristic processing device software, multiple characteristic processing devices are operated.Particularly, by corresponding software by virtual First Characteristic processor group be key-course; By corresponding software by virtual Second Characteristic processor group for forward layer.
For the ease of understanding the balance method again of a kind of hyperthread device processes business proposing with application the present invention, carry out following example.
Use the concurrent physical processor of x86 chip simultaneously, in conjunction with Hyper-Threading, concurrent physical processor is carried out to multiple virtual, the development kit that application software is used Hyper-Threading to provide, the entity of concurrent physical processor is carried out to virtual enclosures, now concerning upper layer software (applications), what see is exactly the polycaryon processor after virtual.
Further, for forwarding application software, at least need 4 above processors, wherein 4 processors that fictionalize are so as the protocol host processing of message, other processors that fictionalize are as the forward process of message, now protocol host processor is known as control cpu, message repeating processor is known as dataplan cpu, control cpu is made up of multiple processors, the effect difference of each processor, be divided into timer cpu, it is time processor, manager cpu, it is management processor, remaining processor is dataplan cpu, it is message repeating processor, the orientation that completes message forwards.
Further, for the software after optimization can be moved on monokaryon equipment, need to carry out hyperthread to 2 virtual processor to single processor, 2 processors of the control part of software are invented to one to carry out, become virtual multiple thread as many control cpu at this, another virtual processor is directly as dataplan cpu.
Further, the hyperthread that the present invention proposes is for the network equipment, normally the multiprocessor machine of the network equipment is carried out to functional processor division, be decomposed into multi-service processor, that is to say, for example: minimum needs 8 nuclear equipments of equipment of certain company are processed a whole set of Network forwarding process, if now the processor cores of x86 framework only has 4, so just can not complete the network equipment forwarding process of certain company, by buying 8 nuclear equipments, for the low side network equipment, cost increases again greatly, if so now combined with Hyper-Threading, so only need to use 4 core processors, just can realize the demand that certain company's network equipment is greater than 4 to processor number.
The network processes of simplifying when use is again when balance method, more can greatly dwindle the use number to processor, but for the network processes software of part company multicore architecture, need at least 2 processors to complete, if so now only use the equipment of a processor, add Hyper-Threading, can realize part company software and manage herein the normal operation on device equipment, this propose with Hyper-Threading add the network operation again balance method reduce the operation implementation method to processor monomer physics number.
By adopting the balance method again of the disclosed a kind of hyperthread device processes business of the present invention, the present invention is by the equipment for only having a processor on hardware, fictionalize two processors by hyperthread, need the software of multiple processors from software view, multiple processors of control plane are undertaken virtual by process, distinguish by thread, multiple processors of forwarding plane are undertaken virtual by process, also distinguish by thread, now just form a processor and fictionalized two processors, on software, a virtual processor is as key-course, one as forwarding layer, play in this way and reduced overall equipment cost, meet the object of the cost demand of low side devices.
Although described by reference to the accompanying drawings embodiments of the present invention, but those skilled in the art can make various modifications and variations without departing from the spirit and scope of the present invention, such modification and modification all fall into by within claims limited range.
Claims (7)
1. a balance method again for hyperthread device processes business, is characterized in that, comprises concrete following steps:
S1: the first processor of chip is carried out to multiple by hyperthread virtual, obtain multiple characteristic processing devices;
S2: the described multiple characteristic processing devices that obtain are carried out to virtual enclosures;
S3: the First Characteristic processor group after described encapsulation is as the protocol host processing of message, described Second Characteristic processor group is as the forward process of message, and wherein said multiple characteristic processing devices comprise described First Characteristic processor group and described Second Characteristic processor group.
2. the method for claim 1, is characterized in that, described first processor is concurrent physical processor.
3. the method for claim 1, is characterized in that, described multiple characteristic processing devices are virtual logical processor.
4. the method for claim 1, is characterized in that, described First Characteristic processor group and described Second Characteristic processor group are virtual logical processor.
5. the method for claim 1, is characterized in that, by described multiple characteristic processing device software, described multiple characteristic processing devices is operated.
6. method as claimed in claim 5, is characterized in that, by corresponding software by virtual described First Characteristic processor group be key-course.
7. method as claimed in claim 5, is characterized in that, by corresponding software by virtual described Second Characteristic processor group for forward layer.
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| CN201410053329.4A CN103823707A (en) | 2014-02-17 | 2014-02-17 | Hyper-threading based rebalancing method for equipment to process business |
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| CN201410053329.4A CN103823707A (en) | 2014-02-17 | 2014-02-17 | Hyper-threading based rebalancing method for equipment to process business |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105094947A (en) * | 2015-07-28 | 2015-11-25 | 中国联合网络通信集团有限公司 | Method and system for quotas management of virtual computing resource |
| CN106293981A (en) * | 2016-07-29 | 2017-01-04 | 浪潮电子信息产业股份有限公司 | Detection method for server CPU hyper-threading technology |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1926510A (en) * | 2004-03-31 | 2007-03-07 | 英特尔公司 | Event processing mechanism |
| CN101369224A (en) * | 2007-08-14 | 2009-02-18 | 英特尔公司 | Providing quality of service via thread priority in a hyper-threaded microprocessor |
| US20110191559A1 (en) * | 2010-01-29 | 2011-08-04 | International Business Machines Corporation | System, method and computer program product for data processing and system deployment in a virtual environment |
-
2014
- 2014-02-17 CN CN201410053329.4A patent/CN103823707A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1926510A (en) * | 2004-03-31 | 2007-03-07 | 英特尔公司 | Event processing mechanism |
| CN101369224A (en) * | 2007-08-14 | 2009-02-18 | 英特尔公司 | Providing quality of service via thread priority in a hyper-threaded microprocessor |
| US20110191559A1 (en) * | 2010-01-29 | 2011-08-04 | International Business Machines Corporation | System, method and computer program product for data processing and system deployment in a virtual environment |
Non-Patent Citations (1)
| Title |
|---|
| 刘近光 等: "多核多线程处理器的发展及其软件系统架构", 《微处理机》 * |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105094947A (en) * | 2015-07-28 | 2015-11-25 | 中国联合网络通信集团有限公司 | Method and system for quotas management of virtual computing resource |
| CN105094947B (en) * | 2015-07-28 | 2018-06-12 | 中国联合网络通信集团有限公司 | The quota management method and system of a kind of virtual computing resource |
| CN106293981A (en) * | 2016-07-29 | 2017-01-04 | 浪潮电子信息产业股份有限公司 | Detection method for server CPU hyper-threading technology |
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