CN103823399B - Method for solving incompatibility between VOIP (Voice Over Internet Protocol) and CS CALL (Counter-Strike Call) by using FPGA (Field Programmable Gate Array) - Google Patents

Abstract

The invention relates to the application field of the FPGA (Field Programmable Gate Array) and in particular relates to a method for solving incompatibility between VOIP (Voice Over Internet Protocol) and CS CALL (Counter-Strike Call) by using FPGA, so that a mobile CPE (Central Processing Element) product can support VOIP and CS CALL simultaneously. A circuit module is selected and synchronized in a chip due to the adoption of modular design idea of the FPGA, so that a system is simple, easy to implement and strong in reliability; meanwhile, the user does not need to carry out chip production; an applicable chip can be obtained within the shortest design cycle at lowest development cost with the minimum risk; a special chip can be directly produced under the condition that the system is stable, thus reducing the cost.

Description

A kind of utilization FPGA solves the method that VOIP and CS CALL can not be compatible

Technical field

The present invention relates to FPGA application, more particularly, to one kind can not be compatible using FPGA solution VOIP and CS CALL Method.

Background technology

FPGA, i.e. field programmable gate array, it is further on the basis of the programming devices such as PAL, GAL, CPLD The product of development.It is as special IC（ASIC）One of field semi-custom circuit and occur, both solved The deficiency of custom circuit, overcomes the limited shortcoming of original programming device gate circuit number again.

It is directed to traditional mobile gateway CPE product at present on the market, voice scheme has two kinds：One kind is VOIP（Note 1） Scheme, is exactly by analogue signal in brief（Voice）Digitized, with data packet（Data Packet）Form in IP network Network (IP Network）On do real-time transmission；One kind is CS CALL（Note 2）Scheme, walks traditional circuit hosting domain and mobile phone Make a phone call the same.Wherein, VOIP scheme is that to process that voice packet walks by DSP is data field（PS）, CS CALL is by 3G What module process voice packet was walked is circuit hosting domain（CS）.

The abbreviation Voice over Internet Protocol of described VOIP is it is simply that by analogue signal（Voice）Numeral Change, with data packet（Data Packet）Form in IP network (IP Network）On do real-time transmission.Described CS CALL Abbreviation Circuit Switch Call, be that a kind of circuit switched type connects, distribute private network resource in connection establishment, Discharge private resource in Connection Release, the voice that we commonly use is exactly this service.

Under 3G, access network is simultaneously connected with CS and PS, and that is, core net is divided into CS and PS, signal of generally making a phone call Walk CS, data service signal walks PS, different data services is to compete bandwidth on the basis of in real time.That is, in net When network condition difference, the voice of VoIP product walks that ps domain time delay is larger, and voice quality also can not walk CS domain with CS CALL Quality is compared.

In view of background above, if by two kinds of voice modes and can exist in same end product, can be mutual with advantage Mend, network condition difference in the case of using CS CALL, network condition good in the case of using VOIP.And current mobile network Close product very difficult that both are simultaneously compatible.It is primarily present two big obstacles：

Obstacle one：The pcm bus of VOIP and CS CALL transmission are all independent, speech chip as from chip, during work Clock will rely on PCLK, be unable to this two PCM transfer bus are used it is necessary to select one of them as voice circulation simultaneously Road.

Obstacle two：Although traditional switched circuit can select pcm bus, also bring along the step-out of signal simultaneously, do not have Method ensures the reliability of signal, and this has also resulted in the incompatible of CS CALL and VOIP.

Content of the invention

It is an object of the invention to provide a kind of utilization FPGA solves the method that VOIP and CS CALL can not be compatible, solve Current CS CALL and VOIP incompatible, lead to when network condition difference, the voice of VoIP product walks ps domain time delay relatively Greatly, the problem compared with quality that voice quality cannot walk CS domain with CS CALL.

For solving the above problems, the technical solution used in the present invention is：

A kind of utilization FPGA solves the method that VOIP and CS CALL can not be compatible, including the design of FPGA general control system, choosing Select circuit module design and synchronous circuit module designs three parts；

Described FPGA general control system design comprises the following steps：

Step one, is wrapped respectively using PCM1 tetra- EBI that selection circuit realized in VHDL voice in FPGA general control system Dock with OUN, IN, CLK, FS of VOIP pcm bus containing IN, OUT, CLK, FS；

Step 2, is wrapped respectively using PCM2 tetra- EBI that selection circuit realized in VHDL voice in FPGA general control system Dock with OUN, IN, CLK, FS of CS CALL pcm bus containing IN, OUT, CLK, FS；

Step 3, comprises selection circuit module inside FPGA general control system, can be passed through according to the instruction of client layer The low and high level change of GPIO1 and GPIO2, completes the selection of PCM voice flow between VOIP and CS CALL；

Step 4, FPGA general control system comprise synchronous circuit module it is ensured that PCM voice flow select after signal same Step.

Described selection circuit module design comprises the following steps：

Step one, selection circuit module realizes PCM1 and PCM2 two to bus, is responsible for and the docking of DSP1 and DSP2；

Step 2, selection circuit module receives the instruction of FPGA general control system, control selections circuit according to network environment Determine select any road PCM voice flow, by corresponding PCM tetra- signal line signal receive send, do not have selected then Blocking processing；

Step 3, selection circuit module sends the PCM voice flow of selection to synchronous circuit and carries out subsequent treatment.

Described synchronous circuit module design comprises the following steps：

Step one, synchronous circuit module receives the PCM voice flow of selection circuit transmission, is sent at synchronous circuit core Reason area；

Step 2, synchronous circuit module pass through synchronization process mechanism, especially by phaselocked loop carry out signal synchronization it is ensured that PCM voice flow is out-of-step free；

Step 3, synchronous circuit module sends the PCM voice flow after synchronization to SLIC chip, realizes call.

For making the present invention play superior technique effect：

Using FPGA programmable features it is achieved that FPGA general control system, wherein mainly comprise selection circuit and synchronization The big module of circuit two, has been respectively completed the real-time selection of PCM voice flow and the synchronization of PCM signal it is ensured that the biography of voice signal Defeated.

Have the beneficial effects that using produced by technique scheme：The present invention modular design method of FPGA, Selection circuit module and synchronous circuit module is realized so that simple system is easily realized in chip, highly reliable.User is not required to simultaneously Throw piece to produce, the design cycle is the shortest, development cost are minimum, least risk, just can obtain the chip sharing, in system stability In the case of can be directly produced special chip and carry out reduces cost.

Brief description

Fig. 1 is the knot that a kind of present invention utilization FPGA solves one embodiment of method that VOIP and CS CALL can not be compatible Structure schematic diagram, comprises the structured flowchart of whole FPGA general control system.

Fig. 2 is the schematic diagram that FPGA general control system is controlled to selection circuit according to upper strata instruction.

Fig. 3 is the fundamental block diagram of selection circuit, is that present invention one kind can not be compatible using FPGA solution VOIP and CS CALL Method in DSP1, DSP2 annexation figure with FPGA general control system respectively.

Specific embodiment

In order that the objects, technical solutions and advantages of the present invention become more apparent, below in conjunction with drawings and Examples, right The present invention is further elaborated.It should be appreciated that specific embodiment described herein is only in order to explain the present invention, not For limiting the present invention.

Fig. 1 shows that a kind of present invention utilization FPGA solves an enforcement of the method that VOIP and CS CALL can not be compatible Example：A kind of utilization FPGA solves the method that VOIP and CS CALL can not be compatible, including the design of FPGA general control system, selects electricity Road module design and synchronous circuit module design three parts；

Described FPGA general control system design comprises the following steps：

Step one, as shown in figure 3, realize PCM1 tetra- bus of selection circuit using VHDL voice in FPGA general control system Interface comprises IN, OUT, CLK, FS and VOIP respectively（DSP1）OUN, IN, CLK, FS docking of pcm bus；

Step 2, as shown in figure 3, realize PCM2 tetra- bus of selection circuit using VHDL voice in FPGA general control system Interface comprises IN, OUT, CLK, FS and CS CALL respectively（DSP2）OUN, IN, CLK, FS docking of pcm bus；

Step 3, such as Fig. 2 shows, comprises selection circuit module inside FPGA general control system, understands the instruction according to client layer, By the low and high level change of GPIO1 and GPIO2, complete the selection of PCM voice flow between VOIP and CS CALL；

Step 4, FPGA general control system comprise synchronous circuit module it is ensured that PCM voice flow select after signal same Step.

Described selection circuit module design comprises the following steps：

Step one, such as Fig. 2 shows, selection circuit module realizes PCM1 and PCM2 two to bus, is responsible for DSP1's and DSP2 Docking；

Step 2, selection circuit module receives the instruction of FPGA general control system, control selections circuit according to network environment Determine select any road PCM voice flow, by corresponding PCM tetra- signal line signal receive send, do not have selected then Blocking processing；

Step 3, selection circuit module sends the PCM voice flow of selection to synchronous circuit and carries out subsequent treatment.

Described synchronous circuit module design comprises the following steps：

Step one, synchronous circuit module receives the PCM voice flow of selection circuit transmission, is sent at synchronous circuit core Reason area；

Step 2, synchronous circuit module pass through synchronization process mechanism, especially by phaselocked loop carry out signal synchronization it is ensured that PCM voice flow is out-of-step free；

Step 3, synchronous circuit module sends the PCM voice flow after synchronization to SLIC chip, realizes call.

FPGA general control system can receive the instruction of upper strata transmission according to the use scene of user according to real needs, Then carry out judgement process, retransmit instruction and carry out implementing control to selection circuit and synchronous circuit.

Wherein, selection circuit module mainly realizes VOIP（DSP1）With CS CALL（DSP2）Between PCM select, according to The scene demand of upper layer software (applications), if the place covering in 3G signal, needs using VOIP, just the PCM of DSP1 is transmitted To PCM1, conversely, needing, using CS CALL, just the PCM of DSP2 to be transferred to PCM2.Synchronous circuit module, main realization The synchronization of the upper transmission signal of PCM, the transmission due to signal there may be time delay, leads to the step-out of signal, and synchronous circuit ensure that The reliability of signal transmission.Other ingredients, including SPI control circuit, the USB hub communication electricity of CPU and 3G Module Road.SPI control circuit is responsible for controlling the initialization of SLIC and the detection of working condition, and USB hub is responsible for CPU and 3G The communication of Module, 3G Module loads as an equipment of system.

Selection circuit such as Fig. 2 shows and mainly achieves VOIP（DSP1）With CS CALL（DSP2）Between selection.Using FPGA Programmable features, be designed using VHDL language it is easy to realize the switching between PCM.Compared with traditional exchange chip, Performance is more stable.It should be noted that PCM-OUT and PCM-IN in PCM, different, the traditional method migration of transmission direction Do not enable, the Programmable Design using FPGA can solve easily.

Because digital signal is when digital circuit device inside passes through line and logical block, there is certain time delay.Prolong When size relevant with the length of line and the number of logical block, be also subject to the manufacturing process of device, running voltage, temperature simultaneously Impact etc. condition.The low and high level conversion of signal is also required to certain transit time.Exactly there is these two aspects factor, multichannel When the level value of signal changes, in the moment of signal intensity, the output of combination logic has sequencing, is not same time-varying Change, the step-out of signal may be led to.Using the synchronous circuit of FPGA can ensure that voice signal synchronization it is ensured that transmission reliability Property.

The compatible VOIP and CS CALL of the system can meet the different demands of user, compensate in terminating gateway product A kind of technological deficiency of mode can only be selected；

This control system based on FPGA, using modular design method, simple system is easily realized, highly reliable；

Selection circuit module is responsible for VOIP（DSP1）With CS CALL（DSP2）Selection, can be in real time according to scene, upper strata is soft The requirement of part switches over, real-time.Compared with traditional exchange chip, cost performance is higher, and stability is higher；

Synchronous circuit module can avoid the step-out of signal it can be ensured that the reliability of signal is so that the capacity of resisting disturbance of system By force, stability is strong；

FPGA adopts high-speed cmos technique, and integrated level is high, can substitute up to thousand of pieces of general purpose I C chips, greatly reduces electricity The area on road, reduce power consumption, improve reliability, several functions are realized in a chip, reduce totle drilling cost, complexity and Power consumption, simultaneously can be compatible with CMOS, Transistor-Transistor Logic level；

Using FPGA design ASIC circuit, user does not need to throw piece production, and the design cycle is the shortest, development cost are minimum, wind Danger is minimum, just can obtain the chip sharing, can be directly produced special chip and carry out reduces cost in the case of system stability.

Claims (1)

1. a kind of utilization FPGA solve method that VOIP and CS CALL can not be compatible it is characterised in that：Including FPGA master control system System design, the design of selection circuit module and synchronous circuit module design three parts；

Described FPGA general control system design comprises the following steps：

Step one, is comprised respectively using PCM1 tetra- EBI that selection circuit realized in VHDL voice in FPGA general control system IN, OUT, CLK, FS are docked with OUT, IN, CLK, FS of VOIP pcm bus；

Step 2, is comprised respectively using PCM2 tetra- EBI that selection circuit realized in VHDL voice in FPGA general control system IN, OUT, CLK, FS are docked with OUT, IN, CLK, FS of CS CALL pcm bus；

Step 3, comprises selection circuit module inside FPGA general control system, can according to the instruction of client layer, by GPIO1 and The low and high level change of GPIO2, completes the selection of PCM voice flow between VOIP and CS CALL；

Step 4, FPGA general control system comprise synchronous circuit module it is ensured that PCM voice flow select after signal synchronization；

Described selection circuit module design comprises the following steps：

Step one, selection circuit module realizes PCM1 and PCM2 two to bus, is responsible for and the docking of DSP1 and DSP2；

Step 2, selection circuit module receives the instruction of FPGA general control system according to network environment, and control selections circuit determines Selected any road PCM voice flow, the signal in corresponding PCM tetra- signal line is received and sends, do not have selected, block Process；

Step 3, selection circuit module sends the PCM voice flow of selection to synchronous circuit and carries out subsequent treatment；

Described synchronous circuit module design comprises the following steps：

Step one, synchronous circuit module receives the PCM voice flow of selection circuit transmission, is sent to synchronous circuit core processing Area；

Step 2, synchronous circuit module passes through synchronization process mechanism, carries out the synchronization of signal it is ensured that PCM especially by phaselocked loop Voice flow is out-of-step free；

Step 3, synchronous circuit module sends the PCM voice flow after synchronization to SLIC chip, realizes call.