CN103811493A - Semiconductor device and method of forming the same - Google Patents

Semiconductor device and method of forming the same Download PDF

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Publication number
CN103811493A
CN103811493A CN201310164907.7A CN201310164907A CN103811493A CN 103811493 A CN103811493 A CN 103811493A CN 201310164907 A CN201310164907 A CN 201310164907A CN 103811493 A CN103811493 A CN 103811493A
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nmos
grid structure
region
semiconductor substrate
dislocation
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CN103811493B (en
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庄学理
朱鸣
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
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Abstract

The invention discloses a semiconductor device and a method of forming the same. The semiconductor device includes a first NMOS device with a first threshold voltage and a second NMOS device with a second threshold voltage. The first NMOS device includes a first gate structure over a semiconductor substrate, first source/drain (S/D) regions in the semiconductor substrate and adjacent to opposite edges of the first gate structure. The first S/D regions are free of dislocation. The second NMOS device includes a second gate structure over the semiconductor substrate, second S/D regions in the semiconductor substrate and adjacent to opposite edges of the second gate structure, and a dislocation in the second S/D regions.

Description

Semiconductor device and forming method thereof
Technical field
The present invention relates to semiconductor device and forming method thereof.
Background technology
Semiconductor integrated circuit (IC) industry has experienced fast development.In IC evolution, functional density (, the quantity of interconnect devices on every chip area) has increased conventionally and physical dimension (, using the minimum element (or line) that can make of manufacturing process) has reduced.Conventionally this scaled technique is by enhancing productivity and reducing relevant cost and bring benefit.This scaled technique has also increased processing and has manufactured the complexity of IC, and progressive in order to realize these, also needs similar development at IC manufacture view.
For example, along with by scaled to each technology node semiconductor device (such as mos field effect transistor (MOSFET)), for example realize, by the source/drain parts of strain (, stress source region) for increasing carrier mobility and improved device performance.Although be used to form IC device stress source region existing method be enough to substantially realize their desired use, be not still entirely satisfactory in every respect.
Summary of the invention
In order to solve problems of the prior art, according to an aspect of the present invention, provide a kind of semiconductor device, comprise: the first nmos device, have first threshold voltage, described the first nmos device comprises: first grid structure, is positioned at Semiconductor substrate top; The first source/drain (S/D) region, is arranged in described Semiconductor substrate and is adjacent to the opposite edges of described first grid structure, and wherein, a described S/D region does not comprise dislocation; And second nmos device, thering is Second Threshold voltage, described the second nmos device comprises: second grid structure, is positioned at described Semiconductor substrate top; The 2nd S/D region, is arranged in described Semiconductor substrate and is adjacent to the opposite edges of described second grid structure; And dislocation, be arranged in described the 2nd S/D region.
Described device also comprises: the PMOS grid structure that is positioned at described Semiconductor substrate top; Be arranged in described Semiconductor substrate and be adjacent to the Three S's/D region of the opposite edges of described PMOS grid structure; And be arranged in the epitaxially grown parts in described the Three S's/D region.In one embodiment, described epitaxially grown parts are epitaxy Si Ge.In another embodiment, described the Three S's/D region does not comprise dislocation.
In described device, the degree of depth of described dislocation in approximately 10 nanometers in the scope of approximately 150 nanometers.
In described device, described first threshold voltage is greater than described Second Threshold voltage.
In described device, described the first nmos device comprises level threshold value voltage transistor (SVT) and/or high threshold voltage transistors (HVT).
In described device, described the second nmos device comprises low threshold voltage transistor (LVT) and/or super low threshold voltage transistor (uLVT).
In described device, the kind of described the 2nd S/D district inclusion is Si, Ge, Ar, Xe, C, BF 2, As, In or their combination.
In described device, the leakage current of described the first nmos device is less than the leakage current of described the second nmos device.
In described device, the speed of service of described the first nmos device is less than the speed of service of described the second nmos device.
According to a further aspect in the invention, provide a kind of semiconductor device, having comprised: the first nmos device, described the first nmos device comprises: first grid structure, is positioned at Semiconductor substrate top; With the first source/drain (S/D) region, be arranged in described Semiconductor substrate and be adjacent to the opposite edges of described first grid structure, wherein, a described S/D region does not comprise dislocation; The second nmos device, described the second nmos device comprises: second grid structure, is positioned at described Semiconductor substrate top; The 2nd S/D region, is arranged in described Semiconductor substrate and is adjacent to the opposite edges of described second grid structure; And dislocation, be arranged in described the 2nd S/D region, wherein, the threshold voltage of described the first nmos device is greater than the threshold voltage of described the second nmos device; And PMOS device, described PMOS device comprises: the 3rd grid structure, is positioned at described Semiconductor substrate top; With the 3rd source/drain (S/D) region, be arranged in described Semiconductor substrate and be adjacent to the opposite edges of described the 3rd grid structure, wherein, described the Three S's/D region does not comprise dislocation.
In described device, described the Three S's/D region comprises epitaxially grown parts.
In described device, the kind of described the 2nd S/D district inclusion is silicon (Si) or germanium (Ge).
In described device, described dislocation forms along <111> direction.
According to another aspect of the invention, provide a kind of method of manufacturing semiconductor device, having comprised: above substrate, formed a NMOS grid structure and the 2nd NMOS grid structure; Above a described NMOS grid structure, form guard member; In the substrate that is adjacent to described the 2nd NMOS grid structure, form non-crystallization region; Above a described NMOS grid structure and described the 2nd NMOS grid structure, deposit stress film; Implement annealing process to form dislocation in the substrate that is adjacent to described the 2nd NMOS grid structure; And remove described stress film.
In described method, described stress film is silicon nitride, silica, silicon oxynitride or their combination.
In described method, adopt injection technology with approximately 1 × 10 14atom/cm 2to approximately 2 × 10 15atom/cm 2implantation dosage form described non-crystallization region.
In described method, at the temperature of approximately 400 ℃ to approximately 750 ℃, within the time period of approximately 10 seconds to approximately 5 minutes, implement described annealing process by rapid thermal annealing (RTA) technique.
In described method, the technique that is used to form described dislocation be by spike thermal annealing (spike RTA) technique at the temperature of approximately 900 ℃ to approximately 1050 ℃, the annealing process of implementing within the time period of approximately 0.1 second to approximately 2 seconds.
Accompanying drawing explanation
When reading in conjunction with the accompanying drawings, the present invention may be better understood according to the following detailed description.Should be emphasized that, according to the standard practices in industry, various parts are not drawn and the object for illustrating only in proportion.In fact,, in order clearly to discuss, the size of various parts can be increased arbitrarily or be reduced.
Fig. 1 illustrates the flow chart that forms the method for semiconductor device according to each aspect of the present invention.
Fig. 2 to Fig. 6 is according to the cross-sectional side view of the semiconductor device in each stage of manufacturing in the method according to Fig. 1 of one or more embodiment.
Embodiment
In order to implement different parts of the present invention, following discloses content provides many different embodiment or example.Be described below the particular instance of element and layout to simplify the present invention.Certainly these are only that example is not intended for use to limit.For example, in the following description first component the formation above second component or on second component can comprise wherein first component with second component directly to contact the embodiment of formation, and also can comprise and wherein between first component and second component, form extra parts, the embodiment that first component can directly not contacted with second component.In addition, the present invention may repeat accompanying drawing number and/or letter in each example.This repetition is object and itself do not show the relation between discussed each embodiment and/or structure for the sake of simplicity and clearly.Clearly describe but embodied the various equivalents of the principle of the invention although be appreciated that those skilled in the art can find out in this article.
The example of device that can be benefited from one or more embodiment of the present invention is the semiconductor device with field-effect transistor (FET).This device is for example complementary metal oxide semiconductors (CMOS) (CMOS) field-effect transistor.Following discloses content will continue this example each embodiment with explanation the application.But, being appreciated that unless expressly stated, the application should be not limited to the device of particular type.
See figures.1.and.2 to Fig. 6, below describing method 100 and semiconductor device 200 together.Semiconductor device 200 refers to a part for integrated circuit or integrated circuit, it can comprise active device, such as mos field effect transistor (MOSFET), complementary metal oxide semiconductors (CMOS) (CMOS) transistor, high voltage transistor and/or high frequency transistor, other suitable elements and/or their combination.In addition, semiconductor device 200 can comprise passive device, such as resistor, capacitor, inductor and/or fuse.Be appreciated that and can be processed to form semiconductor device 200 by CMOS technology, and therefore in this article some techniques are not described in detail.Can be before method 100, during or other steps are provided afterwards, and for other embodiment of method, steps more described below can be replaced or remove.In addition, be further appreciated that and can in semiconductor device 200, increase miscellaneous part, and for other embodiment of semiconductor device 200, parts more described below can be replaced or remove.
With reference to Fig. 1, the method 100 of manufacturing semiconductor device is described according to each aspect of the present invention.Method 100 starts from step 102, wherein above substrate, forms a NMOS grid pile overlapping piece, the 2nd NMOS grid pile overlapping piece and PMOS grid pile overlapping piece.Method 100 proceeds to step 104, wherein substrate is implemented to pre-amorphous injection (PAI) technique.Method 100 proceeds to step 106, wherein above substrate, deposits stress film.Method 100 proceeds to step 108, wherein substrate is implemented to annealing process.Method 100 proceeds to step 110, wherein removes stress film from substrate.Discussion below for example understands each embodiment of the semiconductor device 200 that can manufacture according to the method for Fig. 1 100.
Fig. 2 to Fig. 6 is the cross-sectional side view at the semiconductor device 200 of each fabrication stage according to the method 100 of Fig. 1.See figures.1.and.2, method 100 starts from step 102, wherein above substrate 202, forms a NMOS grid pile overlapping piece 240, the 2nd NMOS grid pile overlapping piece 250 and PMOS grid pile overlapping piece 260.Each in the one NMOS grid pile overlapping piece 240, the 2nd NMOS grid pile overlapping piece 250 and PMOS grid pile overlapping piece 260 limits the channel region of the substrate 202 of its below.In the present embodiment, preserve a NMOS grid pile overlapping piece 240 and be used to form the nmos device with low-leakage current.The nmos device with low-leakage current for example comprises (for example having level threshold value voltage, 0.3 volt) level threshold value voltage transistor (SVT) and/or there is the high threshold voltage transistors (HVT) of high threshold voltage (for example, 0.4 volt).In the present embodiment, preserve the 2nd NMOS grid pile overlapping piece 250 and be used to form the nmos device with the high speed of service.The nmos device with the high speed of service for example comprises (for example having low threshold voltage, 0.2 volt) low threshold voltage transistor (LVT) and/or there is the super low threshold voltage transistor (uLVT) of low threshold voltage (for example, 0.2 volt of <).
In the present embodiment, substrate 202 is the Semiconductor substrate that comprise silicon.In some optional embodiments, substrate 202 comprises elemental semiconductor, comprises silicon and/or the germanium of crystal form; Compound semiconductor, comprises carborundum, GaAs, gallium phosphide, indium phosphide, indium arsenide and/or indium antimonide; Alloy semiconductor, comprises SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP and/or GaInAsP; Or their combination.In the time that substrate 202 is alloy semiconductor, alloy semiconductor substrate can have gradient SiGe parts, and wherein Si and Ge composition change to another ratio of another location from a ratio of a position of gradient SiGe parts.Can above silicon substrate, form alloy SiGe, and/or SiGe substrate can be strain.In another optional embodiment, Semiconductor substrate can be semiconductor-on-insulator (SOI).
As known in the art, according to designing requirement, substrate 202 comprises various doped regions (for example, p-type trap or N-shaped trap).Doped region is doped with p-type alloy, such as boron or BF 2; And/or N-shaped alloy, such as phosphorus or arsenic.Can be directly on substrate 202, in P well structure, in N well structure, in Dual Well Structure, or use bulge-structure to form doped region.In certain embodiments, substrate 202 comprise isolated part 204 with limit and isolation liner at the bottom of each active region of 202.Isolated part 204 utilizes such as shallow trench isolation and limits and electricity isolation regional from the isolation technology of (STI) or local oxidation of silicon (LOCOS).Isolated part 204 comprises silica, silicon nitride, silicon oxynitride, other suitable materials or their combination.
Still with reference to Fig. 2, in certain embodiments, by succession depositing on substrate 202, also patterning grid dielectric layer 206, gate electrode layer 208 and hard mask layer 210 form a NMOS grid pile overlapping piece 240, the 2nd NMOS grid pile overlapping piece 250 and PMOS grid pile overlapping piece 260.In an example, gate dielectric 206 is the films that comprise silica, silicon nitride, silicon oxynitride, high-k dielectric, other suitable dielectric materials or their combination.High-k dielectric comprises metal oxide.The example that is used for the metal oxide of high-k dielectric comprises the oxide of Li, Be, Mg, Ca, Sr, Sc, Y, Zr, Hf, Al, La, Ce, Pr, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu and composition thereof.In the present embodiment, gate dielectric 206 is thickness at approximately 10 dusts to the high k dielectric layer within the scope of approximately 30 dusts.Can adopt that suitable technique such as ald (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), thermal oxidation, UV ozone oxidation or theys' are combined to form gate dielectric 206.Gate dielectric 206 can also comprise boundary layer (not shown), and this boundary layer is for reducing the damage between gate dielectric 206 and substrate 202.Boundary layer can comprise silica.
Then on gate dielectric 206, form gate electrode layer 208.In certain embodiments, gate electrode layer 208 comprises single layer structure or sandwich construction.In the present embodiment, gate electrode layer 208 comprises polysilicon.In addition, gate electrode layer 208 can be the doped polycrystalline silicon with identical or different dopant species.In one embodiment, the thickness of gate electrode layer 208 at about 30nm in the scope of about 60nm.Can adopt such as the technique of low-pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD), other suitable techniques or their combination and form gate electrode layer 208.Then, above gate electrode layer 208, form hard mask layer 210, and on hard mask layer 210, form the photosensitive layer (not shown) of patterning.The pattern transfer of photosensitive layer, to hard mask layer 210, is then transferred to gate electrode layer 208 and gate dielectric 206 to form a NMOS grid pile overlapping piece 240, the 2nd NMOS grid pile overlapping piece 250 and PMOS grid pile overlapping piece 260.In certain embodiments, hard mask layer 210 comprises silica.In optional embodiment, hard mask layer 210 comprises silicon nitride, silicon oxynitride and/or other suitable dielectric materials, and can adopt the method formation such as CVD or PVD.The thickness of hard mask layer 210 at approximately 100 dusts in the scope of approximately 800 dusts.Then remove photosensitive layer by dry method and/or wet method stripping technology.
With further reference to Fig. 2, form sidewall spacer (or being called as gate spacer part) 212 in abutting connection with the opposing sidewalls of a NMOS grid pile overlapping piece 240, the 2nd NMOS grid pile overlapping piece 250 and PMOS grid pile overlapping piece 260.In certain embodiments, sidewall spacer 212 comprises single layer structure or sandwich construction.In the present embodiment, comprise that by depositing operation CVD, PVD, ALD or other suitable technology form spacer materia cover layer (not shown) above NMOS grid pile overlapping piece 240, PMOS grid pile overlapping piece 250 and substrate 202.In certain embodiments, spacer materia comprises silica, silicon nitride, silicon oxynitride, other suitable materials or their combination.In certain embodiments, the thickness of the layer of spacer material of deposition at approximately 10 dusts in the scope of approximately 60 dusts.Then, spacer materia is implemented to anisotropic etching process to form sidewall spacer 212.Sidewall spacer 212 can be protected the sidewall of a NMOS gate spacer part 240, the 2nd NMOS gate spacer part 250 and PMOS gate spacer part 260.Alternatively, the doped region that sidewall spacer 212 can form below for skew, such as heavily doped regions and source/drain.
In certain embodiments, in the substrate 202 at edge that is adjacent to PMOS grid pile overlapping piece 260, form source/drain (S/D) parts 214.In certain embodiments, the end face of source/drain parts 214 is higher than the end face of substrate 202.In certain embodiments, the end face of source/drain parts 214 is higher than the end face of substrate 202, and its difference in height is between about 1nm and about 10nm.In optional embodiment, the end face of the end face of source/drain parts 214 and substrate 202 is substantially coplanar.In certain embodiments, first in substrate 202, form groove cavity (not shown), then in groove cavity, growth strain material forms source/drain parts 214.In certain embodiments, employing comprises the technique growth strain material of selective epitaxy growth (SEG), cyclic deposition and etching (CDE), chemical vapor deposition (CVD) technology (for example, vapor phase epitaxy (VPE) and/or ultra high vacuum CVD (UHV-CVD)), molecular beam epitaxy (MBE), other suitable epitaxy techniques or their combination.In certain embodiments, strain gauge material has the lattice constant that is different from substrate 202 to produce strain or stress on the channel region at semiconductor device 200, and therefore makes the carrier mobility of device can improve device performance.
With reference to Fig. 1 and Fig. 3, method 100 proceeds to step 104, wherein substrate 202 is implemented to pre-amorphous injection (PAI) technique 218.In certain embodiments, thus PAI technique 218 is injected substrate 202 and cause damage to form non-crystallization region (amorphized region) 220 to the lattice structure of substrate 202.In the present embodiment, in source/drain (S/D) region of opposite edges that is adjacent to the 2nd NMOS grid pile overlapping piece 250, form non-crystallization region 220.Non-crystallization region 220 has depth D 1 (measuring from the upper surface of substrate 202).Form depth D 1 according to design specification.In certain embodiments, depth D 1 in approximately 10 nanometers in the scope of approximately 150 nanometers.In the present embodiment, depth D 1 is less than approximately 100 nanometers.Because sidewall spacer 212 is used for assembling the Implantation Energy of PAI technique 218, can carry out controlling depth D1 by the thickness of sidewall spacer 212.Equally, can pass through PAI technique 218, carry out controlling depth D1 such as Implantation Energy, injection kind and/or implantation dosage.In at least one embodiment, PAI technique 218 use silicon (Si) or germanium (Ge) inject substrate 202.In optional embodiment, PAI technique 218 can be used other to inject kind, such as Ar, Xe, C, BF 2, As, In, other suitable injection kinds or their combination.In the present embodiment, according to implantation temperature, PAI technique 218 about 15KeV under the Implantation Energy of about 50KeV with approximately 1 × 10 14atom/cm 2to approximately 2 × 10 15atom/cm 2implantation dosage inject Si or Ge.In at least one embodiment, for example, in the lower PAI technique 218 of implementing of room temperature (, 25 ℃).In optional embodiment, for example, at low temperature (,-60 ℃ to-100 ℃) lower to regulating Cryo (low temperature) function in ion implantor to implement PAI technique 218 to improve the decrystallized efficiency of injection.In certain embodiments, implement PAI technique 218 with approximately 0 degree to the inclination angle of approximately 20 degree.
In some optional embodiments, PAI technique 218 can be multi-step injection technology, comprises at least first step and the second step of injection technology.Adopt respectively the first and second Implantation Energy levels, the first and second implantation dosages, and first step and the second step of injection technology are implemented in the first and second injection inclinations angle.In at least one embodiment, the first and second Implantation Energy levels at about 15KeV in the scope of about 50KeV.In another embodiment, the first Implantation Energy level is higher than the second Implantation Energy level.In at least one embodiment, the first and second implantation dosages are approximately 1 × 10 14atom/cm 2to approximately 2 × 10 15atom/cm 2scope in.In another embodiment, the first implantation dosage is greater than the second implantation dosage.In certain embodiments, the Meige dosage of the first and second implantation dosages is approximately 1 × 10 14atom/cm 2to approximately 2 × 10 15atom/cm 2scope in, and ratio between the first and second implantation dosages is in the scope of approximately 1: 1 to approximately 7: 3.In one embodiment, the first and second inclinations angle are spent to the scopes of approximately 20 degree approximately 0.In another embodiment, the first injection inclination angle is greater than the second injection inclination angle.
In the present embodiment; during PAI technique 218,260 protected 216 of a NMOS grid pile overlapping piece 240 and PMOS grid pile overlapping pieces cover and make the edge that is adjacent to a NMOS grid pile overlapping piece 240 or PMOS grid pile overlapping piece 260 not form non-crystallization region.In certain embodiments, guard member 216 is photoresist layer or hard mask layers of patterning.Therefore, can avoid the rain supply of the NMOS grid pile overlapping piece 240 being caused by the PAI technique 218 of damage substrate 202, thereby the leakage current of a NMOS grid pile overlapping piece 240 is minimized.After PAI technique 218, remove guard member 216 by for example etch process or stripping technology.
With reference to Fig. 1 and Fig. 4, method 100 proceeds to step 106, above a NMOS grid pile overlapping piece 240, the 2nd NMOS grid pile overlapping piece 250, PMOS grid pile overlapping piece 260 and substrate 202, deposits stress film 222.Can be by chemical vapor deposition (CVD), physical vapor deposition (PVD), ald (ALD), high-density plasma CVD (HDPCVD), coating, other suitable methods and/or they be combined to form stress film 222.Stress film 222 comprises dielectric material.In certain embodiments, stress film 222 comprises silicon nitride, silicon oxynitride, SiCN and/or their combination.In optional embodiment, stress film 222 comprises silica.In certain embodiments, the thickness of stress film 222 is greater than the thickness of the spacer materia that is used to form sidewall spacer 212.In certain embodiments, the thickness of stress film 222 at approximately 100 dusts in the scope of approximately 300 dusts.In certain embodiments, making in the subsequent anneal technique of non-crystallization region 220 recrystallizations, stress film 222 is for providing tensile stress.
With reference to Fig. 1 and Fig. 5, method 100 proceeds to step 108, and substrate 202 is implemented to annealing process 224.In certain embodiments, annealing process 224 is rapid thermal annealing (RTA) technique, spike RTA technique or millisecond thermal annealing (MSA) technique (for example, millisecond LASER HEAT annealing process).In at least one embodiment, annealing process 224 is included in the RTA technique that continues the time enforcement of approximately 10 seconds to approximately 5 minutes at the temperature of approximately 600 ℃ to approximately 750 ℃.In optional embodiment, annealing process 224 is included in the spike RTA technique that continues the time enforcement of approximately 0.1 second to approximately 2 seconds at the temperature of approximately 990 ℃ to approximately 1050 ℃.In optional embodiment, annealing process 224 can also comprise that preheating step is to minimize (or even eliminating) end (EOR) defect.In certain embodiments, can under being the temperature of approximately 400 ℃ to approximately 700 ℃, scope implement preheating step.In certain embodiments, preheating step can be implemented the time of approximately 10 seconds to approximately 5 minutes.In the present embodiment, at the temperature of approximately 550 ℃, implement preheating step, continue approximately 30 seconds.
During annealing process 224, because non-crystallization region 220 is by recrystallization, in substrate 202, form the dislocation 226 of the recrystallization corresponding region of non-crystallization region 220.In certain embodiments, be adjacent to the opposite edges formation dislocation 226 of the 2nd NMOS grid pile overlapping piece 250.In certain embodiments, substrate 202 refers to (100) substrate, and forms dislocation 226 along <111> direction.In certain embodiments, <111> direction has the angle θ that the surperficial datum level perpendicular to substrate 202 is measured relatively, and this angle θ is that approximately 25 degree are to approximately 45 degree.In the present embodiment, dislocation 226 has the <111> direction that angle θ is approximately 35 degree.Start to form dislocation 226 from pinch-off point (pinchoff point) 228.Pinch-off point 228 has the depth D 2 of measuring from the upper surface of substrate 202.In certain embodiments, the depth D 2 of pinch-off point 228 in approximately 10 nanometers in the scope of approximately 150 nanometers.In the present embodiment, the depth D 2 of pinch-off point 228 in approximately 10 nanometers in the scope of approximately 30 nanometers.Pinch-off point 228 has level buffering (vicinity) W from the adjacent gate edge metering of the 2nd NMOS grid pile overlapping piece 250.Forming level buffering W and depth D 2 and they according to design specification is functions of annealing process 224.In certain embodiments, the level of pinch-off point 228 buffering W in approximately-5 nanometers to the scope of approximately 10 nanometers ("-" represents that pinch-off point 228 is positioned at NMOS grid pile overlapping piece 240 or PMOS grid pile overlapping piece 250 belows).Can form like this pinch-off point 228 makes it not be arranged on the channel region that is arranged in substrate 202 being limited by the 2nd NMOS grid pile overlapping piece 250.
With reference to Fig. 1 and Fig. 6, method 100 proceeds to step 110, removes stress film 222 from substrate 202.For example, remove stress film 222 by using the wet etching of phosphoric acid or hydrofluoric acid, or by the dry ecthing of use suitable etch agent.
According to disclosed embodiment, the benefit of the dislocation of NMOS grid pile overlapping piece be for nmos device (such as, low threshold voltage transistor (LVT) and/or super low threshold voltage transistor (uLVT)) active region (for example, source/drain) thus in the dislocation that the forms stress that can improve in the channel region of NMOS grid pile overlapping piece increase the device speed of service.In addition, prevent that the technique that for example, forms dislocation in the active region (, source/drain) for nmos device (such as level threshold value voltage transistor (SVT) and/or high threshold voltage transistors (HVT)) from can improve device performance by the increase of prevention leakage current.Therefore, the stress level that disclosed embodiment provides increase in channel region to be to improve the carrier mobility of nmos device of the high speed of service of needs, and needs the nmos device of low-leakage current not increase rain supply to another.Be appreciated that, different embodiment can have advantages of different, and there is no specific advantage be that any embodiment is essential.
Semiconductor device can implement further CMOS or MOS technology processes to form various parts.For example, method 100 can continue to form master space part.Can also form contact component, such as silicide regions.Contact component comprises silicide material, such as nickle silicide (NiSi), nickel-platinum suicide (NiPtSi), nickel-platinum suicide germanium (NiPtGeSi), nickle silicide germanium (NiGeSi), ytterbium silicide (YbSi), platinum silicide (PtSi), silication iridium (IrSi), silication bait (ErSi), cobalt silicide (CoSi), other suitable electric conducting materials and/or their combination.Can be by comprising depositing metal layers; To metal level anneal make metal level can with pasc reaction with form silicide; Then the technique of removing unreacted metal level forms contact component.Can further on substrate, form interlayer dielectric (ILD) layer and substrate is further implemented to chemico-mechanical polishing (CMP) technique with planarization substrate.In addition, can, before forming ILD layer, form contact etch stop layer (CESL) at the top of grid structure.
In an embodiment, a NMOS grid pile overlapping piece 240, the 2nd NMOS grid pile overlapping piece 250 and PMOS grid pile overlapping piece 260 retain polysilicon in resulting devices.In another embodiment, implement grid and replace technique (or rear grid technology), wherein replace the first polysilicon NMOS grid pile overlapping piece 240, the second polysilicon NMOS grid pile overlapping piece 250 and polysilicon PMOS grid pile overlapping piece 260 with metal gates.For example, metal gates can be replaced the grid pile overlapping piece (, polysilicon gate stack) of a NMOS grid pile overlapping piece 240, the 2nd NMOS grid pile overlapping piece 250 and PMOS grid pile overlapping piece 260.Metal gates comprises lining, work function layer, conductive layer, metal gate layers, packed layer, other suitable layers and/or their combination.Various layers comprise any suitable material, such as aluminium, copper, tungsten, titanium, tantalum, tantalum aluminium, tantalum nitride aluminium, titanium nitride, tantalum nitride, nickle silicide, cobalt silicide, silver, TaC, TaSiN, TaCN, TiAl, TiAlN, WN, metal alloy, other suitable materials and/or their combination.
Following process can further form various contact/through hole/lines and multilayer interconnection parts (for example, metal level and interlayer dielectric) on substrate, and it is configured to connect various parts or the structure of semiconductor device.Miscellaneous part can provide electrical interconnection to device.For example, multilayer interconnection comprises vertical interconnect, such as conventional through hole or contact; With horizontal interconnect part, such as metal wire.Various interconnecting members can be applied various electric conducting materials, comprise copper, tungsten and/or silicide.In an example, inlay and/or dual-damascene technics is used to form the multilayer interconnect structure that copper is relevant.
Disclosed semiconductor device can be in various application, such as digital circuit, image sensor devices, heterogeneous semiconductor device, dynamic random access memory (DRAM) unit, single-electronic transistor (SET) and/or other microelectronic components (being referred to as in this article microelectronic component).Certainly, each aspect of the present invention is also applicable to and/or is easy to adapt to the transistor of other types, comprise single gridistor, double gate transistor and other multi-gated transistors, and can be for many different application, comprise sensor unit, memory cell, logical block and other.
In one embodiment, a kind of semiconductor device comprises first nmos device with first threshold voltage and second nmos device with Second Threshold voltage.The first nmos device comprise be arranged in Semiconductor substrate top first grid structure, be positioned at Semiconductor substrate and be adjacent to the first source/drain (S/D) region of the opposite edges of first grid structure.The one S/D region does not comprise dislocation.The second nmos device comprise be arranged in Semiconductor substrate top second grid structure, be arranged in Semiconductor substrate and be adjacent to second grid structure opposite edges the 2nd S/D region and be positioned at the dislocation in the 2nd S/D region.
In another embodiment, a kind of semiconductor device comprises the first nmos device, the second nmos device and PMOS device.The first nmos device comprises the first grid structure that is positioned at Semiconductor substrate top, and is arranged in Semiconductor substrate and is adjacent to the first source/drain (S/D) region of the opposite edges of first grid structure.The one S/D region does not comprise dislocation.The second nmos device comprise be arranged in Semiconductor substrate top second grid structure, be arranged in Semiconductor substrate and be adjacent to second grid structure opposite edges the 2nd S/D region and be positioned at the dislocation in the 2nd S/D region.The threshold voltage of the first nmos device is greater than the threshold voltage of the second nmos device.PMOS device comprises the 3rd grid structure that is positioned at Semiconductor substrate top, and is arranged in Semiconductor substrate and is adjacent to the 3rd source/drain (S/D) region of the opposite edges of the 3rd grid structure.The Three S's/D region does not comprise dislocation.
In another embodiment, a kind of method that is used to form semiconductor device comprises: above substrate, form a NMOS grid structure and the 2nd NMOS grid structure; Above a NMOS grid structure, form guard member; In the substrate that is adjacent to the 2nd NMOS grid structure, form non-crystallization region; Above a NMOS grid structure and the 2nd NMOS grid structure, deposit stress film; Implement annealing process to form dislocation in the substrate that is adjacent to the 2nd NMOS grid structure; And removal stress film.
In order to implement different parts of the present invention, above disclosure provides many different embodiment or example.The particular instance of element and layout is described to simplify the present invention in the above.Certainly these are only that example does not intend to limit.Therefore,, in the situation that not deviating from scope of the present invention, can arrange, combine or configure element disclosed herein to be different from the mode of the exemplary embodiment illustrating herein.
Discuss the parts of some embodiment above, made those of skill in the art's each side that the present invention may be better understood.Those of skill in the art should be appreciated that, they can design or change as basis with the present invention easily other for reach with herein the identical object of the embodiment that introduces and/or realize technique and the structure of same advantage.Those of skill in the art also should recognize, these equivalent constructions do not deviate from the spirit and scope of the present invention, and in the situation that not deviating from the spirit and scope of the present invention, can carry out multiple variation, replacement and change.

Claims (10)

1. a semiconductor device, comprising:
The first nmos device, has first threshold voltage, and described the first nmos device comprises:
First grid structure, is positioned at Semiconductor substrate top;
The first source/drain (S/D) region, is arranged in described Semiconductor substrate and is adjacent to the opposite edges of described first grid structure, and wherein, a described S/D region does not comprise dislocation; And
The second nmos device, has Second Threshold voltage, and described the second nmos device comprises:
Second grid structure, is positioned at described Semiconductor substrate top;
The 2nd S/D region, is arranged in described Semiconductor substrate and is adjacent to the opposite edges of described second grid structure; With
Dislocation, is arranged in described the 2nd S/D region.
2. device according to claim 1, also comprises:
Be positioned at the PMOS grid structure of described Semiconductor substrate top;
Be arranged in described Semiconductor substrate and be adjacent to the Three S's/D region of the opposite edges of described PMOS grid structure; And
Be arranged in the epitaxially grown parts in described the Three S's/D region.
3. device according to claim 2, wherein, described the Three S's/D region does not comprise dislocation.
4. device according to claim 1, wherein, the degree of depth of described dislocation in approximately 10 nanometers in the scope of approximately 150 nanometers.
5. device according to claim 1, wherein, described first threshold voltage is greater than described Second Threshold voltage.
6. device according to claim 1, wherein, the leakage current of described the first nmos device is less than the leakage current of described the second nmos device.
7. device according to claim 1, wherein, the speed of service of described the first nmos device is less than the speed of service of described the second nmos device.
8. a semiconductor device, comprising:
The first nmos device, comprising:
First grid structure, is positioned at Semiconductor substrate top; With
The first source/drain (S/D) region, is arranged in described Semiconductor substrate and is adjacent to the opposite edges of described first grid structure, and wherein, a described S/D region does not comprise dislocation; The second nmos device, comprising:
Second grid structure, is positioned at described Semiconductor substrate top;
The 2nd S/D region, is arranged in described Semiconductor substrate and is adjacent to the opposite edges of described second grid structure; With
Dislocation, is arranged in described the 2nd S/D region, and wherein, the threshold voltage of described the first nmos device is greater than the threshold voltage of described the second nmos device; And PMOS device, comprising:
The 3rd grid structure, is positioned at described Semiconductor substrate top; With
The 3rd source/drain (S/D) region, is arranged in described Semiconductor substrate and is adjacent to
The opposite edges of described the 3rd grid structure, wherein, described the Three S's/D region does not comprise dislocation.
9. device according to claim 8, wherein, described dislocation forms along <111> direction.
10. a method of manufacturing semiconductor device, comprising:
Above substrate, form a NMOS grid structure and the 2nd NMOS grid structure;
Above a described NMOS grid structure, form guard member;
In the substrate that is adjacent to described the 2nd NMOS grid structure, form non-crystallization region;
Above a described NMOS grid structure and described the 2nd NMOS grid structure, deposit stress film;
Implement annealing process to form dislocation in the substrate that is adjacent to described the 2nd NMOS grid structure; And
Remove described stress film.
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