CN103811322A - Semiconductor structure and formation method thereof - Google Patents
Semiconductor structure and formation method thereof Download PDFInfo
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- CN103811322A CN103811322A CN201210454418.0A CN201210454418A CN103811322A CN 103811322 A CN103811322 A CN 103811322A CN 201210454418 A CN201210454418 A CN 201210454418A CN 103811322 A CN103811322 A CN 103811322A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 99
- 238000000034 method Methods 0.000 title claims abstract description 68
- 230000015572 biosynthetic process Effects 0.000 title claims abstract description 51
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 186
- 239000000463 material Substances 0.000 claims abstract description 144
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 103
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 103
- 229910052751 metal Inorganic materials 0.000 claims abstract description 98
- 239000002184 metal Substances 0.000 claims abstract description 98
- 239000000758 substrate Substances 0.000 claims abstract description 61
- 238000005530 etching Methods 0.000 claims abstract description 25
- 238000002955 isolation Methods 0.000 claims abstract description 21
- 239000002210 silicon-based material Substances 0.000 claims abstract description 14
- 229920005591 polysilicon Polymers 0.000 claims description 177
- 239000003989 dielectric material Substances 0.000 claims description 51
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 23
- 238000005516 engineering process Methods 0.000 claims description 15
- 239000007772 electrode material Substances 0.000 claims description 13
- 239000000377 silicon dioxide Substances 0.000 claims description 10
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 7
- 229910052710 silicon Inorganic materials 0.000 claims description 7
- 239000010703 silicon Substances 0.000 claims description 7
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 6
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 claims description 6
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 6
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 3
- 239000000126 substance Substances 0.000 abstract description 8
- 238000000227 grinding Methods 0.000 abstract description 7
- 239000010410 layer Substances 0.000 description 246
- PXHVJJICTQNCMI-UHFFFAOYSA-N nickel Substances [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 15
- 229910052759 nickel Inorganic materials 0.000 description 8
- 238000003701 mechanical milling Methods 0.000 description 7
- 229920002120 photoresistant polymer Polymers 0.000 description 6
- 239000000243 solution Substances 0.000 description 6
- 150000002500 ions Chemical class 0.000 description 4
- WGTYBPLFGIVFAS-UHFFFAOYSA-M tetramethylammonium hydroxide Chemical compound [OH-].C[N+](C)(C)C WGTYBPLFGIVFAS-UHFFFAOYSA-M 0.000 description 4
- 238000001039 wet etching Methods 0.000 description 4
- 238000000137 annealing Methods 0.000 description 3
- 230000004888 barrier function Effects 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- CEPICIBPGDWCRU-UHFFFAOYSA-N [Si].[Hf] Chemical compound [Si].[Hf] CEPICIBPGDWCRU-UHFFFAOYSA-N 0.000 description 2
- ILCYGSITMBHYNK-UHFFFAOYSA-N [Si]=O.[Hf] Chemical compound [Si]=O.[Hf] ILCYGSITMBHYNK-UHFFFAOYSA-N 0.000 description 2
- 238000010276 construction Methods 0.000 description 2
- 230000001276 controlling effect Effects 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- ZQXQADNTSSMHJI-UHFFFAOYSA-N hafnium(4+) oxygen(2-) tantalum(5+) Chemical compound [O-2].[Ta+5].[Hf+4] ZQXQADNTSSMHJI-UHFFFAOYSA-N 0.000 description 2
- KQHQLIAOAVMAOW-UHFFFAOYSA-N hafnium(4+) oxygen(2-) zirconium(4+) Chemical compound [O--].[O--].[O--].[O--].[Zr+4].[Hf+4] KQHQLIAOAVMAOW-UHFFFAOYSA-N 0.000 description 2
- KUVFGOLWQIXGBP-UHFFFAOYSA-N hafnium(4+);oxygen(2-);titanium(4+) Chemical compound [O-2].[O-2].[O-2].[O-2].[Ti+4].[Hf+4] KUVFGOLWQIXGBP-UHFFFAOYSA-N 0.000 description 2
- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(iv) oxide Chemical compound O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 description 2
- 238000002513 implantation Methods 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 2
- 239000002346 layers by function Substances 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- ZXEYZECDXFPJRJ-UHFFFAOYSA-N $l^{3}-silane;platinum Chemical compound [SiH3].[Pt] ZXEYZECDXFPJRJ-UHFFFAOYSA-N 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- 229910004166 TaN Inorganic materials 0.000 description 1
- 229910004200 TaSiN Inorganic materials 0.000 description 1
- 229910010038 TiAl Inorganic materials 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 229910017052 cobalt Inorganic materials 0.000 description 1
- 239000010941 cobalt Substances 0.000 description 1
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000009422 external insulation Methods 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 230000009931 harmful effect Effects 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Substances [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 1
- 229910021339 platinum silicide Inorganic materials 0.000 description 1
- 230000001105 regulatory effect Effects 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000010944 silver (metal) Substances 0.000 description 1
- 229910003468 tantalcarbide Inorganic materials 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- 229910052718 tin Inorganic materials 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 229910021341 titanium silicide Inorganic materials 0.000 description 1
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 description 1
- 229910021342 tungsten silicide Inorganic materials 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28079—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being a single metal, e.g. Ta, W, Mo, Al
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28088—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being a composite, e.g. TiN
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
Abstract
The invention discloses a semiconductor structure and a formation method thereof. The formation method comprises the steps of providing a semiconductor substrate, forming an shallow trench isolation structure in the semiconductor substrate, forming a first polycrystalline silicon material layer on the semiconductor substrate and the shallow trench isolation structure and a cover material layer on one part of the surface of the first polycrystalline silicon material layer, and a second polycrystalline silicon material layer on one part of the surface of the first polycrystalline silicon material layer, and etching the second polycrystalline silicon material layer, the cover material layer and the first polycrystalline silicon material layer to form a pseudo-gate structure and a polycrystalline resistor. The pseudo-gate structure is formed by the first polycrystalline silicon material layer and the second polycrystalline silicon material layer, while the polycrystalline resistor is formed only by the first polycrystalline silicon material layer, so that height difference is formed between the surface of the pseudo-gate structure and the surface of the polycrystalline resistor; as a chemical mechanical grinding process for forming a metal gate does not affect the polycrystalline resistor and a metal silicide on the surface of the polycrystalline resistor, the pseudo-gate structure and the polycrystalline resistor can be formed simultaneously.
Description
Technical field
The present invention relates to semiconductor technology, particularly a kind of semiconductor structure that is integrated with MOS transistor and polysilicon resistance and forming method thereof.
Background technology
Along with the characteristic size (CD of semiconductor device, Critical Dimension) become more and more less, the integrated level of semiconductor chip is more and more higher, needs the number of devices and the type that form also to get more and more in unit are, thereby also more and more higher to the requirement of semiconductor technology.The how position of the various different components of reasonable arrangement and utilize the common ground of each device manufacture to save semiconductor technology step and material to become the focus of present research.In semiconductor device is manufactured, polysilicon is a kind of electric conducting material being in daily use, conventionally can be for making gate electrode, the high value polysilicon resistance etc. of MOS transistor.Prior art forms polysilicon resistance conventionally in the polygate electrodes that forms MOS transistor, can save technique.
Please refer to Fig. 1 ~ Fig. 5, for existing technique forms the cross-sectional view of the forming process of MOS transistor and polysilicon resistance simultaneously.
Please refer to Fig. 1, Semiconductor substrate 10 is provided, at the interior formation fleet plough groove isolation structure 11 of Semiconductor substrate 10, form oxide layer 12 on described Semiconductor substrate 10 surfaces, form polysilicon layer 13 on described oxide layer 12 surfaces;
Please refer to Fig. 2, described polysilicon layer 13(be please refer to Fig. 1) and oxide layer 12(please refer to Fig. 1) carry out etching, until expose Semiconductor substrate 10, described oxide layer 12 forms gate oxide 14, described polysilicon layer 13 forms gate electrode 15, the gate oxide 14 and the gate electrode 15 that are positioned at described Semiconductor substrate 10 surfaces form grid structure 16, and the polysilicon layer 13 being positioned on described fleet plough groove isolation structure 11 becomes polysilicon resistance 17;
Please refer to Fig. 3, form side wall 18 at the sidewall of described grid structure 16 and polysilicon resistance 17, in the interior formation of Semiconductor substrate 10 source region 19 and the drain region 20 of described grid structure 16 both sides;
Please refer to Fig. 4, in described source region 19, drain region 20, grid structure 16 and polysilicon resistance 17 surfaces form layer of dielectric material 21, and described layer of dielectric material 21 is carried out to etching, expose part source region 19, drain region 20 surface, part gate electrode 15 surface and be positioned at the part surface at polysilicon resistance 17 two ends;
Please refer to Fig. 5, the source region 19, drain region 20, gate electrode 15 and polysilicon resistance 17 surfaces that expose at described dielectric layer 21 form metal silicide 22.
Along with semiconductor device becomes more and more less, metal gates has slowly substituted traditional polysilicon gate becomes the grid structure of main flow.But when after utilizing, grid technique forms the MOS transistor that grid is metal gate, described MOS transistor can not form with polysilicon resistance simultaneously.
More formation technique about polysilicon resistance please refer to the american documentation literature that the patent No. is US6400252B1.
Summary of the invention
The problem that the present invention solves is to provide a kind of semiconductor structure that is integrated with MOS transistor and polysilicon resistance and forming method thereof, and making grid is that MOS transistor and the polysilicon resistance of metal gates can form simultaneously.
For addressing the above problem, technical solution of the present invention provides a kind of formation method of semiconductor structure, comprise: Semiconductor substrate is provided, and described Semiconductor substrate comprises first area and second area, form fleet plough groove isolation structure at the second area of described Semiconductor substrate; Form gate dielectric material layer in described Semiconductor substrate and surface of shallow trench isolation structure, form the first polysilicon material layer on described gate dielectric material layer surface, the first polysilicon material layer surface at described second area forms layer of cover material, the first polysilicon material layer surface in described first area forms the second polysilicon material layer, described the second polysilicon material layer and layer of cover material flush; Form the first mask layer on described the second polysilicon material layer, layer of cover material surface, take described the first mask layer as mask, described the second polysilicon material layer, layer of cover material, the first polysilicon material layer, gate dielectric material layer are carried out to etching, form be positioned at surface, Semiconductor substrate first area pseudo-grid structure, be positioned at the polysilicon resistance on fleet plough groove isolation structure and be positioned at the cover layer on described polysilicon resistance surface; In the Semiconductor substrate of described pseudo-grid structure both sides, form source region and drain region; Form the first silicide in described source region and surface, drain region; Etched portions cover layer, forms the second silicide on the surface at described polysilicon resistance two ends; Form first medium layer at described semiconductor substrate surface, described first medium layer covers described pseudo-grid structure and cover layer, described first medium layer is carried out to the first cmp, until expose described pseudo-grid structure and cover surface; Remove described pseudo-grid structure, form the first opening, in described the first opening, fill full metal level, described metal level is carried out to the second cmp, form metal gates.
Optionally, in the time that described gate dielectric material layer is silicon oxide layer, described metal level comprises high-K gate dielectric material layer, be positioned at the functional material layer on high-K gate dielectric material layer surface and be positioned at the metal gate electrode material layer on described functional material layer surface, and the technique that forms described the first silicide, the second silicide is carried out after forming metal gates.
Optionally, in the time that described gate dielectric material layer is high-K gate dielectric material layer, described metal level comprises functional material layer and the metal gate electrode material layer that is positioned at described functional material layer surface, and the technique that forms described the first silicide, the second silicide was carried out or carries out after forming metal gates before forming metal gates.
Optionally, when forming described the first silicide, when the technique of the second silicide is carried out after forming described metal gates, form described the first silicide, the concrete technology of the second silicide comprises: at described first medium layer, metal gates and cover surface form the second mask layer, take described the second mask layer as mask, described first medium layer and cover layer are carried out to etching, in described source region, surface, drain region forms the second opening, surface at described polysilicon resistance two ends forms the 3rd opening, the source region exposing at the second opening and surface, drain region form the first silicide, the surface at the polysilicon resistance two ends that expose at the 3rd opening forms the second silicide.
Optionally, described the second opening, the 3rd opening adopt same etch step to form, and described the first silicide, the second silicide adopt same Formation of silicide step to form.
Optionally, while carrying out before the technique of described the first silicide of formation, the second silicide is forming described metal gates, the concrete technology that forms described the first silicide, the second silicide comprises: after forming described polysilicon resistance, source region and drain region, cover layer to described polysilicon resistance two end surfaces carries out etching, until expose the surface at described polysilicon resistance two ends, form the first silicide in described source region and surface, drain region, form the second silicide on the surface at the described polysilicon resistance two ends that expose.
Optionally, described the first silicide, the second silicide adopt same Formation of silicide step to form.
Optionally, the height on described source region, surface, drain region is corresponding with the height on polysilicon resistance surface.
Optionally, the difference in height between described source region, surface, drain region and polysilicon resistance surface is 0 nanometer ~ 30 nanometer.
Optionally, described source region, high 10 nanometer ~ 50 nanometers of drain region surface ratio semiconductor substrate surface.
Optionally, the thickness range of described the first polysilicon material layer is 10 nanometer ~ 50 nanometers.
Optionally, described tectal thickness range is 10 nanometer ~ 50 nanometers.
Optionally, the technique that forms described source region, drain region comprises: in the Semiconductor substrate of described pseudo-grid structure both sides, form the first groove and the second groove, utilize selective epitaxial process in described the first groove and the second groove, to fill full germanium silicon material and carbofrax material, form source region and drain region, the surface in described source region and drain region is higher than semiconductor substrate surface.
Optionally, described tectal material is silica, silicon nitride or silicon oxynitride.
Technical solution of the present invention also provides a kind of semiconductor structure, and described semiconductor structure comprises MOS transistor and polysilicon resistance, and described semiconductor structure adopts the formation method of above-mentioned semiconductor structure to form.
Compared with prior art, the present invention has the following advantages:
Because the polysilicon material layer that forms described pseudo-grid structure comprises the first polysilicon material layer and the second polysilicon material layer, and the polysilicon material layer that forms described polysilicon resistance is only the first polysilicon material layer, make described pseudo-grid body structure surface and polysilicon resistance surface there is difference in height, form the chemical mechanical milling tech of metal gates and can not impact the metal silicide on polysilicon resistance surface, making described grid is that MOS transistor and the polysilicon resistance of metal gate can form simultaneously.
Further, because the height on described source region and surface, drain region is corresponding with the height on polysilicon resistance surface, make to utilize etching and Formation of silicide technique just can form the first silicide and the second silicide, reduced cost.
Accompanying drawing explanation
Fig. 1 ~ Fig. 5 is the cross-sectional view that existing technique forms the forming process of MOS transistor and polysilicon resistance simultaneously;
Fig. 6 ~ Figure 14 is the cross-sectional view of the forming process of the semiconductor structure of the embodiment of the present invention.
Embodiment
As shown in background technology, the polysilicon resistance 17 of prior art is to form with polysilicon gate construction 16 simultaneously, the height of described polysilicon resistance 17 and grid structure 16 equates, and fleet plough groove isolation structure 11 surfaces that form due to prior art tend to a little more than Semiconductor substrate 10 surfaces, make the surface of polysilicon resistance 17 can be a little more than the surface of grid structure 16, metal silicide 22 surfaces on polysilicon resistance 17 surfaces can be higher than grid structure 16 surfaces.When but after utilizing, grid technique forms metal gates, if polysilicon resistance and pseudo-grid structure form simultaneously, the follow-up chemical mechanical milling tech formation metal gates that need to utilize twice, the height of the metal gates forming equals the height of pseudo-grid structure, because the actual height of polysilicon resistance can be a little more than the height of the pseudo-grid of polysilicon, described chemical mechanical milling tech can destroy the metal silicide on polysilicon resistance and surface or remove, affect device performance, therefore utilize MOS transistor and the polysilicon resistance that prior art can not be metal gates by grid to form simultaneously.
Therefore, the embodiment of the present invention provides a kind of formation method of semiconductor structure, because the polysilicon material layer that forms described pseudo-grid structure comprises the first polysilicon material layer and the second polysilicon material layer, and the polysilicon material layer that forms described polysilicon resistance is only the first polysilicon material layer, make described pseudo-grid body structure surface and polysilicon resistance surface there is difference in height, the chemical mechanical milling tech that forms metal gates can not impact the metal silicide on polysilicon resistance surface, making described grid is that MOS transistor and the polysilicon resistance of metal gate can form simultaneously.
For above-mentioned purpose of the present invention, feature and advantage can more be become apparent, below in conjunction with accompanying drawing, the specific embodiment of the present invention is described in detail.
Set forth detail in the following description so that fully understand the present invention.But the present invention can be different from alternate manner described here and implements with multiple, and those skilled in the art can do similar popularization without prejudice to intension of the present invention in the situation that.Therefore the present invention is not subject to the restriction of following public concrete enforcement.
Please refer to Fig. 6 to Figure 14, is the cross-sectional view of the forming process of the semiconductor structure of the embodiment of the present invention.
Please refer to Fig. 6, Semiconductor substrate 100 is provided, described Semiconductor substrate 100 comprises first area I and second area II, at the interior formation fleet plough groove isolation structure 105 of Semiconductor substrate 100 of described second area II.
Described Semiconductor substrate 100 is silicon substrate, silicon-on-insulator substrate, silicon-Germanium substrate one wherein.Described first area I is adjacent with second area II or be separated by.In subsequent technique, form MOS transistor at described first area I, form polysilicon resistance at described second area II.In actual fabrication of semiconductor device, described Semiconductor substrate 100 has one or more first area I and second area II, in the present embodiment, the second area II adjacent with described first area I with one with a first area I does exemplary illustrated, and the quantity of described first area and second area and position should too not limit the scope of the invention.
In the Semiconductor substrate 100 of described second area II, be formed with fleet plough groove isolation structure 105, described fleet plough groove isolation structure 105 is for by follow-up its surperficial polysilicon resistance and Semiconductor substrate, other device electric isolation of being formed at.In other embodiments, described fleet plough groove isolation structure is also formed at around the Semiconductor substrate of first area I, for the different MOS transistor of electric isolation.
Please refer to Fig. 7, form gate dielectric material layer 110 on described Semiconductor substrate 100 surfaces, form the first polysilicon material layer 120 on described gate dielectric material layer 110 surface, the first polysilicon material layer 120 surfaces at described second area II form layer of cover material 130, form the 3rd polysilicon material layer 140 on described the first polysilicon material layer 120 surfaces and layer of cover material 130 surfaces.
The material of described gate dielectric material layer 110 is silica or high-K gate dielectric material, and described high-K gate dielectric material is hafnium oxide (HfO
2), wherein one or more such as hafnium silicon oxide (HfSiO), hafnium silicon oxynitride (HfSiON), hafnium oxide tantalum (HfTaO), hafnium oxide titanium (HfTiO), hafnium oxide zirconium (HfZrO).In the time that the material of described gate dielectric material layer 110 is high-K gate dielectric material, the metal level forming in follow-up the first opening comprises functional material layer and is positioned at the metal gate electrode material layer on described functional material layer surface.In the time that the material of described gate dielectric material layer is silica, the follow-up metal level forming in the first opening comprises high-K gate dielectric material layer, be positioned at the functional material layer on high-K gate dielectric material layer surface and be positioned at the metal gate electrode material layer on described functional material layer surface.In the present embodiment, the material of described gate dielectric material layer 110 is silica, adopts thermal oxidation technology to be formed at Semiconductor substrate 100 surfaces.In the time that the material of described gate dielectric material layer is high-K gate dielectric material, utilize atom layer deposition process to form high-K gate dielectric material layer at described semiconductor substrate surface and surface of shallow trench isolation structure.
The material of described layer of cover material 130 is silica, silicon nitride or silicon oxynitride etc., the follow-up cover layer as polysilicon resistance surface of described layer of cover material 130, make described polysilicon resistance and external insulation, and described cover layer can also be served as the grinding barrier layer on polysilicon resistance surface, avoid follow-up chemical mechanical milling tech to cause damage to described polysilicon resistance.And by controlling the gross thickness of described the first polysilicon material layer and layer of cover material, just can control the total height of pseudo-grid structure, thereby can control the total height of metal gates.In the present embodiment, the thickness range of described the first polysilicon material layer 120 is 10 nanometer ~ 50 nanometers, and the thickness range of described layer of cover material 130 is 10 nanometer ~ 50 nanometers.
The thickness of described the 3rd polysilicon material layer 140 is greater than described layer of cover material 130, make follow-up described the 3rd polysilicon material layer 140 to be ground when stopping at layer of cover material 130 surface and forming the second polysilicon material layer the flush of described the second polysilicon material layer and layer of cover material.
In other embodiments, also can first form the second polysilicon material layer on the first polysilicon material layer surface of described first area, the first polysilicon material layer surface at described the second polysilicon material layer and second area forms layer of cover material, then forms surface contour layer of cover material and the second polysilicon material layer by cmp.
Please refer to Fig. 8, described the 3rd polysilicon material layer 140 is carried out to the 3rd cmp, until expose described cover layer 130, form the second polysilicon material layer 145, make described the second polysilicon material layer 145 and cover layer 130 flush.
Because described the 3rd chemical mechanical milling tech is using cover layer 130 as grinding stop-layer, the thickness of final described the second polysilicon material layer 145 forming is equated with the thickness of cover layer 130.And be used to form pseudo-grid structure because the first polysilicon material layer 120, the second polysilicon material layer 145 of described first area I is follow-up, therefore by controlling the formation thickness of described the first polysilicon material layer 120 and cover layer 130, just the height of pseudo-grid structure can be controlled, thereby the height of the metal gates of final formation can be controlled.
Please refer to Fig. 9, please refer to Fig. 8 at described the second polysilicon material layer 145() and layer of cover material 130(please refer to Fig. 8) surface form the first mask layer 150, take described the first mask layer 150 as mask, to described the second polysilicon material layer 145, layer of cover material 130, the first polysilicon material layer 120(please refer to Fig. 8), gate dielectric material layer 110(please refer to Fig. 8) carry out etching, formation is positioned at the pseudo-grid structure 160 on Semiconductor substrate 100 I surfaces, first area, be positioned at polysilicon resistance 170 and the cover layer 135 that is positioned at described polysilicon resistance 170 surfaces on fleet plough groove isolation structure 105.
The material of described the first mask layer 150 is photoresist, silica, silicon nitride, silicon oxynitride etc., and the material of described the first mask layer 150 is different from the material of described layer of cover material 130.In the time that the material of described the first mask layer is not photoresist, also be included in described the first mask layer surface and form patterned photoresist layer (not shown), utilizing described patterned photoresist layer is mask, described the first mask layer is carried out to etching, then remove described patterned photoresist layer, take described the first mask layer as mask, described the second polysilicon material layer, layer of cover material, the first polysilicon material layer, gate dielectric material layer are carried out to etching.
Described pseudo-grid structure 160 comprises gate dielectric layer 161 and polygate electrodes 162, wherein said gate dielectric layer 161 is formed by gate dielectric material layer 110 etching, and described polygate electrodes 162 is formed by the second polysilicon material layer 145 and the first polysilicon material layer 120 etchings.Described polysilicon resistance 170 is formed by the first polysilicon material layer 120 etchings, and described polysilicon resistance 170 surfaces are formed with cover layer 135.
Owing to thering is the difference in height of the second polysilicon material layer 145 thickness between described pseudo-grid structure 160 top surfaces and polysilicon resistance 170 top surfaces, and described polysilicon resistance 170 surfaces have cover layer 135 all the time, etching in follow-up formation metal gates process, grinding, depositing operation can not exert an influence to described polysilicon resistance 170, improved the reliability of polysilicon resistance 170, and described polysilicon resistance can form with the MOS transistor that grid is metal gates simultaneously.And in the time that the second Formation of silicide is before described metal gates, as long as the thickness of described the second silicide is less than the thickness of cover layer 135, the etching, grinding, the depositing operation that form in metal gates process also can not impact described the second silicide, thereby have guaranteed electric property and the reliability of the second silicide.
In the present embodiment, described the first polysilicon material layer 120 at forming process situ doped with P type or N-type foreign ion, to regulate the resistance value of polysilicon resistance of final formation.In other embodiments, also can, forming after the first polysilicon material layer, before forming layer of cover material, carry out Implantation to described the first polysilicon material layer, thus in the first polysilicon material layer impurity ion.
Forming after described pseudo-grid structure 160 or removing described the first mask layer 150 behind follow-up formation source region and drain region.
Please refer to Figure 10, form side wall 180 in described pseudo-grid structure 160 and polysilicon resistance 170 sidewalls, in the interior formation of Semiconductor substrate 100 source region 190 and the drain region 200 of described pseudo-grid structure 160 both sides.
The side wall of the side wall of described pseudo-grid structure 160 sidewalls and polysilicon resistance 170 sidewalls can synchronously form, and also can form step by step, and in the present embodiment, the side wall 180 of described pseudo-grid structure 160 and polysilicon resistance 170 sidewalls synchronously forms.Described side wall 180 is silicon oxide layer, silicon nitride layer or both laminated construction.Owing to forming the known technology that the technique of side wall is those skilled in the art, therefore not to repeat here.
In the present embodiment, the formation technique in described source region 190 and drain region 200 is: form the first groove (not shown) and the second groove (not shown) in the Semiconductor substrate 100 of described pseudo-grid structure 160 both sides, utilize selective epitaxial process in described the first groove and the second groove, to fill full germanium silicon material or carbofrax material, utilize the effect of stress of described germanium silicon material or carbofrax material increase channel region, improve the electric property of MOS transistor.And doped with foreign ion, form respectively source region 190 and drain region 200 in the germanium silicon material in described the first groove and the second groove or carbofrax material.In the present embodiment, the source region 190 that described selective epitaxial process forms and 200 surface ratio Semiconductor substrate 100 surfaces, drain region are high, between source region 190,200 surfaces, drain region and Semiconductor substrate 100 surfaces, there is difference in height, make described source region 190 corresponding with polysilicon resistance 170 surfaces with 200 surfaces, drain region, the height that is source region 190 and 200 surfaces, drain region equates or approximately equal with the height on polysilicon resistance 170 surfaces, makes follow-uply can utilize same Formation of silicide technique to form the first silicide and the second silicide.In the present embodiment, described source region 190 and drain region 200 surface ratio Semiconductor substrate 100 high 10 nanometer ~ 50 nanometers in surface, and difference in height between described source region 190,200 surfaces, drain region and polysilicon resistance 170 surfaces is 0 nanometer ~ 30 nanometer.
In other embodiments, described source region and surface, drain region also can flush with semiconductor substrate surface.
In other embodiments, the formation technique that forms described source region and drain region can also be: first in the Semiconductor substrate of described pseudo-grid structure both sides, carry out light dope Implantation, form light dope source region and lightly doped drain, form after side wall, again take described side wall and pseudo-grid structure as mask, Semiconductor substrate to described pseudo-grid structure both sides is carried out heavy doping ion injection, forms heavy doping source region and heavy doping drain region.
Please refer to Figure 11, form first medium layer 210 on described Semiconductor substrate 100 surfaces, described first medium layer 210 covers described pseudo-grid structure and cover layer, and described first medium layer is carried out to the first cmp, until expose described pseudo-grid structure 160 and cover layer 135 surfaces.The material of described first medium layer 210 is silica, low-K dielectric material or ultralow K dielectric material.
Please refer to Figure 12, remove described polygate electrodes 162(and please refer to Figure 11), form the first opening, in described the first opening, fill full metal level, described metal level is carried out to the second cmp, form metal gates 220.
The technique of removing described pseudo-grid structure 160 is dry etch process or wet-etching technology.In the present embodiment, utilize polygate electrodes 162(described in Tetramethylammonium hydroxide (TMAH) solution wet etching to please refer to Figure 11), form the first opening (not shown).
In the present embodiment, because the material of described gate dielectric material layer 110 is silica, the follow-up metal level that need to form in described the first opening comprises high-K gate dielectric material layer, functional material layer and metal gate electrode material layer.Before forming described high-K gate dielectric material layer, can remove the gate dielectric layer that described the first opening exposes, also can retain the gate dielectric layer that described the first opening exposes.In other embodiments, in the time that the material of described gate dielectric material layer is high-K gate dielectric material, the follow-up metal level forming in described the first opening only need to comprise functional material layer and metal gate electrode material layer.
In the present embodiment, described metal level comprise be positioned at the first opening inner wall surface high-K gate dielectric material layer, be positioned at the functional material layer on described high-K gate dielectric material layer surface and be positioned at the metal gate electrode material layer on described functional material layer surface.The material of described high-K gate dielectric material layer is hafnium oxide (HfO
2), wherein one or more such as hafnium silicon oxide (HfSiO), hafnium silicon oxynitride (HfSiON), hafnium oxide tantalum (HfTaO), hafnium oxide titanium (HfTiO), hafnium oxide zirconium (HfZrO), the material of described functional material layer be Ti, Ta, TiN, TaN, TiAl, TaC, TaSiN wherein one or more, the material of described metal gate electrode material layer be Al, Cu, Ag, Au, Pt, Ni wherein one or more.Described functional material layer not only can be used as the diffusion impervious layer of metal gate electrode material layer, be used for the diffusion of the material of barrier metal layer of gate electrode material, the work function of grid structure can also be regulated, the work function of the grid structure of described MOS transistor can be changed by adjusting the material of described functional material layer and thickness.
When described high-K gate dielectric material layer, functional material layer, metal gate electrode material layer are filled after completely described the first opening completely, described metal level is carried out to the second cmp, until stop at described first medium layer 210 and cover layer 135 surfaces, in described the first opening, form metal gates 220, described metal gates 220 comprises the high-K gate dielectric layer 221 that is positioned at described the first opening inner wall surface, is positioned at the functional layer 222 and the metal gate electrode 223 that is positioned at described functional layer 222 surfaces on described high-K gate dielectric layer 221 surfaces.
Please refer to Figure 13, form the second mask layer 230 on described first medium layer 210, metal gates 220 and cover layer 135 surfaces, take described the second mask layer 230 as mask, described first medium layer 210 and cover layer 135 are carried out to etching, form the second opening 240 in described source region 190 and 200 surfaces, drain region, form the 3rd opening 350 on the surface at described polysilicon resistance 170 two ends.
The material of described the second mask layer 230 is photoresist, silica, silicon nitride, silicon oxynitride, low-K dielectric material one or multiple-level stack structure wherein, described the second mask layer 230 not only forms the mask layer of the second opening, the 3rd opening as etching, in the time forming the first silicide and the second silicide, described the second mask layer covers the surface of described metal gates, avoid, in the process that forms silicide, described metal gates is caused to damage, affect the electric property of metal gates.
In the present embodiment, because the height on described source region and surface, drain region is corresponding with the height on polysilicon resistance surface, make to utilize an etching technics just to form the second opening and the 3rd opening simultaneously, and described the second opening is in exposing source region and surface, drain region, described the 3rd opening and exposing polysilicon resistance surface, can not carry out too much etching to source region, drain region or polysilicon resistance, thereby can not affect the electric property of semiconductor structure.
In other embodiments, can also carry out respectively etching to the cover layer on the interlayer dielectric layer on source region and surface, drain region and polysilicon resistance surface, utilize twice etching technique to form the second opening and the 3rd opening.
Please refer to Figure 14, the source region 190 exposing at described the second opening 240 and 200 surfaces, drain region form the first silicide 245, and polysilicon resistance 170 surfaces that expose at described the 3rd opening 250 form the second silicide 255.
The material of described the first silicide 245 and the second silicide 255 is one or more the combination in nickle silicide, titanium silicide, tungsten silicide, cobalt silicide, silication lead, platinum silicide.In the present embodiment, the material of described the first silicide 245 and the second silicide 255 is nickle silicide, and described the first silicide 245 and the second silicide 255 adopt same Formation of silicide step to form.The concrete technology that forms described the first silicide 245 and the second silicide 255 comprises: at described the second mask layer 230 surface and the second openings 240, the 3rd opening 250 inner wall surface form nickel metal layer, described nickel metal layer is carried out to high annealing, described nickel metal layer and source region, the silicon on drain region and the polysilicon resistance surface formation metal silicide that reacts, then utilize wet-etching technology to remove unreacted nickel metal layer, the source region 190 exposing at described the second opening 240 and 200 surfaces, drain region form the first silicide 245, polysilicon resistance 170 surfaces that expose at described the 3rd opening 250 form the second silicide 255.
Because described metal silicide is nickle silicide, the nickle silicide of formation is carried out to high annealing again can cause resistance to increase, electric property variation, and existing technique will inevitably experience high-temperature process while forming high-K gate dielectric material layer, therefore the technique that in the present embodiment, forms described the first silicide 245 and the second silicide 255 must be carried out after described formation metal gates.
In other embodiments, when the material of described gate dielectric material layer is high K dielectric material, when the metal level of follow-up formation does not comprise high-K gate dielectric material layer, described the first silicide and the second silicide can also form before forming metal gates.While formation before described the first silicide and the second silicide are forming metal gates, forming described polysilicon resistance, after source region and drain region, cover layer to described polysilicon resistance two end surfaces carries out etching, until expose the surface at described polysilicon resistance two ends, in described source region, surface, drain region, pseudo-grid body structure surface, the surface at cover surface and the polysilicon resistance two ends that expose forms nickel metal layer, described nickel metal layer is carried out to high annealing, utilize wet etching to remove unreacted nickel metal layer, form the first silicide in described source region and surface, drain region, surface at the described polysilicon resistance two ends that expose forms the second silicide.In the time that the thickness of described the second silicide is less than described tectal thickness, even if first form described the second silicide, owing to having cover layer as grinding barrier layer, the grinding technics in follow-up formation metal gates process also can not cause harmful effect to described the second silicide.
Form after the first silicide and the second silicide, can remove described the second mask layer, also can not remove described the second mask layer, described the second mask layer and first medium layer are as a part for interlayer dielectric layer.
Follow-up, be also included on described source region, drain region, metal gates and polysilicon resistance and form conductive plunger, described MOS transistor and polysilicon resistance are electrically connected with external circuit.
According to above-mentioned formation method, the embodiment of the present invention also provides a kind of semiconductor structure, please refer to Figure 14, comprising: Semiconductor substrate 100, described Semiconductor substrate 100 comprises first area I and second area II, in the second area II of described Semiconductor substrate, has fleet plough groove isolation structure 105; Be positioned at the MOS transistor on described Semiconductor substrate 100 I surfaces, first area, described MOS transistor comprises the metal gates 220 that is positioned at Semiconductor substrate 100 surfaces and source region 190 and the drain region 200 that is positioned at the Semiconductor substrate 100 of described metal gates 220 both sides; Be positioned at the polysilicon resistance 170 on described fleet plough groove isolation structure 105, be positioned at the cover layer 135 on described polysilicon resistance 170 surfaces, described polysilicon resistance 170 surfaces have difference in height with metal gates 220 surfaces, described cover layer 135 surfaces and metal gates flush; Cover the first medium layer 210 of described Semiconductor substrate 100, and the surface of described first medium layer 210 and metal gates 220, cover layer 135 flush; Be positioned at second mask layer 230 on described first medium layer 210 surface; Run through described the second mask layer 230, first medium layer 210 and be positioned at described source region 190 and second opening 240 on 200 surfaces, drain region, first silicide 245 on the source region 190 of coming out described in being positioned at and 200 surfaces, drain region; Run through described the second mask layer 230, cover layer 135 and be positioned at the 3rd surperficial opening 250 at described polysilicon resistance 170 two ends, be positioned at the second surperficial silicide 255 at described polysilicon resistance 170 two ends.
Because the polysilicon material layer that forms described pseudo-grid structure comprises the first polysilicon material layer and the second polysilicon material layer, and the polysilicon material layer that forms described polysilicon resistance is only the first polysilicon material layer, make described pseudo-grid body structure surface and polysilicon resistance surface there is difference in height, form the chemical mechanical milling tech of metal gates and can not impact the metal silicide on polysilicon resistance surface, making described grid is that MOS transistor and the polysilicon resistance of metal gate can form simultaneously.
Although the present invention with preferred embodiment openly as above; but it is not for limiting the present invention; any those skilled in the art without departing from the spirit and scope of the present invention; can utilize method and the technology contents of above-mentioned announcement to make possible variation and modification to technical solution of the present invention; therefore; every content that does not depart from technical solution of the present invention; any simple modification, equivalent variations and the modification above embodiment done according to technical spirit of the present invention, all belong to the protection range of technical solution of the present invention.
Claims (15)
1. a formation method for semiconductor structure, is characterized in that, comprising:
Semiconductor substrate is provided, and described Semiconductor substrate comprises first area and second area, forms fleet plough groove isolation structure at the second area of described Semiconductor substrate;
Form gate dielectric material layer in described Semiconductor substrate and surface of shallow trench isolation structure, form the first polysilicon material layer on described gate dielectric material layer surface, the first polysilicon material layer surface at described second area forms layer of cover material, the first polysilicon material layer surface in described first area forms the second polysilicon material layer, described the second polysilicon material layer and layer of cover material flush;
Form the first mask layer on described the second polysilicon material layer, layer of cover material surface, take described the first mask layer as mask, described the second polysilicon material layer, layer of cover material, the first polysilicon material layer, gate dielectric material layer are carried out to etching, form be positioned at surface, Semiconductor substrate first area pseudo-grid structure, be positioned at the polysilicon resistance on fleet plough groove isolation structure and be positioned at the cover layer on described polysilicon resistance surface;
In the Semiconductor substrate of described pseudo-grid structure both sides, form source region and drain region;
Form the first silicide in described source region and surface, drain region;
Etched portions cover layer, forms the second silicide on the surface at described polysilicon resistance two ends;
Form first medium layer at described semiconductor substrate surface, described first medium layer covers described pseudo-grid structure and cover layer, described first medium layer is carried out to the first cmp, until expose described pseudo-grid structure and cover surface;
Remove described pseudo-grid structure, form the first opening, in described the first opening, fill full metal level, described metal level is carried out to the second cmp, form metal gates.
2. the formation method of semiconductor structure as claimed in claim 1, it is characterized in that, in the time that described gate dielectric material layer is silicon oxide layer, described metal level comprises high-K gate dielectric material layer, be positioned at the functional material layer on high-K gate dielectric material layer surface and be positioned at the metal gate electrode material layer on described functional material layer surface, and the technique that forms described the first silicide, the second silicide is carried out after forming metal gates.
3. the formation method of semiconductor structure as claimed in claim 1, it is characterized in that, in the time that described gate dielectric material layer is high-K gate dielectric material layer, described metal level comprises functional material layer and the metal gate electrode material layer that is positioned at described functional material layer surface, and the technique that forms described the first silicide, the second silicide was carried out or carries out after forming metal gates before forming metal gates.
4. the formation method of semiconductor structure as claimed in claim 2 or claim 3, it is characterized in that, when forming described the first silicide, when the technique of the second silicide is carried out after forming described metal gates, form described the first silicide, the concrete technology of the second silicide comprises: at described first medium layer, metal gates and cover surface form the second mask layer, take described the second mask layer as mask, described first medium layer and cover layer are carried out to etching, in described source region, surface, drain region forms the second opening, surface at described polysilicon resistance two ends forms the 3rd opening, the source region exposing at the second opening and surface, drain region form the first silicide, the surface at the polysilicon resistance two ends that expose at the 3rd opening forms the second silicide.
5. the formation method of semiconductor structure as claimed in claim 4, is characterized in that, described the second opening, the 3rd opening adopt same etch step to form, and described the first silicide, the second silicide adopt same Formation of silicide step to form.
6. the formation method of semiconductor structure as claimed in claim 3, it is characterized in that, when forming described the first silicide, when the technique of the second silicide was carried out before forming described metal gates, form described the first silicide, the concrete technology of the second silicide comprises: form described polysilicon resistance, after source region and drain region, cover layer to described polysilicon resistance two end surfaces carries out etching, until expose the surface at described polysilicon resistance two ends, form the first silicide in described source region and surface, drain region, surface at the described polysilicon resistance two ends that expose forms the second silicide.
7. the formation method of semiconductor structure as claimed in claim 6, is characterized in that, described the first silicide, the second silicide adopt same Formation of silicide step to form.
8. the formation method of semiconductor structure as claimed in claim 1, is characterized in that, the height on described source region, surface, drain region is corresponding with the height on polysilicon resistance surface.
9. the formation method of semiconductor structure as claimed in claim 8, is characterized in that, the difference in height between described source region, surface, drain region and polysilicon resistance surface is 0 nanometer ~ 30 nanometer.
10. the formation method of semiconductor structure as claimed in claim 1, is characterized in that, described source region, high 10 nanometer ~ 50 nanometers of drain region surface ratio semiconductor substrate surface.
The formation method of 11. semiconductor structures as claimed in claim 1, is characterized in that, the thickness range of described the first polysilicon material layer is 10 nanometer ~ 50 nanometers.
The formation method of 12. semiconductor structures as claimed in claim 1, is characterized in that, described tectal thickness range is 10 nanometer ~ 50 nanometers.
The formation method of 13. semiconductor structures as claimed in claim 8, it is characterized in that, the technique that forms described source region, drain region comprises: in the Semiconductor substrate of described pseudo-grid structure both sides, form the first groove and the second groove, utilize selective epitaxial process in described the first groove and the second groove, to fill full germanium silicon material and carbofrax material, form source region and drain region, the surface in described source region and drain region is higher than semiconductor substrate surface.
The formation method of 14. semiconductor structures as claimed in claim 1, is characterized in that, described tectal material is silica, silicon nitride or silicon oxynitride.
15. 1 kinds of semiconductor structures, described semiconductor structure comprises MOS transistor and polysilicon resistance, it is characterized in that, described semiconductor structure adopts the formation method of the semiconductor structure described in any one in claim 1 to 14 to form.
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