CN103811319A - High k metal grid forming method - Google Patents
High k metal grid forming method Download PDFInfo
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- CN103811319A CN103811319A CN201210445689.XA CN201210445689A CN103811319A CN 103811319 A CN103811319 A CN 103811319A CN 201210445689 A CN201210445689 A CN 201210445689A CN 103811319 A CN103811319 A CN 103811319A
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- 238000000034 method Methods 0.000 title claims abstract description 75
- 229910052751 metal Inorganic materials 0.000 title claims abstract description 65
- 239000002184 metal Substances 0.000 title claims abstract description 65
- 239000004065 semiconductor Substances 0.000 claims abstract description 37
- 239000000758 substrate Substances 0.000 claims abstract description 29
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims abstract description 13
- 229910052799 carbon Inorganic materials 0.000 claims abstract description 13
- 238000006243 chemical reaction Methods 0.000 claims abstract description 12
- 229910003074 TiCl4 Inorganic materials 0.000 claims description 28
- 239000007789 gas Substances 0.000 claims description 28
- XJDNKRIXUMDJCW-UHFFFAOYSA-J titanium tetrachloride Chemical compound Cl[Ti](Cl)(Cl)Cl XJDNKRIXUMDJCW-UHFFFAOYSA-J 0.000 claims description 28
- 230000015572 biosynthetic process Effects 0.000 claims description 25
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 19
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 claims description 16
- 229910052757 nitrogen Inorganic materials 0.000 claims description 9
- 229910052786 argon Inorganic materials 0.000 claims description 8
- 239000006227 byproduct Substances 0.000 claims description 5
- 238000005516 engineering process Methods 0.000 abstract description 6
- 239000013078 crystal Substances 0.000 abstract description 3
- 239000010410 layer Substances 0.000 description 27
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 16
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 14
- 238000000231 atomic layer deposition Methods 0.000 description 10
- 238000002347 injection Methods 0.000 description 6
- 239000007924 injection Substances 0.000 description 6
- 238000002955 isolation Methods 0.000 description 6
- 238000004519 manufacturing process Methods 0.000 description 5
- 238000004140 cleaning Methods 0.000 description 4
- 239000000126 substance Substances 0.000 description 4
- 238000010276 construction Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 238000010521 absorption reaction Methods 0.000 description 1
- 238000005452 bending Methods 0.000 description 1
- 239000007795 chemical reaction product Substances 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- NHDHVHZZCFYRSB-UHFFFAOYSA-N pyriproxyfen Chemical compound C=1C=CC=NC=1OC(C)COC(C=C1)=CC=C1OC1=CC=CC=C1 NHDHVHZZCFYRSB-UHFFFAOYSA-N 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000002210 silicon-based material Substances 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28088—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being a composite, e.g. TiN
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
- H01L21/28556—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD
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- Computer Hardware Design (AREA)
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- Power Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Chemical & Material Sciences (AREA)
- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
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- Insulated Gate Type Field-Effect Transistor (AREA)
- Electrodes Of Semiconductors (AREA)
- Chemical Vapour Deposition (AREA)
Abstract
The invention provides a high k metal grid forming method, and relates to the semiconductor technical field; the high k metal grid forming method comprises the following steps: S101, providing a semiconductor substrate provided with a high k dielectric layer in a reaction chamber; step 102, employing ALD technology to form a metal film on the high k dielectric layer; S103, carrying out carbon doping treatment on the metal film. The high k metal grid forming method carries out carbon doping treatment to the formed metal film used for making the metal grid, thereby reducing crystal grain size of the metal grid, reducing threshold-voltage change and improving semiconductor device performance.
Description
Technical field
The present invention relates to technical field of semiconductors, in particular to a kind of method that forms high-k/metal gate.
Background technology
High-K metal grid (HKMG) technology is the important technology of semiconductor applications.In the prior art, high-K metal grid generally comprises the laminated construction of high k dielectric layer and metal gates formation.In the laminated construction of high k dielectric layer and metal gates formation, except random doping fluctuation (random dopant fluctuations, RDF) cause threshold voltage variation (thresholdvoltage variability, TVV), outside, the crystal structure of metal gates and grain size (crystallite dimension) are also one of major reasons causing threshold voltage variation.
In high-k/metal gate technique, titanium nitride (TiN) and tantalum nitride (TaN) are by widely as metal gates.Due to the metal gates forming there is good homogeneity and damage that high k dielectric layer is brought less, ALD(atomic layer deposition, ald) be widely used in the manufacturing process of metal gates.But traditional ALD process, possesses hardly and improve the grain size of metal gates and the adjustment node of crystal structure that form, the crystallite dimension of the metal gates of formation is often very large and cannot adjust.
In the prior art, application ALD technique forms the method (being example take metal gates as TiN) of metal gates, general main comprising the steps:
Step e 1 a: Semiconductor substrate that is formed with high k dielectric layer is provided in reative cell.
Step e 2: utilize TiCl4 pulse to process this Semiconductor substrate, form one deck individual layer TiCl4 film on high k dielectric layer.
Step e 3: utilize the indoor unnecessary TiCl4 of nitrogen cleaning reaction.
Step e 4: utilize NH3 pulse to process this Semiconductor substrate.In this process, NH3 can react with TiCl4, generates TiN and HCl, and the TiN of generation is as the part of metal gates.
Step e 5: utilize the indoor unnecessary NH3 of nitrogen cleaning reaction and byproduct of reaction (such as HCl).
Step e 6: repeating step E2 to E5 many times, the metal gates of meet the demands to form (main dinger thickness degree aspect).
In the prior art, generally form metal gates by abovementioned steps E1 to E6.But, the metal gates that utilizes this existing ALD technique to form, its crystallite dimension is often very large, and cannot adjust.This feature of metal gates, will be easy to the variation of threshold voltage of the semiconductor device that causes final manufacture.
Therefore, need to propose a kind of method of new formation high-k/metal gate, the metal gates meeting the demands to form grain size, reduces threshold voltage variation, improves the performance of semiconductor device.
Summary of the invention
For the deficiencies in the prior art, the invention provides a kind of method that forms high-k/metal gate, the method comprises the steps:
Step S101: the Semiconductor substrate that is formed with high k dielectric layer is provided in reative cell;
Step S102: utilize ALD technique to form metallic film on described high k dielectric layer;
Step S103: described metallic film is carried out to carbon doping treatment.
Wherein, described step S102 comprises:
Step S1021: utilize TiCl4 pulse or TaCl4 pulse to process described Semiconductor substrate;
Step S1022: remove unnecessary described TiCl4 or TaCl4 in described reative cell;
Step S1023: utilize NH3 pulse to process described Semiconductor substrate, described NH3 is reacted with described TiCl4 or TaCl4, to form metallic film on described high k dielectric layer;
Step S1024: remove unnecessary described NH3 and byproduct of reaction in described reative cell.
Wherein, in described step S102, the duration of described TiCl4 pulse or TaCl4 pulse and described NH3 pulse is 0.01 ~ 10 second.
Wherein, in described step S102, the gas flow rate of described TiCl4 pulse or TaCl4 pulse and described NH3 pulse is 1 ~ 300sccm.
Wherein, the method for removing the method for described TiCl4 unnecessary in described reative cell or TaCl4 and remove described NH3 unnecessary in described reative cell and byproduct of reaction in described step S1022 in described step S1024 is: in described reative cell, pass into nitrogen or argon gas.
Wherein, the gas flow rate of described nitrogen or argon gas is 1 ~ 300sccm.
Wherein, the duration that passes into described nitrogen or argon gas is 0.1 ~ 10 second.
Wherein, in described step S102, after described step S1024, also comprise step S1025: repeat described step S1021 to described step S1024 at least one times.
Wherein, in described step S102, repeat described step S1021 to the number of times of described step S1024 be 1 ~ 100 time, be preferably 1 ~ 30 time.
Wherein, in described step S103, the method for described metallic film being carried out to carbon doping treatment is: utilize metallic film described in C2H4 burst process.
Wherein, it is characterized in that, after described step S103, also comprise step S104: repeat described step S102 and step S103 at least one times.
Wherein, the temperature of described reative cell is 300 ~ 700 ℃.
The method of the formation high-k/metal gate of the embodiment of the present invention, by the metallic film (such as TiN film or TaN film) for making metal gates forming is carried out to carbon doping treatment, reduce the crystallite dimension of metal gates, reduce threshold voltage variation, improved the performance of semiconductor device.
Accompanying drawing explanation
Following accompanying drawing of the present invention is used for understanding the present invention in this as a part of the present invention.Shown in the drawings of embodiments of the invention and description thereof, be used for explaining principle of the present invention.
In accompanying drawing:
Fig. 1 is the flow chart of a kind of method that forms high-k/metal gate of embodiment of the present invention proposition.
Embodiment
In the following description, a large amount of concrete details have been provided to more thorough understanding of the invention is provided.But, it is obvious to the skilled person that the present invention can be implemented without one or more these details.In other example, for fear of obscuring with the present invention, be not described for technical characterictics more well known in the art.
Should be understood that, the present invention can be with multi-form enforcement, and should not be interpreted as the embodiment that is confined to propose here.On the contrary, provide these embodiment to expose thorough and complete, and scope of the present invention is fully passed to those skilled in the art.In the accompanying drawings, for clear, the size in Ceng He district and relative size may be exaggerated.Same reference numerals represents identical element from start to finish.
Be understood that, when element or layer be called as " ... on ", " with ... adjacent ", " being connected to " or " being coupled to " other element or when layer, its can be directly on other element or layer, with it adjacent, connect or be coupled to other element or layer, or can there is element or layer between two parties.On the contrary, when element be called as " directly exist ... on ", when " with ... direct neighbor ", " being directly connected to " or " being directly coupled to " other element or layer, there is not element or layer between two parties.Although it should be understood that and can use term first, second, third, etc. to describe various elements, parts, district, floor and/or part, these elements, parts, district, floor and/or part should not limited by these terms.These terms are only used for distinguishing an element, parts, district, floor or part and another element, parts, district, floor or part.Therefore, do not departing under the present invention's instruction, the first element discussed below, parts, district, floor or part can be expressed as the second element, parts, district, floor or part.
Spatial relationship term for example " ... under ", " ... below ", " below ", " ... under ", " ... on ", " above " etc., thereby can be used for convenience of description the relation of element shown in description figure or feature and other element or feature here.It should be understood that except the orientation shown in figure, spatial relationship term intention also comprise use and operate in the different orientation of device.For example, if the device in accompanying drawing upset, then, be described as " below other element " or " under it " or " under it " element or feature will be oriented to other element or feature " on ".Therefore, exemplary term " ... below " and " ... under " can comprise upper and lower two orientations.Device can additionally be orientated (90-degree rotation or other orientation) and as used herein spatial description language correspondingly explained.
The object of term is only to describe specific embodiment and not as restriction of the present invention as used herein.In the time that this uses, " one " of singulative, " one " and " described/to be somebody's turn to do " also intention comprise plural form, unless the other mode of pointing out known in context.It is also to be understood that term " composition " and/or " comprising ", in the time using in these specifications, determine the existence of described feature, integer, step, operation, element and/or parts, but do not get rid of one or more other existence or the interpolations of feature, integer, step, operation, element, parts and/or group.In the time that this uses, term "and/or" comprises any and all combinations of relevant Listed Items.
Here with reference to the cross-sectional view of the schematic diagram as desirable embodiment of the present invention (and intermediate structure), inventive embodiment is described.Like this, can expect due to for example manufacturing technology and/or tolerance cause from shown in the variation of shape.Therefore, embodiments of the invention should not be confined to the given shape in district shown here, but comprise owing to for example manufacturing the form variations causing.For example, the Qi edge, injection region that is shown as rectangle has round or bending features and/or implantation concentration gradient conventionally, rather than binary from injection region to non-injection regions changes.Equally, when the disposal area forming by injection can cause this disposal area and injection to be carried out some injections in the district between the surface of process.Therefore, the district showing in figure is in fact schematically, their shape be not intended display device district true form and be not intended to limit scope of the present invention.
Unless otherwise defined, all terms (comprising technology and scientific terminology) have the identical implication of conventionally understanding with the those of ordinary skill in field of the present invention as used herein.Also will understand, in dictionary such as common use, defined term should be understood to have the implication consistent with they implications in the environment of association area and/or these specifications, and can not explaining in desirable or excessively formal meaning, unless definition so expressly here.
In order thoroughly to understand the present invention, will detailed step and detailed structure be proposed in following description, so that the method for the formation high-k/metal gate that explaination the present invention proposes.Preferred embodiment of the present invention is described in detail as follows, but except these are described in detail, the present invention can also have other execution modes.
The detailed step of an illustrative methods of the method for the formation high-k/metal gate of the present invention's proposition is described with reference to Fig. 1 below.Wherein, Fig. 1 is the flow chart of a kind of method that forms high-k/metal gate of embodiment of the present invention proposition.
The method of the formation high-k/metal gate that the embodiment of the present invention provides, has applied the improved ALD technique that is different from prior art, specifically comprises the steps:
Step 1, in reative cell, provide the Semiconductor substrate that is formed with high k dielectric layer.
Wherein, the reative cell using, can be identical with the reaction chamber structure that carries out in prior art using when ALD processes, and also can on existing reative cell, carry out as required certain improvement, such as increasing new air inlet pipe etc.For a person skilled in the art, can select according to specific needs easily suitable reative cell, therefore repeat no more the concrete structure of reative cell.
Preferably, in whole technical process, the temperature of reative cell is controlled at 300 ~ 700 ℃.
About described Semiconductor substrate, can be the Semiconductor substrate of gate first technique, can be also the Semiconductor substrate of gate last technique, only need in this Semiconductor substrate, to there is high k dielectric layer and the state in metal gates to be formed.About high k dielectric layer, it can select suitable material to realize according to any means of the prior art, does not limit at this.
The Semiconductor substrate providing in this step, can also comprise the structures such as source electrode, drain electrode, gate lateral wall, does not limit at this.
As example, in the present embodiment, described Semiconductor substrate selects single crystal silicon material to form.In described Semiconductor substrate, be formed with isolation structure, described isolation structure be shallow trench isolation from (STI) structure or selective oxidation silicon (LOCOS) isolation structure, Semiconductor substrate is divided into nmos area and PMOS district by described isolation structure.In described Semiconductor substrate, to be also formed with various traps (well) structure, in order simplifying, in diagram, to be omitted.The processing step of above-mentioned formation trap (well) structure, isolation structure, grid structure, by those skilled in the art are had the knack of, is described no longer in detail at this.
Step 2, utilize TiCl4 or TaCl4 pulse to process described Semiconductor substrate.Through TiCl4 or TaCl4 burst process, TiCl4 film or the TaCl4 film of meeting absorption monolayer on high k dielectric layer.
Wherein, in embodiments of the present invention, TiCl4 pulse, refers to the TiCl4 gas passing in reative cell; Certainly,, pass into TiCl4 gas in reative cell in, also can make the pulse generator (such as RF generator) in reative cell produce pulse simultaneously.The principle of TaCl4 pulse and NH3 pulse is identical therewith, follow-up repeating no more.
Preferably, the duration of TiCl4 or TaCl4 pulse is 0.01 ~ 10 second (S).
Wherein, the gas flow rate of TiCl4 or TaCl4 pulse is 1 ~ 300sccm.
Step 3: utilize unnecessary TiCl4 or TaCl4 in gas clean-up reative cell.
Particularly, in reative cell, pass into certain gas, by the indoor unnecessary TiCl4 of air-flow cleaning reaction or TaCl4.The gas adopting, is preferably nitrogen (N2), argon gas (Ar) or other gas not reacting with Semiconductor substrate.
Preferably, pass into gas remove process time be 0.1 ~ 10 second (S).
Step 4: utilizing NH3 pulse to process on the high k dielectric layer of Semiconductor substrate and form individual layer TiN or TaN metallic film this Semiconductor substrate, particularly, is TiN film or TaN film.This metallic film is for making metal gates.
Preferably, the duration of NH3 pulse is 0.01 ~ 10 second (S).
Wherein, the gas flow rate of NH3 pulse is 1 ~ 300sccm.
When select TiCl4 pulse in step 2 time, in this step, NH3 can react with TiCl4, generates individual layer TiN film and HCl accessory substance, and this TiN film is as the part of metal gates.
When select TaCl4 pulse in step 2 time, in this step, NH3 can react with TaCl4, generates individual layer TaN film and HCl accessory substance, and the TaCl4 film of aforesaid individual layer becomes TaN film, and this TaN film is as the part of metal gates.
Step 5: utilize unnecessary NH3 and accessory substance (as HCl) in gas clean-up reative cell.
Particularly, in reative cell, pass into certain gas, by the indoor unnecessary accessory substance such as NH3 and HCl of air-flow cleaning reaction.The gas adopting, is preferably nitrogen, argon gas or other gas not reacting with Semiconductor substrate.
Preferably, pass into gas remove process time be 0.1 ~ 10 second (S).
Wherein, above-mentioned steps 2 to step 5 is the process that forms metallic film by ALD technique.In the present embodiment, be with the difference of prior art, the reaction condition such as gas flow rate, duration is optimized
Step 6: repeated execution of steps 2, to the certain number of times of step 5, forms certain thickness metallic film, i.e. TiN film or TaN film.
Wherein, in step 6, repeated execution of steps 2 to the number of times of step 5 can be 0 time, in whole step 2 to step 6, execution step 2 is to step 5 totally 1 time.
Preferably, in whole step 2, to step 6, repeated execution of steps 2 to the number of times of step 5 is 1 ~ 30 time.
Step 7: to described Semiconductor substrate, particularly, refer to described certain thickness TiN film or TaN film, carry out carbon doping treatment.
The method of in this step, carrying out carbon doping treatment can be: utilize C2H4 pulse to process the metallic film in described Semiconductor substrate (specifically referring to TiN film or TaN film).Because C2H4 can be decomposed to form C and H2, C is adsorbed on the TiN film that forms in abovementioned steps or the surface of TaN film.Therefore can complete the carbon doping of the metallic film to Semiconductor substrate.
Preferably, the duration of C2H4 pulse is 0.01 ~ 10 second (S).
Wherein, the gas flow rate of C2H4 pulse is 1 ~ 300sccm.
In the present embodiment, carry out after carbon doping, can reduce the crystallite dimension of metallic film (TiN film or TaN film).Thereby can be by suitable adjusting process condition, formation grain size meets the metal gates of device performance requirement, reduces threshold voltage variation, and then improves device performance.
Step 8: repeated execution of steps 2 is to step 7, until form the metallic film meeting the demands.
Because process step 2 is to step 7, the thickness of the metallic film of formation (TiN film or TaN film) often can't meet the requirement of making metal gates, therefore, needs repeated execution of steps 2 to step 7, until form the metallic film that meets thickness requirement.
So far, completed the introduction of the method for the exemplary formation high-k/metal gate of the embodiment of the present invention.In embodiments of the present invention, after completing steps 8, also may comprise the step of metallic film being carried out to CMP processing, form metal gates to remove unnecessary metal.
The method of the formation high-k/metal gate of the embodiment of the present invention, by the metallic film (such as TiN film or TaN film) for making metal gates forming is carried out to carbon doping treatment, reduce the crystallite dimension of metal gates, reduce threshold voltage variation, improved the performance of semiconductor device.
With reference to Fig. 1, wherein show the flow chart of a kind of typical method in the method for formation high-k/metal gate that the present invention proposes, for schematically illustrating the flow process of whole manufacturing process.The method specifically comprises:
Step S101: the Semiconductor substrate that is formed with high k dielectric layer is provided in reative cell;
Step S102: utilize ALD technique to form metallic film on described high k dielectric layer;
Step S103: described metallic film is carried out to carbon doping treatment.
The present invention is illustrated by above-described embodiment, but should be understood that, above-described embodiment is the object for giving an example and illustrating just, but not is intended to the present invention to be limited in described scope of embodiments.In addition it will be appreciated by persons skilled in the art that the present invention is not limited to above-described embodiment, can also make more kinds of variants and modifications according to instruction of the present invention, these variants and modifications all drop in the present invention's scope required for protection.Protection scope of the present invention is defined by the appended claims and equivalent scope thereof.
Claims (12)
1. a method that forms high-k/metal gate, is characterized in that, described method comprises:
Step S101: the Semiconductor substrate that is formed with high k dielectric layer is provided in reative cell;
Step S102: utilize ALD technique to form metallic film on described high k dielectric layer;
Step S103: described metallic film is carried out to carbon doping treatment.
2. the method for formation high-k/metal gate as claimed in claim 1, is characterized in that, described step S102 comprises:
Step S1021: utilize TiCl4 pulse or TaCl4 pulse to process described Semiconductor substrate;
Step S1022: remove unnecessary described TiCl4 or TaCl4 in described reative cell;
Step S1023: utilize NH3 pulse to process described Semiconductor substrate, described NH3 is reacted with described TiCl4 or TaCl4, to form metallic film on described high k dielectric layer;
Step S1024: remove unnecessary described NH3 and byproduct of reaction in described reative cell.
3. the method for formation high-k/metal gate as claimed in claim 2, is characterized in that, in described step S102, the duration of described TiCl4 pulse or TaCl4 pulse and described NH3 pulse is 0.01 ~ 10 second.
4. the method for formation high-k/metal gate as claimed in claim 2, is characterized in that, in described step S102, the gas flow rate of described TiCl4 pulse or TaCl4 pulse and described NH3 pulse is 1 ~ 300sccm.
5. the method for formation high-k/metal gate as claimed in claim 2, it is characterized in that, the method for removing the method for described TiCl4 unnecessary in described reative cell or TaCl4 and remove described NH3 unnecessary in described reative cell and byproduct of reaction in described step S1022 in described step S1024 is: in described reative cell, pass into nitrogen or argon gas.
6. the method for formation high-k/metal gate as claimed in claim 5, is characterized in that, the gas flow rate of described nitrogen or argon gas is 1 ~ 300sccm.
7. the method for formation high-k/metal gate as claimed in claim 5, is characterized in that, the duration that passes into described nitrogen or argon gas is 0.1 ~ 10 second.
8. the method for formation high-k/metal gate as claimed in claim 2, is characterized in that, in described step S102, also comprises step S1025 after described step S1024: repeat described step S1021 to described step S1024 at least one times.
9. the method for formation high-k/metal gate as claimed in claim 8, is characterized in that, in described step S102, repeat described step S1021 to the number of times of described step S1024 be 1 ~ 100 time.
10. the method for formation high-k/metal gate as claimed in claim 1, is characterized in that, in described step S103, the method for described metallic film being carried out to carbon doping treatment is: utilize metallic film described in C2H4 burst process.
The method of 11. formation high-k/metal gates as described in claim 1 ~ 10 any one, is characterized in that, also comprises step S104: repeat described step S102 and step S103 at least one times after described step S103.
The method of 12. formation high-k/metal gates as described in claim 1 ~ 10 any one, is characterized in that, the temperature of described reative cell is 300 ~ 700 ℃.
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| CN201210445689.XA CN103811319B (en) | 2012-11-08 | 2012-11-08 | A kind of method for forming high-k/metal gate |
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| CN201210445689.XA CN103811319B (en) | 2012-11-08 | 2012-11-08 | A kind of method for forming high-k/metal gate |
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| CN103811319A true CN103811319A (en) | 2014-05-21 |
| CN103811319B CN103811319B (en) | 2018-06-08 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110724932A (en) * | 2019-10-18 | 2020-01-24 | 长江存储科技有限责任公司 | Film layer and deposition method thereof, semiconductor structure and forming method thereof |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1738009A (en) * | 2004-08-19 | 2006-02-22 | 集成工艺系统株式会社 | Deposition method of TiN film having a multi-layer structure |
| CN1812054A (en) * | 2004-12-01 | 2006-08-02 | 三星电子株式会社 | Dual work function metal gate structure and related method of manufacture |
| CN101748373A (en) * | 2009-12-26 | 2010-06-23 | 大连理工大学 | Preparation method of Cu (C) film with high heat stability and low resistivity |
| CN102082087A (en) * | 2009-11-30 | 2011-06-01 | 海力士半导体有限公司 | Semiconductor device including carbon-containing electrode and method for fabricating the same |
-
2012
- 2012-11-08 CN CN201210445689.XA patent/CN103811319B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1738009A (en) * | 2004-08-19 | 2006-02-22 | 集成工艺系统株式会社 | Deposition method of TiN film having a multi-layer structure |
| CN1812054A (en) * | 2004-12-01 | 2006-08-02 | 三星电子株式会社 | Dual work function metal gate structure and related method of manufacture |
| CN102082087A (en) * | 2009-11-30 | 2011-06-01 | 海力士半导体有限公司 | Semiconductor device including carbon-containing electrode and method for fabricating the same |
| CN101748373A (en) * | 2009-12-26 | 2010-06-23 | 大连理工大学 | Preparation method of Cu (C) film with high heat stability and low resistivity |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110724932A (en) * | 2019-10-18 | 2020-01-24 | 长江存储科技有限责任公司 | Film layer and deposition method thereof, semiconductor structure and forming method thereof |
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