CN103809158A - SAR radar data encryption device and method based on SOC chip - Google Patents
SAR radar data encryption device and method based on SOC chip Download PDFInfo
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- G—PHYSICS
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- G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
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- G01S13/00—Systems using the reflection or reradiation of radio waves, e.g. radar systems; Analogous systems using reflection or reradiation of waves whose nature or wavelength is irrelevant or unspecified
- G01S13/88—Radar or analogous systems specially adapted for specific applications
- G01S13/89—Radar or analogous systems specially adapted for specific applications for mapping or imaging
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Abstract
The invention discloses an SAR radar data encryption device and method based on SOC chip, the device includes: an SOC chip integrating FPGAIP and MCU IP; program FLASH memory connected to FPGAIP; a configuration FLASH memory connected with the MCU IP; an RS-485 receiver connected to the FPGAIP; the first RS-485 interface is connected with the RS-485 receiver; the RS-485 transmitter is connected with the FPGA IP; the second RS-485 interface is connected with the RS-485 transmitter; the RS-232 transceiver is connected with the MCU IP; and an RS-232 interface connected to the RS-232 transceiver. The invention adopts the SOC chip integrating the FPGA IP and the MCU IP, and uses a single chip to complete all the work of data encryption, key management, interface communication and the like, thereby realizing the real-time encryption of the imaging data of the SAR radar system, simplifying the complexity of the system and effectively reducing the time and cost of system development.
Description
Technical field
The present invention relates to radar communication technical field, especially a kind of SAR radar data encryption device and method based on SOC chip.
Background technology
Synthetic-aperture radar (Synthetic Aperture Radar, be called for short SAR) is a kind of high-resolution two-dimensional imaging radar, can round-the-clock collection earth's surface information, and utilize signal processing operations to realize the instrument of high-resolution imaging.The working method of SAR is that radar is loaded on aircraft or satellite, and the static target on ground is carried out to imaging, adopt synthetic aperture principle improve orientation to resolution.Synthetic-aperture radar plays an important role at aspects such as Disaster prediction, military information scouting, topography and geomorphology mapping, resource investigations.
The development trend of SAR is mainly in the world: multi-target detection demonstration, location, motion and direction are estimated; High-resolution imaging and target identification; The ultra broadband SAR antenna with the ability that penetrates the woods, earth's surface adopts phased array, multifrequency multi polarized SAR technology; High speed Real-time digital signal processing technology.
Domestic, as far back as the initial stage eighties, Chinese Academy of Sciences electron institute is just developed into carried SAR, and carries out imaging processing by optical system.Further use numerical approach real time imagery to the nineties." 863 " were planned the late nineteen eighties, to spaceborne L-band synthetic-aperture radar project verification research, in the development that several years ago completes model machine, and carry out airborne taking a flight test, simultaneously under its promotion, many colleges and universities, as Beijing Institute of Aeronautics, South Airways, one-tenth electricity, west electricity etc., utilize the research of having carried out SAR formation method from the measured data (spaceborne and airborne) of external introduction.Can say, aspect SAR imaging, substantially catch up with the international paces that advance.
Due to the extreme importance of SAR system in Military Application; it is particularly important that thereby the encryption that makes data becomes; present stage is because complicacy and the real-time of encrypting algorithm have higher demand; and the Receiving Host in SAR system receives in radar signal; in imaging and compression process, take great amount of hardware resources; final imaging data be not mostly encrypted and be directly kept in storage host, lacking the encipherment protection to data.
And some existing solutions are to adopt two processors to complete whole work, the cryptographic calculation of one of them complete paired data, and another completes key management, other work such as interface communication, have increased hardware complexity and development time, and cost is higher.Therefore be badly in need of exploitation a kind of simple, but meet the real-time of SAR system data, while cryptographic algorithm has lot of complexity and possesses the data encryption hardware system of certain interface communication ability.
Summary of the invention
(1) technical matters that will solve
Fundamental purpose of the present invention is to provide a kind of SAR radar data encryption device based on SOC chip, carries out real-time encrypted to realize to the imaging data of SAR radar system.
(2) technical scheme
For achieving the above object, the invention provides a kind of SAR radar data encryption device based on SOC chip, this device comprises: the SOC chip of integrated FPGA IP and MCU IP; Be connected in the program FLASH storer of FPGA IP; Be connected in the configuration FLASH storer of MCU IP; Be connected in the RS-485 receiver of FPGA IP; Be connected in a RS-485 interface of RS-485 receiver; Be connected in the RS-485 transmitter of FPGA IP; Be connected in the 2nd RS-485 interface of RS-485 transmitter; Be connected in the RS-232 transceiver of MCU IP; And be connected in the RS-232 interface of RS-232 transceiver.
In such scheme, be integrated in FPGA IP and MCU IP co-ordination in SOC, wherein said FPGAIP is responsible for the reception of data stream, and key reception is communicated by letter with MCU IP, and data are real-time encrypted, and data send; Described MCU IP is responsible for communicating by letter with main control system, communicates by letter with FPGAIP, and key generates, and key injects and cipher key destruction.
In such scheme, described FPGA IP and MCU IP, by SFR (SpecialFunction Register) bus communication of MCU IP, make MCU IP FPGA IP can be used as to a peripheral hardware and conduct interviews.
In such scheme, described program FLASH storer and described configuration FLASH storer are preserved respectively the binary code of FPGA IP and MCU IP program, import to respectively in FPGA IP and MCU IP in the time that system powers on.
In such scheme, described RS-485 receiver is used for the input data of RS-485 level format to be converted to common single-ended form, thereby FPGAIP can be identified and receive.
In such scheme, the Single-end output end of described RS-485 receiver is connected with FPGA IP Data Input Interface, and differential input end is connected with a RS-485 interface.
In such scheme, described RS-485 transmitter is used for the transmitted signal of FPGA IP to be converted to RS-485 level format, and sends data storage host to.
In such scheme, the single-ended input end of described RS-485 transmitter is connected with FPGA IP data output interface, and difference output end is connected with the 2nd RS-485 interface.
In such scheme, described RS-232 transceiver has been used for the conversion of MCU IP serial ports level to PC serial ports level and PC serial ports level to MCU IP serial ports level, and it is connected with MCU end serial line interface with RS-232 interface respectively.
In such scheme, a described RS-485 interface is the physical interface that this device is connected with Radar signal receiver and data storage host with the 2nd RS-485 interface; Described RS-232 interface is the physical interface that this device is connected with main control system.
For achieving the above object, the present invention also provides a kind of SAR radar data encryption method based on SOC chip, is applied to described device, and the method comprises:
Step 1: system is after powering on, first carry out program loading work, FPGA IP and MCU IP load program separately respectively from program FLASH storer and configuration FLASH storer, and FPGAIP sends program by SFR bus to MCU IP and loads settling signal after program loads successfully;
Step 2:MCU IP receives key generated data and order from main control system;
Step 3:MCU IP completes the backward main frame of reception and sends answer signal;
Step 4:MCU IP completes the backward FPGA IP of key generation work and carries out key injection;
Step 5:FPGAIP successfully receives the backward MCU IP of key and sends answer signal;
Step 6: view data is received by FPGAIP after expressly signal being converted to common single-ended form by RS-485 receiver from RS-485 interface enters;
Step 7:FPGAIP carries out after real-time encrypted ciphertext to export to data;
Step 8: data output to data storage host through RS-485 interface after being converted to RS-485 level format by RS-485 transmitter
(3) beneficial effect
Can find out from technique scheme, the present invention has following beneficial effect:
1) the SAR radar data encryption device based on SOC chip provided by the invention, adopt the SOC chip of integrated FPGA IP and MCU IP, use single-chip to complete data encryption, key management and interface communication etc. be work all, realize and carried out real-time encrypted to the imaging data of SAR radar system, simplify system complexity, effectively reduced time and the cost of system development.
2) the SAR radar data encryption device based on SOC chip provided by the invention, data input and output level format is all RS-485, and data stream format is identical with radar host computer, can directly be serially connected between radar signal Receiving Host and data storage host, just can complete real-time encrypted to radar image data, without former SAR radar system is changed, there are higher ease for use and versatility.
3) the SAR radar data encryption device based on SOC chip provided by the invention, use a SOC chip, solve and taken into account the difficult problem that the real-time encrypted and system interface of data is communicated by letter, make the realization of whole hardware system simpler, and can meet again all functions of system and performance requirement.
Accompanying drawing explanation
Fig. 1 is the structural representation of the SAR radar data encryption device based on SOC chip provided by the invention;
Fig. 2 is the schematic diagram that Fig. 1 shown device is applied in SAR radar system;
Fig. 3 is the groundwork schematic flow sheet of Fig. 1 shown device.
Embodiment
For making the object, technical solutions and advantages of the present invention clearer, below in conjunction with specific embodiment, and with reference to accompanying drawing, the present invention is described in more detail.
Consider and need to take into account the real-time encrypted and key management of data, the work such as interface communication, this device uses the SOC chip of a integrated FPGA IP and MCU IP, because the parallel data processing power of FPGA is stronger, so FPGA IP is mainly responsible for the realization of cryptographic algorithm, and MCU has innate advantage on aspect Application of Interface and control, MCU IP is mainly responsible for the work such as key management and interface communication, complete with external control main frame and communicate by letter with FPGA IP, input and output level format is all unified for RS-485, can directly be serially connected between radar signal Receiving Host and data storage host, without former SAR radar system is changed.
As shown in Figure 1, Fig. 1 is the structural representation of the SAR radar data encryption device based on SOC chip provided by the invention, this device comprises: the SOC chip of integrated FPGA IP and MCU IP, be connected in the program FLASH storer of FPGA IP, be connected in the configuration FLASH storer of MCU IP, be connected in the RS-485 receiver of FPGA IP, be connected in a RS-485 interface of RS-485 receiver, be connected in the RS-485 transmitter of FPGA IP, be connected in the 2nd RS-485 interface of RS-485 transmitter, be connected in the RS-232 transceiver of MCU IP, be connected in the RS-232 interface of RS-232 transceiver.
Wherein, SOC chip is made up of FPGA IP and MCU IP, and in the present embodiment, FPGA IP is that the capacity of a Domestic Scientific Research institutes's independent research is the FPGA of 2000 logical blocks, and MCU IP is a 8 general MCU that designed by offshore company.FPGA IP in SOC chip and MCUIP, by SFR (the Special Function Register) bus communication of MCU IP, make MCUIP FPGAIP can be used as to a peripheral hardware and conduct interviews.Be integrated in FPGAIP and MCU IP co-ordination in SOC, wherein FPGAIP is responsible for the reception of data stream, and key reception is communicated by letter with MCUIP, and data are real-time encrypted, and data send.MCU IP is responsible for communicating by letter with main control system, communicates by letter with FPGA IP, and key generates, and key injects and cipher key destruction.
The program of MCU IP and FPGA IP is kept at respectively in configuration FLASH storer and program FLASH storer, in the time that system powers on, imports respectively in MCU IP and FPGAIP.
The program FLASH storer that is connected in FPGA IP has adopted the FLASH storer of ALTERA company, and model is EPCS4N, is connected with the configuration interface of FPGA IP.The configuration FLASH storer that is connected in MCU IP has adopted the FLASH storer of WINBOND company, and model is W25X10, is connected with the configuration interface of MCU.Program FLASH storer and configuration FLASH storer are preserved respectively the binary code of FPGA IP and MCU IP program, import to respectively in FPGA IP and MCU IP in the time that system powers on.
Be connected in the RS-485 receiver of FPGA IP for the input data of RS-485 level format are converted to common single-ended form, thereby FPGA IP can be identified and receive.RS-485 receiver has been selected the RS-485 transceiver of American TI Company, is configured to receive mode of operation, and model is SN65HVD10, and its Single-end output end is connected with FPGA IP Data Input Interface, and differential input end is connected with a RS-485 interface.
Be connected in the RS-485 transmitter of FPGA IP for the transmitted signal of FPGA IP is converted to RS-485 level format, and send data storage host to.RS-485 transmitter has been selected the RS-485 transceiver of American TI Company, is configured to send mode of operation, and model is SN65HVD10, and its single-ended input end is connected with FPGA IP data output interface, and difference output end is connected with the 2nd RS-485 interface.
The RS-232 transceiver that is connected in MCU IP is for completing the conversion of MCU IP serial ports level to PC serial ports level and PC serial ports level to MCU IP serial ports level.RS-232 transceiver has been selected the RS-232 transceiver of U.S.'s Maxim, and model is MAX3232, is connected with MCU end serial line interface with RS-232 interface.
The one RS-485 interface is this device and the physical interface that Radar signal receiver and data storage host are connected with the 2nd RS-485 interface, 9 needle interfaces of having selected China Aerospace electrical equipment company to produce, and model is J30J-9ZKWP7.RS-232 interface is the physical interface that this device is connected with main control system, 9 needle interfaces of having selected China Aerospace electrical equipment company to produce, and model is J30J-9ZJWP7.
The structural representation of the SAR radar data encryption device based on SOC chip based on shown in Fig. 1, Fig. 2 shows the schematic diagram that Fig. 1 shown device is applied in SAR radar system.The radar signal that radar signal Receiving Host receives is expressly sent to the SAR radar data encryption device based on SOC chip provided by the invention with view data, this device is under the control of outside main control system, the view data receiving is expressly encrypted, then view data ciphertext is sent to data storage host and stores.
With reference to Fig. 3, Fig. 3 is the groundwork schematic flow sheet of Fig. 1 shown device, comprises the following steps:
Step 1: system is after powering on, first carry out program loading work, FPGA IP in SOC and MCU IP load respectively program separately from two FLASH storeies, FPGA IP loads settling signal to sending program by SFR bus to MCU IP after program loads successfully, and MCU IP just can start to carry out follow-up work afterwards.
Step 2:MCU IP receives key generated data and order from main control system.
Step 3:MCU IP completes the backward main frame of reception and sends answer signal.
Step 4:MCU IP completes the backward FPGA IP of key generation work and carries out key injection.
Step 5:FPGAIP successfully receives the backward MCU IP of key and sends answer signal.
Step 6: view data is received by FPGA IP after expressly signal being converted to common single-ended form by RS-485 receiver from RS-485 interface enters.
Step 7:FPGAIP carries out after real-time encrypted ciphertext to export to data.
Step 8: data output to storage host through RS-485 interface after being converted to RS-485 level format by RS-485 transmitter.
Above-described specific embodiment; object of the present invention, technical scheme and beneficial effect are further described; institute is understood that; the foregoing is only specific embodiments of the invention; be not limited to the present invention; within the spirit and principles in the present invention all, any modification of making, be equal to replacement, improvement etc., within all should being included in protection scope of the present invention.
Claims (11)
1. the SAR radar data encryption device based on SOC chip, is characterized in that, this device comprises:
The SOC chip of integrated FPGA IP and MCU IP;
Be connected in the program FLASH storer of FPGA IP;
Be connected in the configuration FLASH storer of MCU IP;
Be connected in the RS-485 receiver of FPGA IP;
Be connected in a RS-485 interface of RS-485 receiver;
Be connected in the RS-485 transmitter of FPGA IP;
Be connected in the 2nd RS-485 interface of RS-485 transmitter;
Be connected in the RS-232 transceiver of MCU IP; And
Be connected in the RS-232 interface of RS-232 transceiver.
2. the SAR radar data encryption device based on SOC chip according to claim 1, it is characterized in that, be integrated in FPGA IP and MCU IP co-ordination in SOC, wherein said FPGAIP is responsible for the reception of data stream, key reception, communicate by letter with MCU IP, data are real-time encrypted, and data send; Described MCU IP is responsible for communicating by letter with main control system, communicates by letter with FPGA IP, and key generates, and key injects and cipher key destruction.
3. the SAR radar data encryption device based on SOC chip according to claim 2, it is characterized in that, described FPGA IP and MCU IP, by SFR (SpecialFunction Register) bus communication of MCU IP, make MCU IP FPGA IP can be used as to a peripheral hardware and conduct interviews.
4. the SAR radar data encryption device based on SOC chip according to claim 1, it is characterized in that, described program FLASH storer and described configuration FLASH storer are preserved respectively the binary code of FPGA IP and MCU IP program, import to respectively in FPGA IP and MCU IP in the time that system powers on.
5. the SAR radar data encryption device based on SOC chip according to claim 1, is characterized in that, described RS-485 receiver is used for the input data of RS-485 level format to be converted to common single-ended form, thereby FPGA IP can be identified and receive.
6. the SAR radar data encryption device based on SOC chip according to claim 1, is characterized in that, the Single-end output end of described RS-485 receiver is connected with FPGA IP Data Input Interface, and differential input end is connected with a RS-485 interface.
7. the SAR radar data encryption device based on SOC chip according to claim 1, is characterized in that, described RS-485 transmitter is used for the transmitted signal of FPGA IP to be converted to RS-485 level format, and sends data storage host to.
8. the SAR radar data encryption device based on SOC chip according to claim 1, is characterized in that, the single-ended input end of described RS-485 transmitter is connected with FPGA IP data output interface, and difference output end is connected with the 2nd RS-485 interface.
9. the SAR radar data encryption device based on SOC chip according to claim 1, it is characterized in that, described RS-232 transceiver has been used for the conversion of MCU IP serial ports level to PC serial ports level and PC serial ports level to MCU IP serial ports level, and it is connected with MCU end serial line interface with RS-232 interface respectively.
10. the SAR radar data encryption device based on SOC chip according to claim 1, is characterized in that, a described RS-485 interface is the physical interface that this device is connected with Radar signal receiver and data storage host with the 2nd RS-485 interface; Described RS-232 interface is the physical interface that this device is connected with main control system.
11. 1 kinds of SAR radar data encryption methods based on SOC chip, are applied to the device described in any one in claim 1 to 10, and the method comprises:
Step 1: system is after powering on, first carry out program loading work, FPGA IP and MCU IP load program separately respectively from program FLASH storer and configuration FLASH storer, and FPGAIP sends program by SFR bus to MCU IP and loads settling signal after program loads successfully;
Step 2:MCU IP receives key generated data and order from main control system;
Step 3:MCU IP completes the backward main frame of reception and sends answer signal;
Step 4:MCU IP completes the backward FPGA IP of key generation work and carries out key injection;
Step 5:FPGAIP successfully receives the backward MCU IP of key and sends answer signal;
Step 6: view data is received by FPGAIP after expressly signal being converted to common single-ended form by RS-485 receiver from RS-485 interface enters;
Step 7:FPGAIP carries out after real-time encrypted ciphertext to export to data;
Step 8: data output to data storage host through RS-485 interface after being converted to RS-485 level format by RS-485 transmitter.
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Application publication date: 20140521 |