CN1038006A

CN1038006A - Packets of information exchange, switching method, rules and network

Info

Publication number: CN1038006A
Application number: CN 88104246
Authority: CN
Inventors: 迈克尔·布伦丹·奥多德
Original assignee: O'DOWD RESEARCH PTY Ltd
Current assignee: O'DOWD RESEARCH PTY Ltd
Priority date: 1988-05-24
Filing date: 1988-05-24
Publication date: 1989-12-13

Abstract

Invention relates to packets of information switching technology, communications protocol network and the device of subrange or wide region.Use includes the packets of information of a fixed-length data field and memory offset field, can be at the target place by use contain minimum processor with hardware as the processing of intermediate medium realize the dress packets of information, to the block data transmission of adjacent memory and tear packets of information open.This device comprises does not have dispute packets of information interchanger, and wherein when target was busy, packets of information was modified and circulation again.Use this method and apparatus, widely, the subnet high-power and integrated communication that is exceedingly fast can be inserted in the hardware in large quantities and seldom need the intervention of processor.

Description

Packets of information exchange, switching method, rules and network

The present invention relates to be applicable to the packet switching network method of comprehensive local or wide Local Area Network (LANS or WANS), rules, exchange and node (network interface unit) relate in particular to the fundamental circuit method of no contention (Collision-free) packets of information access and have the end-to-end data transferring technique that can finish in fact in hardware.

It is usually directed to include the critical network unit, the sub-network equipment of transmission and ISO Reference Mode dialogue layer (number 3,4 and 5), it is convenient to end-to-end high-speed communication, and is that comprehensively the data transmission of (audio frequency, video, transducer/control and some terminal communication) and non real-time (facsimile, electronic funds exchange processing, computer documents transmission) in real time provides basis.Methods such as known data transmission, packets of information program, information congestion control, session establishment can be used for finishing such sub-network.

Technology of the present invention and device also can be used for some existing packet switching network to promote its advance.In some aspects, for example the present invention can be applicable between the existing network, at multiple TDM(time division multiplexing) between the time slot in the carrier, between a computer and its ancillary equipment and at multi-processor and the multiple instruction multiple data of MIMD() data between the memory cell of computer transmit.

Looked back this packets of information exchange field in the reference list of ending place of this specification, and this ISO Reference Mode has been discussed.

In the application of a kind of public communication network of circuit and exchange, the packets of information exchange provides the possibility of greater efficiency, it is that user profile (or data block) is divided into short self-routing packets of information, on network, transmit them, and reconfigure them at each target place of their each targets.Yet although having than much progress aspect calculating and the telecommunication in recent years, end-to-end (device auto levelizer) traffic rate has surpassed a little improved packet switching network.

The first cause of this deadlock is, forces software (thereby processor) useful load on node processor by the interrupt-type input-output apparatus that is included in the compiled program of packets of information in handling.The function that is comprised comprises: filling information also increases calibration control and address information; This packets of information is put into each can be reached its target and not have with other packets of information on the continuous link of contention (perhaps, if contention is arranged, just regaining from this chain); In each exchange place verification with send this information once more; The validity of this information of verification and order are carried out ordering (even be not in each exchange place, at least at the target place) if desired once more; Confirm the vicious or out-of-sequence packets of information that each control information and requirement retransfer and miss; Retransfer omit or vicious packets of information and they are arranged on the position; Take out these data so that rebulid this raw information.End to end communication is not only slowly, and the capacity that means node processor is to providing the advanced directed facility of user, for example to being used for the rules conversion of different device, the multichannel dialog box, encrypt and for strengthen ' dumb ' (dumb) equipment of terminal and digital telephone be inapplicable.

The problem that integrates is, if any link or destination node are temporarily crowded and packets of information must be abolished or in order to transmit than slower times and to get rid of, then for the packets of information management of node processor, get rid of the burden that has increased queue management.Audio data is intrinsic field and does not allow to postpone, but can regulate the little percentage loss at random of packets of information.Computer data allows to postpone, and the loss meeting of a packets of information comprises the transmission again of many out of Memory, thereby has increased the weight of congested problem.Other data, control information in the time of strictly according to the facts just can not allow significantly to postpone or do not allow the packets of information loss, and like this, packets of information can not be abolished indiscriminately in integrated system.

In existing compunication, seeking the Different Strategies of these problems.Very large packets of information makes that might reduce (as in SNA) packets of information gives the effect of the accumulation of putting processing, but still uses such packets of information up to now, has lost the advance of packets of information exchange.Transmit the use of rules (as in ARPARNET and SNA) by point-to-point/storage, can be reduced in the burden of this target place and the end-to-end error checking that transmits again, but, if especially all packets of information of data block or information are in each intermediate point rearrangement, the complex situations of all processors can greatly increase.On the other hand, in a kind of simple end-to-end data, services (as in DECNET), this end one point processor can be used to do nearly all work, packets of information does not need to transmit according to the order of sequence in this data, services, can abolish (for example Congestion Control), can be overlapping or can circulate in network internal.These are not applicable to the processing of audio frequency bag, and, except that SNA, do not relate to dialogue layer communication.All these allows long or adjustable length packets of information, thereby stands the long stand-by period.

TDM generally is used for multi-path digital audio frequency channel, and it can provide, and short packets of information postpones, no contention access and order are preserved, and it can be applicable to recommended comprehensive wide area information packet network, and regardless of the cost of auxiliary device how.As the application number of investing Bell Laboratory is 3,749, in 845 disclosed by indication saddle cloth any the eggplant  of comprehensive TDM system censure the cape sincere feeling change on foot Huaihe River Π   shallow＞the female non-irrigated #  of the tranquil thumb  whetstone saddle cloth of giving repeated exhortations say that vigorously the bald throwing of any of several broadleaf plants Shun says the wilful Ping of peace and drop down and send lie father and return and imitate W Chi emperor amaranth and sprout by blocking the close an official document or note of  ɡ   and expect, 979,733, it be used to cushion and the more enforceable hardware technology of addressing information bag go to reduce this processing that does not significantly gear to actual circumstances burden, get on as long as they are removed and be put into another from a TDM trunk line.But what this addressed only is the less important relatively part of this problem.As same assignee's United States Patent (USP), application number is 4,491,945 to have similar effect, discloses based on the Banyan type packets of information exchange of hardware and be used for image information to transmit the scheme that exchange is used to rotate address bit like that.

Packets of information ordering, especially computer data information bag, it is necessary can being arranged different routes or can being changed in the packets of information switching system of buffering at the continuous information bag.In the packets of information switching system, various rules, are commented on compunication in the TANENbAUM benchmark in order to implement alignment problem.The node place is same can " to be adjusted window " and (Sliding-Window) uses together a short ordinal number field in packets of information receiving, so that differentiate next packets of information of giving the phase.In data block (or file) transmitted, in the simplest rules, any out-of-sequence packets of information that all retransfers and all packets of information in succession caused significant the delay and the loss bandwidth.In more complicated rules, buffer is arranged on the next door of each packets of information of a data block movement device at destination node place, and each packets of information just is placed in the suitable buffer when it arrives and goes.Short of information interval more early exists, and then this node processor can begin information is focused on the data block of the adjacency that is used to transmit, so that suitably talk with, and perhaps read message bag and deliver to primary processor from the buffer of calibration sequence.If there is information interval, then omits bag and can be identified so that transmit again.Back one method does not gear to actual circumstances, because to this method, the length of packets of information is very different, the size of data block is big, perhaps data block comprises a large amount of packets of information, moreover it requires more buffer space, the dual processing of bag and more requirement is arranged on the software processes at target place.

In all existing packets of information switching systems of the process computer data known to the applicant, all to interrupt this destination node or primary processor in each moment that receives a calibration information bag according to the order of sequence, so that determine the length of its data segment, to arrange to be used for the calibration memory position of data, and transfer data to the position, cause collecting the most at last raw information.And use with the DMA(direct memory access (DMA) technology of hardware as media), data are sent to memory location and take out data from memory location, in fact do not involve processor, this (sees the Shiva benchmark) in Computer Design all be known, and use or recommendation (applicant is known) similar techniques are not used for transmitting by the data of a network from memory to memory.Bi Yao bus, data, address and control pair DMA are unusable in one network.And the problem out-of-sequence in the computer-internal sequential bits can not produce in DMA transmits.In any case if similar hardware based technology is used for the transfer of data by a network, that will increase actual advance.

In wide area information packet network, be considered under the basic full distributed control asynchronous, no contention, network access and known be that system's (insert loop and loop as the register with Tropper and the comment of Tanenbaum benchmark, fluting loop and mark pass through loop) of matrix provides these characteristics with the ring.In general, anyway, because the structure of their loops, be that the system of matrix is considered to not be suitable in WANS in essence use with the ring.However, it is interested especially that register is inserted the loop because they provide some use to intrinsic packets of information storage or buffering, and the different node on this loop between the packets of information that obtains transmitting at synchronization.

Register, buffer or postpone to insert and guarantee that distribute and middle access no contention, rely in a register or the buffer and (be called here and keep FIFO, be fifo registers) by postponing any straightforward procedure that enters packets of information, take out packets of information and then in the loop, carry out.Tropper and Tanenbaum benchmark are commented on non-contention circuit system, comprise that register inserts, and point out many diverse ways, and wherein, the inherent latency that transmits the data that center on a register insertion loop can reduce to minimum.This is the problem of seeking in darker mode in other benchmark.

Give fixed in fact being disclosed in the United States Patent (USP) of investing NEC by hard-wired register insertion exchange and the audio frequency/data message packet communication in LANS, its application number is 4,500,987, and invest in the United States Patent (USP) of CETT, its application number is 4,168,400, each assignor gives higher priority and dispose various types of packets of information on each exchange or node to be inserted into first-in first-out (FIFO) formation to audio-frequency information bag (with a field identification).In asynchronous loop, use control logic to select the highest priority packets of information,, perhaps replace in the loop packets of information than low priority so that transmit in the information interval between packets of information.This routing node is around the media distribution layout in a series connection loop.

This NEC patent is to utilize the way of giving a fixed cyclical information bag " space " to go configured bandwidth effectively by the needs that audio frequency connects, with the effect two-way communication.But this brings cost, and promptly many giving decided packets of information with emptied, thereby in integrated system (its ability is to be full of audio-frequency information at interval with data packets), foreground is the major advantage of packets of information exchange.In order to keep the loop synchronous, use the regular length packets of information, and the advance that the loop propagation delay be jealous of  8 Su ETT patents to advocate by to be made the side angry  of   ざ magpie by the shave a man's head  dynamically how effective adjustable length packets of information of use that is to have the ability, and disclose and a kind of they have been inserted in the loop to replace the method for defective packets of information.Method neither one disclosed in two patents is the end-to-end processing that is applicable to the packet in network, transmission or dialogue layer.

This be that to use the rules of simple approval in system's (referring to as the bridge joint benchmark of example) of matrix be that this target is duplicated to wrap in this raw information and received and be provided with each packets of information of replying (ACK) Q-character with the ring, its source of being moved out of of this ring arrival of original packet continued circling then.If this destination node is just hurried in, it is this packets of information of reproducible not, and the ACK Q-character can not be set, and then the selection of shifting out this packets of information will be made in the source, and trial or some time before shifting out this packets of information allow this packets of information to enter circulation once more after a while.When destination node was just busy, these rules not only retrained this source, and made it go processing broadcasting to become the just busy place of unpractiaca thing, especially minority addressing node.In addition, in multiloop system (must in WANS), it be unpractical, and owing to be this reason that the system of matrix helps to limit single loop LANS with the loop, it collapses big.

It should be noted that, in this specification, using loop and loop term is synonym, though " loop " by through being usually used in receiving in the system of whole packets of information, " ring " then passes through in the system at each station through the position that is usually used in packet data flow.Also it should be noted that, do not get rid of by the shared double loop that is used for each direction of all exchange components with reference to the described loop of context.

Task of the present invention is to propose as above indicated problem separately or jointly, and improved packets of information switching method, network, exchange, node and/or rules are provided.

From one side, present invention resides in and have regular length (and, preferably short) the memory benchmark (for example displacement) that need consider in the packets of information of data field the time, so that the process that with hardware is media can be used to this source to produce memory access, and, not only produced a suitable storage address but also transmitted separately data segment at the target place.This has alleviated the terminal handler that will consider to interrupt-be driven processing.One " direct memory transmission " like this (DMT) handled the memory that will in fact supervise dress bag, folding bag, sort and be sent to adjacency, and, preferably be suitable for computer data certainly and transmit.Based on context, a short data field is less than 560, preferably is less than 240.

The DMT hardware that is in the source in whole block movement also the computing block verification close number, and it is enrolled a block message bag full stop.In this destination end, this DMT hardware calculates its verification and closes number, and and the block message bag full stop that receives compare, send a suitable ACK(affirmative acknowledgement) or the NAK(negative response) to this source, and (if ACK is sent) interrupts this node processor so that use the buffer that contains this piece.Like this, only interrupt just transmitting very big data block at every end place with a processor.In any case received NAKs shows the non-noise sign that gives the phase, this DMT hardware (or communication software) will be considered to use smaller piece, so that further be sent to that target; If circuit improves, just by big data block.

In fact, every packets of information has three-level addressing: destination node or crosspoint (claiming the node addressing here) in the initial addressing identification given area; Second level addressing is identified in the buffer that destination node (be called socket here, or half talking with number) is located; Be identified in the memory location (being called memory access here) that is identified buffer inside and is placed into the packet data section with implicit third level addressing.Can use additional addressing level or node addressing conversion, so that transmit the adimission area of packets of information to WANs.

On the other hand, the invention provides a kind of also can most ofly enforcement with the ring in hardware is the packets of information exchange and the method for matrix, and the DMT technology that indicates more than being suitable for well.This exchange comprises many crosspoints that are connected in the loop, and each unit adapts to the switching packets that reciprocally combines with node and loop.Corresponding to this one side of the present invention, its responsibility is to be put into (being that it can not transmit the node of packets of information to it) on the busy crosspoint, is resumed in the loop to guarantee the packets of information that is addressed; When this packets of information is put into this loop, do not need source unit to go to monitor receiving of it at the target place.

Best, stroke (RTR) Q-character that rounds off is inserted in the exchange of this target in giving the packets of information of deciding recovery, any unit quilt that is addressed to the stroke characteristic position of not rounding off is early thought disabling unit in the unit after a while, and the unit has the ability to utilize the space on this loop to transmit other packets of information after a while, therefore, give and be used for the packets of information of (upstream) unit early surely, when being put into this loop first, must have the RTP flag bit.

(unless Q-character indicates the thing of reception by the target location, all packets of information stroke that all rounds off, and opposite scheme is possible in the buffering parallel circuits.And this is considered to be equivalent to and utilize the notion of RTP Q-character, but such scheme seldom is in desirable series loop.）

This crosspoint node related with them carries out addressing from minimum to the highest by the direction of data flow around the loop according to the order of sequence, the crosspoint of lowest address (being called address 0) is used as a checkpoint, and the function of checkpoint is to shift out all RTP Q-characters from the packets of information of the packets of information of passing through and all inefficacies.

Also play an important role in handling broadcasting according to checkpoint of the present invention.To the crosspoint that other group of unit requests in loop start broadcasting send one have sending them to this loop before the checkpoint packets of information of removing to disappear " request is broadcasted " (RQ BCST) Q-character that usefulness " broadcasting " Q-character replaces.When the BCST packets of information transmitted each crosspoint, it duplicated and delivers to the node related with it by that unit so that handle.When they return, checkpoint all packets of information of BCST Q-character cancellation.When the broadcast message bag was received, if crosspoint hurries, it must duplicate this packets of information, inserts its address, and put copy immediately after original packet in the loop.

Packets of information exchange of the present invention can combine with " clear passage ", the parallel joint in the loop of bypass crosspoint group (and even providing it all to use in the crosspoint of clear passage porch with the checkpoint and the error checking of the relevant function of RTP Q-character) just, each terminal terminates in the crosspoint to be used for the interface initial circuit.All are sent to unit after a while than the non-broadcast message bag that clear passage downstream units has higher address, so that forward, thus this temporary location of bypass.In general, BCSTS does not have ability to use clear passage.If the clear passage downstream units is hurried, this upstream units will be supspended the transitional information bag.

In this method, circuit volume is not to be devoted to return all arrival sources so that the packets of information of cancellation, for the big traffic may the loop between neighborhood of nodes in, this is useful especially.

This exchange can be implemented in the width up to the packets of information median of any hope, though they are different on details of operation.One one bit wide loop is a series connection loop, and the crosspoint among it (node that is associated with them) distributes by the area and distributes; Higher parallel form will be intensive component equipment (or integrated circuit), for them, will make star line style formula from the binding of peripheral node.The latter's exchange pattern can be exceedingly fast.The comfort level of parallel pattern is corresponding to the figure place in the header field of this packets of information, loop address and type.

Series loop is different with more parallel loop in detail, because (depending on the degree by buffering) is before the address is read out, first of packets of information can flow into this loop, for example, a busy crosspoint may not have ability to go to read to introduce on this loop the address of packets of information before they begin to form the loop that enters this exit, unit again in a series connection loop.Under the sort of situation, if this unit hurries, the RTP Q-character that will have no time here to establish, and this packets of information will continue by this exchange.But the paying this and will be retained in the buffer that passes through and (be called here and keep FIFO of this packets of information, be fifo buffer), and be placed on this loop, along with its RTP Q-character is set up, follow original packet immediately, thereby guarantee that this packets of information finally is received.

Accordingly on the other hand, this invention provides and has been suitable for the high speed information packet network that audio frequency/data transmit, and it is in conjunction with the DMT technology with packets of information exchange with above-mentioned type.According to known technology, the audio-frequency information bag is transmitted, sorts and/or abolishes, and computer data is handled by the DMT hardware that is configured in each routing node.Here, audio frequency, computer data and other packets of information are assigned with the priority of various grades, each crosspoint preferably includes the short buffer queues of a series connection (be used for each priority level), no matter be the packets of information on the loop, still wait for the packets of information that transmits, can both be assigned in the formation and go.This type scheme by above-mentioned CETT patent disclosure does not form part of the present invention.

Because its high-speed and low stand-by period, and owing to use the short message bag, the exchange of this invention and method are particularly useful for the audio-frequency information packet switch.Owing to use disclosed direct memory tranmission techniques, the present invention also is specially adapted to computer data and transmits.In addition, two types packets of information can have processing rapidly on the constructed identical network.

After having described essence of the present invention widely,, by way of example and diagram, certain embodiments is described now with reference to accompanying drawing.

Fig. 1 is the overall block-diagram that shows packets of information exchange elementary cell that constitutes according to the present invention, simultaneously in conjunction with network of relation;

Figure 1A is the block diagram that can implement " clear passage " in key diagram 1 exchange.

Fig. 2 is the schematic diagram applicable to the packet infrastructure of the exchange of Fig. 1 and network use.

Fig. 3 is a block diagram that the crosspoint series connection is implemented of packets of information exchange among Fig. 1.

Fig. 4 is the block diagram of one the 16 parallel enforcement of bit wide of the crosspoint of information exchange among Fig. 1.

Fig. 5 is the circuit diagram of the maintenance FIFO of crosspoint among Fig. 4.

Fig. 6 is the circuit diagram that receives (or transmission) crosspoint FIFO among Fig. 4.

Fig. 7 is the circuit diagram of the address comparator of crosspoint among Fig. 4.

Fig. 8 is the circuit diagram of the error checking circuit of crosspoint among Fig. 4.

Fig. 9 is the verification of crosspoint among Fig. 4 and the circuit diagram of generator circuit.

Figure 10 is the output stage frame circuit diagram of crosspoint among Fig. 4.

Figure 11 shows that clear passage can be linked to the frame circuit diagram of the mode of crosspoint among Fig. 4.

Figure 12 is the block diagram that transmits the Fabric Interface that hardware combines with direct memory.

Figure 13 is the logic and the flow process of the function of explanation direct memory transfer approach; And

With reference to Fig. 1, the network of this selection comprises the packets of information exchange 10 with a plurality of crosspoints 12, and this crosspoint 12 is that series connection links in the loop 14 with corresponding transfer approach, and each unit 12 will be connected to node 15.Checkpoint 16 is also included within this loop, as indicated in, append to a crosspoint 12 easily.

Each node 15 comprises a Fabric Interface 20 that is used to be attached to each crosspoint 12, and comprises that also a device interface 22, the latter comprise this node processor and by device interface 22 dissimilar terminal installation 24 be connected to this network.The function of Fabric Interface 20 is to form respectively and separate the data that back and forth are fed to interface arrangement 12.The function of device interface 22 is tissue and data feeds between device 24 and Fabric Interface 22.This node processor is a microprocessor, and it is handled resident window user interface and is used to handle the communication of many sessions, and interface is to the rules conversion program of the different device of this network, Data-phone enhancing and cryptographic services or the like.

In this example, exchange 10 can regulate comprise a checkpoint 256 crosspoint 12(each its node 15 and the terminal installation 24 that is associated are all arranged).As arrow was specified, these crosspoints were counted addressing from checkpoint (checkpoint distributes 0 address) around the advance sequence of this loop data flow path direction.The address of a crosspoint (with its node) is this loop address.

Not all node all needs to be attached to terminal installation, as digital phone, master computer, terminal, printer, plotter or the like.The device interface of node 15A is a bridge joint configuration, be used for being communicated with the similar network 27 that constitutes according to the present invention, and the device interface of node 15B is constituted as a passage with dissimilar network-in-dialing, and these dissimilar networks are telephone system, X25 packet switching network, Ethernet (TM) or similar network as is well known.The rules conversion is finished with method commonly known in the art in such bridger and passage calculated address and with regard to passage between network.

The form of the packets of information that expression is used in Fig. 2 example, data block P has described 176 packets of information that comprise 4 fields: one 8 bit format field T, one 8 loop address field LA, 16 socket digital section S and one 144 bit data field D.The title of two field configuration information bags.Depend on transmission media and the data link layer rules utilized, this packets of information can be worked out a frame preorder A and frame postorder B, but these and do not require one intensive, within the exchange of parallel construction.

As showing by data block T, format fields self comprises 5 son fields, they are respectively: the given priority level of serving this packets of information (2), the service quality of representing by reliability (1), the stroke that rounds off (RTP) Q-character (1), 2 seat field show the socket address be how to be understood (that is: as socket address (standard) RQ-BCST, or BCST) and a packet format son field (2), it shows whether data field is counted as storage, control, rules or operation information; Thereby this packets of information will be submitted to corresponding as " memorizer information bag ", " control information bag " or the like.

Socket field S discerns a session buffer in the node address space that is indicated by the loop address that is associated, and corresponding half session list I connects.Have this situation, same time 64K is full of session simultaneously at same node, and a terminal installation (as a master computer) can be responsible for many sockets voluntarily, thereby can be connected to a node to many devices here.

As by as indicated in the data block M among Fig. 2, when this data field is understood as that memorizer information, then preceding 16 of this field will be read out as memory benchmark or displacement, remaining 128 one 16 byte section as user data.The theme of DMT technology of the present invention is exactly this displacement and the data segment that is associated with it.If this data field is understood as that control information, then whole 144 will be as the instruction of pressing application definition by node processor, so that consistent with communication or application software operation.If this data field is understood as that rules information, then preceding 8 are used as command field, and remaining bit shows related rules function; For example packets of information is represented an end (EDT) that affirmative acknowledgement or negative response (ACK or NAK), data block transmit or a request (describing below) that is used for state information.Finally, this data field can be understood that network management, operation and monitor message.

One or more verifications with incorporate packets of information (by prior art) into own forces, provide bigger fail safe to one or more fields, but this point is not shown in the example of explanation.

Because the known technology in the register insertion system, the distribution of two-stage priority will no longer be described, and supposition only provides 16 bit wides parallel exchanging form.(not shown) in that form adopts two kinds to transmit FIFOs measures (but not expressing), and one is used for high priority (audio frequency) and another is used for low priority (computer data) packets of information.According to the maintenance FIFO of crosspoint, the low priority packets of information can be preferential, with a packets of information in the high priority formation that allows to be transmitted to it should have on the position, but this low priority bag of taking the lead preferably is assigned to this high priority formation.

Data are surrounded by does not have memory access, depends on the distribution of the two-stage reliability of transmission.If like this, the high reliability position in the type field is set, and therefore received packets of information is understood and is replied; If not so, highly reliable position will not be set, and this whole data field is used to the voice data handled in the minibuffer device at the receiving terminal place of active window technology easy to use.

When operation, carry out the transmission or the reception of data by terminal installation 24 for each, exchange with device interface 22 under the application program operation control of this interface processor, this interface processor distributes a socket number and buffer to (no matter receiving or transmit) between each half-session.For audio data situation (by the known method digitlization), this transmission socket can only be 16 bytes (packet data sections), and the reception socket buffer that is used to connect can be greatly several times (finishing ordering and delay compensation) so that use the known method of little modulus.The capacity energy study plot that is used for the socket buffer of audio frequency communication collapses and connects network, and during call setup, do not need to consult, for the computer data situation, the capacity of each of 4 socket buffers that are assigned to each connection is consulted (every end has one and transmits and receive socket) at the call setup place, but need not to be symmetry (though the socket buffer capacity at the every end place between identical half-session will be identical), can there be 1 megabit big like that, and can be dynamically regulated at a session by rules, operation or control information packet switch.Such communication is virtual pair of I circuit between packets of information.

Distribute to the grade of service (priority and reliability) of output information bag, with they loop and socket address and transmit socket buffer base address (in the situation of memory bag) together by this node software distribution at the call setup place, and be recorded in the transmission table (following be described) with reference to Figure 13.Fabric Interface 20(one hardware unit) can be from transmits continuous 16 the 8 bit data word sections of suitable position taking-up of (by the priority order of distributing) the buffer at each, title and target socket number are appended to each data segment to form a bag, and arrive relevant crosspoint 12 successively by this bag, crosspoint 12 is not striven this packets of information insertion or the loop 14(that arbitrates hereinafter will describe unexpectedly then).

This reception is handled and is directly carried out, each crosspoint and by the loop duplicate (or cancellation) they, shield loop address (if desired) and forward them to the Fabric Interface 20 that is associated successively, here this pair basis and both field are read by hardware.For memorizer information bag situation (reception high-reliability service), Fabric Interface combines the information that comprises in the reception session table of information of same corresponding to the socket digital section of a packets of information in input information packet memory benchmark field, so that in proofreading and correct the reception socket, produce a particular memory address, user data 16 bytes are sent to proofread and correct and receive socket, and influence is delivered to that unit to these data.These actions realize that direct memory of the present invention transmits mechanism and don't exists the dried of processor of any associated devices interface 22 to give.

For the situation that transmits audio frequency (for low reliability typical case), this packets of information is directly delivered to suitable socket buffer in device interface 22 by Fabric Interface 20, carries out suitable ordering, delay compensation and D/A algorithm there.The sound signal that reconstitutes then can be delivered to the telephone terminal corresponding to this reception socket.Thus, this high priority audio frequency wraps in each crosspoint place and will get this low priority computer data bag (as indicating in the past) earlier.

The packets of information of all other types is also delivered to device interface 22 by Fabric Interface 20, but they directly do not enter the socket buffer, but will cause on the device interface processor that interrupts and require some service order.

Figure 1A describes is the use of " clear passage " 14F in the exchange loop among Fig. 1.One group of adjacent crosspoint 12 on this loop of each clear passage bypass.Select to have at the crosspoint that clear passage begins to locate, and make such packets of information freedom of entry passage than the input information bag high in the element address in this clear passage exit.Broadcast message bag (and requiring broadcasting) does not send on clear passage.If this checkpoint of clear passage bypass, the crosspoint that begins to locate at clear passage must be finished the effect of the checkpoint that relates to the RTP Q-character so, preferably relates to getting rid of defective packets of information.

The node that crosspoint and they are associated is valuable by a kind of distributed series connection exchange of arranged spaced on the region to the LAN system that is used for certain site location.In high-speed peripheral with the master computer link, the loop that possesses this specific character is valuable, for example, teaching the assorted gruel of the not smoothgoing tip to censure to change bad ピ to herd the low rifle  rose mould lemon  Fu that is in seal H crook  shelf  south when given uh Lai south the empty badger kneecap of the broken joint of non-  huge legendary turtle ⒌ bangs sole  drone  chessboard thumb rabbit Wei steals humorous pleasing and shoulders soft-shelled turtle and change the extensive matter of bad ピ loess hills ┮ we has the bad fashionable beer of the meaningful   of lotus root promise capsule Huan dimple daughter-in-law Jing

Referring to Fig. 3, the startup of clock signal checking information bag is provided and a conventional decoder 40 of input bag decoding is led over series connection crosspoint 12A, it continues to receive loop 14 by encoder 42, and the digital coding that the series connection on 42 pairs of loops of encoder transmits is also delivered to next crosspoint.And loop 14 itself has only 1 bit wide, and other data channel of major part in the series connection crosspoint in this is given an example are width (16) of packet header.

The bit stream of each the input information bag that transmits from loop interior section 14A, enter 16 bit strings-and receiving register 44 via circuit 43, this loop address and format fields can be read by control logic unit 46 via input bus 48, and make each word of the packets of information of sending to crosspoint enter the Fabric Interface that receives FIFO52 and be associated to this via bus 50 displacements via output bus 54.The bit stream of each packets of information also can be via loop feature 14A to output multiplexer 56, if when this bit stream of its result is selected, it will directly also enter loop 14 by this crosspoint to encoder 42 once more.One isolates trigger 58 is inserted in the loop between multiplexer 56 and the encoder 42, so that one the 1 exchange transient process in the digit buffer shielding multiplexer 50 is provided.The 14A that multiplexer 50 is provided in the interior section in this loop usually goes up the selection data.At last, incoming bit stream is the adjustable length maintenance FIFO62 via 60 to 1 bit wides of circuit also, and it can be displaced to the 2nd input 64 and enter multiplexer 56 from FIFO62.Control logic unit 46 can rewrite preceding 16 that keep FIFO via bus.

In transmission one side of crosspoint, the packets of information that is used to transmit is shifted to send into via bus 70 from the Fabric Interface that is associated and transmits FIFO68.Packets of information from transmit FIFO16 via bus 72 can by 16 words be moved out to one also-string transfer register 74, and from here as a series connection bit stream via circuit 76 to multiplexer 56 the 3rd input.

The operation of the series connection crosspoint among Fig. 3 just will be described now.

Utilize and receive FIFO52 and unloaded transmission FIFO68 and the multiplexer 56 that is in normal condition, the position of an input information bag stream enters receiving register 44, enter and keep FIFO62, and by multiplexer 56 only with 1 delay enter once more this loop preceding 16 be recorded after, the packet header in receiving register 44 is read by logical block 46.If an input information bag is sought this address, perhaps it has the setting of broadcast feature position, and the word of logical block 46 these packets of information of continuous dislocation then receives FIFO58 so that the data of receiving register 44 are inserted, and from here to Fabric Interface.During this period, in any case the position of original packet is mobile and be disposed into the next crosspoint (unless it is the broadcast message bag) in this loop as " extremely " packets of information by multiplexer 56 from loop feature 14A.

Seek end one early (upstream) node and/or do not have it the setting of RTP Q-character be not that the packets of information of broadcasting says that it is dead becoming.Directly say that by the crosspoint in this loop becoming is " non-buffering " allowing the input information bag; Wherein the crosspoint that multiplexer 56 is converted to the loop program block says that becoming is " buffering ".

When a title with ' this address ' (or broadcasting) input information bag is recorded to receiving register 44 (with when this crosspoint is non-buffering), suppose that receiving FIFO52 is full of.At this moment that will be too late for the mid-RTP Q-character of original packet in transmitting on this loop, and dead packets of information will take place once more for this.And keep FIFO62 to allow (by logical block 46) to go to expand to adapt to all positions of input information bag.The title of packets of information will be recorded to receiving register 44 simultaneously and keep going among preceding 16 of FIFO, so that control logic 46 can identification address and be kept at RTP Q-character (and being to insert this address) in the packet header that keeps among the FIFO62 in the broadcasting situation.When change has been finished, and after original packet had been left multiplexer 56, control logic 46 exchange multiplexers 56 were to select circuit 64 and set about shifting out modified packets of information from keep FIFO62, corresponding this FIFO that dwindles of while.

The packets of information of supposing another packets of information to arrive and revising is also being carried out by this way, then its passage 14A on the loop will be by multiplexer 56 shielding (or interruption), and it is recorded among the maintenance FIFO after last position of first information bag immediately, and its title will be read by logical block 46 after being recorded to receiving register 44.If it also is about " this address ", and receive FIFO and be still and be full of, it will be moved into and keep FIFO62 reach the top up to its title (when control logic stops to be shifted this packets of information when entering), and its title will be modified as previously mentioned, as previously mentioned, it will be returned on the loop.

If this crosspoint just is being cushioned and an input information bag is dead packets of information,, keep FIFO not to be expanded, and the position will be revised mutually continuously in receiving register 44, thereby make this packets of information invalid then for adapting to it.In any case if it is an effective information bag of addressing downstream units, it will be held the FIFO buffering, and (do not revising) from being placed on immediately after the packets of information formerly among the FIFO62 on this loop.

Logical block 46 is utilized crosspoint and the packets of information that is used to transmit in transmitting FIFO68 in non-buffer status, exchange multiplexer 56 changes the buffer status of crosspoint to it like this to select circuit 76(), word for word parallel shifted is by transfer register 86 for packets of information in transmitting FIFO68 quilt simultaneously, and serial shift is to loop 14 then.When this situation takes place, do aforesaid processing for any packets of information that the buffering crosspoint arrives.As the processing broadcast BC STS that indicates for a long time.The crosspoint of a non-buffering will transmit the broadcast message bag and directly enter indeclinable channel loop (being read by every other crosspoint), but when identification BCST, control logic will be displaced to it and receive FIFO, so that be sent to Fabric Interface.If crosspoint just is cushioned, as mentioned above, this BCST packets of information will be moved into and receive FIFO52, and it will be by keeping FIFO62 to keep, till the packets of information that transmits from transfer register 74 has been left, afterwards, multiplexer 56 will be selected circuit 64, and the BCST that postpones will be returned by the loop.

In any case if this crosspoint just is being cushioned and this reception FIFO52 is full of, then this packet header (be kept at keep FIFO62 in) will be changed in control logic unit 46 becomes RQ BCST and changes the address and become " this address ".This packets of information will continue as the checkpoint 16 of an effective information bag by this loop, and here it will can not read (because its nonzero address) by first unit, reach this original switching unit that can discern its address up to it.That (if this unit is non-buffering), packets of information is with the loop (by other unit do not read) of (I) continuation by being moved by this checkpoint, (II) will be replicated and move into reception FIFO52, (III) will be stored in and keep among the FIFO62, and control logic makes it return a BCST with rule of checkpoint address (zero), is put back into the loop then and gets on.

Any crosspoint of a BCST of request deactivation all sends the RQ BCST packets of information of an addressing checkpoint, and here this RQ BCST Q-character is changed to a BCST Q-character, and this packets of information is sent back to this loop.

At last, be to be noted that, in example, comprise direct circuit 14A by crosspoint in order to reduce the delay in non-buffer cell.If not so, this crosspoint will such as preceding roughly description turn round crossing, still, all will in keeping FIFO62, postpone the sufficiently long time, so that read whole title and make and realize judging for each packets of information of control logic.For may being nonsensical, but do not wish by having the loop of twisted pair medium by high speed loop with very short bit time yet.

＜checkpoint 〉

In the design of the crosspoint of just having narrated, for serial exchange, checkpoint 16(Fig. 1) almost be identical.Topmost difference is that its control logic guarantees that it always cushions whole packets of information, thereby this control logic can detect and get rid of the packets of information of a mistake.

The basic function of this checkpoint is that all are not provided with the packets of information of RTP Q-character in cancellation (mobile, remove), arbitrary RTP mark in the cancellation software kit requires broadcasting with all RQ-BCSTS() be transformed to BCSTS(broadcasting) and the packets of information of from the loop, removing all inefficacies.As previously mentioned, finish packets of information mobile be simple, not will they be shifted out outside the maintenance FIFO and order packet rewrite subsequently they.One of device that can be connected to the checkpoint crosspoint is the control desk of network manager, and its allows network manager to keep by utilization and the broadcasting of Control Software Package deactivation, adjusts from transfer rate, the cost sheet of indivedual nodes and monitors this system.For example, in order to adjust transfer rate from crosspoint, each unit comprise one again the SM set mode counter go to by the transmission FIFO packet count, also comprise a control register of set again that only is used to control the packets of information of sending by the circuit management person.(for the purpose of billing, this state counter also can directly be inquired by the circuit management person.) this counter every now and then relatively and when this Count of Status equal that control register puts several the time, the transmission of packets of information just stops.Then, can select transfer rate by reset mode counter periodically and the input of adjusting status register.

The sixteen bit crosspoint that walks abreast

In order to carry out packets of information exchange and transfer of data at high speed, in loop apparatus, need correspondence to a certain degree, the packets of information interchanger that is constituted according to the present invention can have any desirable to response until the bit number of a packets of information.But, be 16 for a preferred minimum value of parallel circuit system, this is the bit number in the above-mentioned packet header and is the arithmetic multiple of bit number in this packets of information.This interchanger will make the equipment component of a miniaturization and even can realize with the VLSI chip.The crosspoint that is used for a kind of like this interchanger describes with reference to figure 4 below.

16 buses that constitute loop 100 enter crosspoint 12 parallel series ground and keep FIFO104 and a multiplexer 106 by an input register 102, a variable-length, and before leaving crosspoint it also through an output stage 108.Because this crosspoint is in the place that is in close proximity to another, does not need encoder in this interchanger scheme.After input register 102, the bus that loop 100 is taken is connected with: (I) by one 2 cycle delay element 110(through bus 111) be connected data FIFO112 to the interchanger interface through bus 114, and (II) to an address comparator 116, error checking device 118 and control logic unit 120.

Control logic unit 120 has and much is connected to or from the connecting line of other each circuit in the crosspoint (by arrow 121 expressions).This will make an explanation hereinafter, but mark for simplicity and not.For having the reason of two output bus 100a and 100b also will be illustrated below to multiplexer 106 from maintenance FIFO104.

Aspect transmission, the packets of information of this interchanger interface (in 16 words) reception transfers to by bus 122 and receives FIFO certainly, and sends multiplexer 126 by bus 126 to from receiving FIFO.At last, error checking generator 128 by bus 132 receive from the loop output of crosspoint and calculation check and, this verification and this moment appear on the bus 130 as the other input to multiplexer.

For this interchanger, a kind of realization of suitable insertion degree is employed all the other public lines of crosspoint on operating loop and the base plate, and each crosspoint all is inserted on this base plate.Except the bus of loop, this base plate with the remainder data line comprise that 10 bus 134(are provided with the crosspoint address according to the employed packets of information of base plate) and the first word incoming line 136 of a formation daisy chain from the crosspoint to the crosspoint and when first word of the packets of information holding wire effectively time the in input register 102.Therefore, on online 138, control logic produces first word output signal, and it comprises the signal that is used at first word incoming line of next unit, loop.Other base plate line (not shown) comprises " firmly " reset line, a clock line (25 megahertz) and power line.This implementation is that supposition crosspoint and its related exchange interface are to be in extremely approaching place, is likely to be on the same block of circuit card.

At work, (minimum-rate of the data transmission rate that provides between 400 megahertz crosspoints) is recorded to next crosspoint packet word from a crosspoint each clock cycle.When first word of packets of information in receiving register 102 when being effective (signal that sends on as online 136), its address compares with the address of this crosspoint and whether control logic sends whether the packets of information address is greater than or less than this address and be zero relevant signal in comparator 116, and its title division is by circuit 118 verifications and exist under the situation of error control logic to send signal.

According to Fig. 3 to the described principle of serial crosspoint, control logic 120 mail message bags (adopting displacement word continuously), Here it is: if this packets of information be effectively and be to be used for " this address ", then it by 2 bit delayer 110(for for the purpose of synchronous) be displaced to reception FIFO and any packets of information of waiting for is displaced to loop 100 through multiplexer 106 in FIFO124; If packets of information lost efficacy, then first (and all hysteresis) word is not moved out of input register 102 and the packets of information waited for can be transmitted once more in transmission FIFO124; If packets of information is effective, but " here " (here) be not addressed, if and not have among the FIFO124 packets of information to wait for and keep FIFO104 in transmission be empty, the packets of information that then enters is shifted (utilizing a word to postpone) to the loop 100 by keeping FIFO104 and multiplexer 106; If an output information bag (from FIFO124) is just shifting by multiplexer 106, the packets of information that then enters is kept FIFO104(by shift-in, and it can be expanded as required); And if it is full to receive FIFO, any packets of information that enters that then is used for " this address " (This address) stops by keeping FIFO(to be cushioned as required) and enter output stage.There, its title is correspondingly revised.(the input LA that enters output stage 108 represents that this crosspoint loop address is fed to that circuit so if need this crosspoint loop address under the RQ-BCST situation, makes it to select by Be Controlled logical one 20.）

The work of the crosspoint of this example also can be described by the typical program of appended appendix 1, the employed suitable chip of this circuit is listed in the appendix 2, so that those skilled in the art can go design and constitute a crosspoint to go work by its described content.Yet the further explanation of relevant some circuit function will provide below.

Referring to Fig. 5, keep FIFO104 to use having realizing at variable existing 16 multi-stage pipeline registers (MPRS) between and four cycles.Three multi-stage pipeline register (MPR ₁, MPR ₂, MPR ₃) use of being connected, be 1-12 cycle (packets of information is 12,16 word lengths) to obtain total delay.Input to MPR to the input bus 100 that keeps FIFO ₁, the output bus 100a from FIFO is the output of the series connection transmission of all three MPR simultaneously.Output bus 100b only is the output of first MPR transmission.Control line 150(is two lines for each MPR) be the signal that is used for controlling from logical block 120.The delay in 1-4 cycle is by control MPR ₁With select bus 100b to realize by multiplexer 106, the delay in 5-12 cycle is realized by all three MPR of control and selection bus 100a.

Fig. 6 has illustrated a kind of method that receives and transmit FIFO that constitutes.Logical block 120 that complicated is need show that these FIFO are empty or full, thereby shows do not have packets of information or show that no longer including (all) packets of information can pack among them.But the FIFO that is made of the both-end random access chip in the method for routine can only show that they are empty when not comprising word, is full when they no longer include word and can pack into.The working condition that receives FIFO112 will be given explanation, and the working condition of transmission FIFO124 can be identical.Input bus 111 is fed to both-end arbitrary access memory cell 152 and output bus 114 output bus as this memory cell, in addition in conventional method, unit 152 by write address counter 154 and read address counter 156 by separately write and read bus 158 and 160 control.

In order to keep a packet count, adopted forward-backward counter 162 and comparator 164 as shown in the figure.Counter 162 is respectively from writing complete signal and running through forward counting signal on full signal (this signal obtains from counter 154 sum counters 156 respectively) the reception line 166 and the signal that counts down on the line 168.Operation difference (being illustrated in the quantity of packets of information among the RAM152) is showing on the bus 170 of comparator 104, when the counting on online 170 respectively greater than 46 or less than 1 the time, thereby comparator 104 is set to provide on online 172 on " FIFO is full " signal and online 174 " FIFO sky " signal is provided.These holding wires are connected to logical block 120.

Fig. 7 has shown a kind of circuit that is applicable to address comparator 116, what be input to this address comparator is this loop address on 8 buses 134, and the loop address of the packets of information that enters (when the title of this packets of information in input register 102 when being effective) also is on 8 buses.These two inputs are received and produce two output signals by digital comparator 182, when loop address during greater than " this address ", signal of output on online 184 is when loop address during less than " this address ", signal of output on online 186, these two output signals are fed to logical block 120.At last, the address of the packets of information that enters on online 180 is sent to NOR gate 188, when Input Address is zero, produces an output on the NOR gate 188 online 190.

Error checking device 118(Fig. 8) is received in whole header field on the bus 192 from input register (when first word of packets of information when being effective therein).This is an input delivering to partial sum gate 194, and the output of this partial sum gate 194 is sent to register 196, and second input of door 194 received in the output of register 196 by feedback loop.The output of door 194 is received OR-gate 202 by bus 203.At work, register 196 by control line 204 by verification and the record initialization.When a packet header is received, it and verification and distance mutually, if in the institute of bus 203 wired on its result non-vanishing, on holding wire 206, produce an error so and deliver to logical block 120.

The effect of error checking generator (see figure 9) has two:

The first, read (by bus 130) leave all bits of each consecutive word of packets of information of crosspoint along bus 100 after calculation check and, and this verification and (in Fig. 4 by bus 132 and multiplexer 106) write in this packets of information back synchronous; The second, wrong verification be placed into any one and found it is in the wrong packets of information, to guarantee can not influence verification and correctness by accident to any variation that title was caused in next crosspoint by error checking device 118.Referring to Fig. 9, OR-gate 210 and register 212 are connected to error checking device as shown in Figure 8 as can be seen, and on output bus 132, do not have OR-gate as can be seen, and generation be: from wherein line of bus 132 with from error checking device 118 online 206 on signal by door 214 distance mutually.This causes the verification that produces and error.

Figure 10 at length shows output stage 108, and the function of output stage is by 8 bus 134a " this address " to be introduced among arbitrary RQ-BCST and by 8 buses 230 from control unit 120 any modification is write in 8 type fields.Bus 134a and bus 230 are to occur as the input of

multiplexer

238 and 240 respectively, these two multiplexers respectively receive 16 loop buses 100 corresponding half (8), 8 buses merging separately from

multiplexer

238 and 240 become 16 loop buses 100, before leaving output stage 108 and crosspoint, loop bus 100 is received isolates register 242.At work, when first word of packets of information during by 106 timing of the multiplexer on the bus of loop, control logic unit 120

conversion multiplexers

238 and 240 go to select suitable input with the title that produces a correction or leave them and will not revise.After this, for the residue part of this packets of information, multiplexer is converted to the normal condition of their two loops of selection bus input.

At last, can adopt the form of crosspoint parallel connection to remove to constitute high-speed channel,, in the configuration in parallel of interchanger and loop, use high-speed channel also to have bigger benefit because interchanger in parallel is structurally unrestricted and bigger capacity is arranged.Figure 11 (together with Figure 1A) shows how 16 crosspoints of Fig. 4 are promptly revised to supply with the input and output of high-speed channel.In these two figure, identical part is used identical label.As if will see, (I) when along with an address when an effective packet header in register 102, occurring in the destination address of output high-speed channel 252, (II) receives one when showing that multichannel coverter 106 at the other end of high-speed channel 252 is not transformed into other input and remaining crosspoint and is not in the signal of buffer status when control unit 120, because the selection of control unit (not shown among Figure 11) can make input high-speed channel 250 enter crosspoint at an easy rate as another input of multiplexer 106.When among these two states any occurs, packets of information (title of packets of information is in register 102) will normally be selected the path.

Fabric Interface and directly memory transmission

Fabric Interface 20 and see Fig. 1 to its device interface 22() in Figure 10, be shown specifically, its logical operation is shown in Figure 11.Yet, it should be noted that Figure 10 is that the transmission of a Fabric Interface and the requisite hardware that receives two aspects are partly schemed, the logical operation of Figure 11 simultaneously is employing virtual connection the (by the packets of information in network) between the reception limit of the transmission limit of the Fabric Interface relevant with crosspoint and other Fabric Interface relevant with other crosspoint input.It is also noted that the packets of information of delivering to Fabric Interface is in this example blocked, just they do not have its loop address field, and this information has been used.

Referring to Figure 12, packets of information from the reception FIFO of related exchange unit 12 or 12b is shifted (word for word) to related exchange interface 20 by bus 54, and be assigned to control information bag FIFO300 through bus 302, be assigned to socket register 304 through bus 306, be assigned to offset register through bus 310, be assigned to output bus interface unit 311 through bus 312.Socket register 304 and offset register 308 latch each socket address and offset field of entering packets of information respectively, used slotting seat number goes inquiry to receive conversational guidance 313 by bus 314, and adder 318 is delivered in skew through bus 316, this adder will be from the base address on bus 320 that table 313 is read (corresponding to the slotting seat number of being searched) and this skew addition, itself and deliver to output bus interface unit 311 as a memory address through 24 buses 322.

(through the bus 324) of reading from conversational guidance is to be used for that dialogue number desired end address of (number) block, and this address is sent to Bus Interface Unit 311 and is used to limit check circuit 326 along bus 322.Reception according to a block end, packets of information from the verification that has it and transmission ends be received, two verifications and being compared, a signal is sent to output scheduling degree 328 through the control line (not shown), showing a block ACK(or NAK) end of packets of information will line up at the scheduler program that is used for transmitting, and the slotting seat number of the relevant reception that is used to talk with is provided by the plug-in unit register through bus 330.When each word along the line 314 of each packets of information of a block is transferred to bus interface 311, its each bit be used to a block verification and the operation verification calculating and calculated at last at the end of block and with compare from receiving reading of conversational guidance 302.This processing procedure by 332 and bus 334 and 336 on "+" number represent.This calculating is exactly the end of determining a block transmission, and that be transmitted is AcK or NAK.

Bus Interface Unit and control information bag receive the processor bus that FIFO is linked device interface 20, and this processor and its memory are usually with 342 and 344 expressions.In FIFO300, each control information bag causes processor once to interrupt, but interface unit 311 can directly be write memory 344 with data and do not need the dried of processor to give, and dialog buffer is the some of memory 344.

Aspect transmission, second Bus Interface Unit 346 also interacts with processor bus 340 and memory 344 and does not produce interruption; It will be read the address and place on the bus 340 (through bus 348) and get the data of being read through bus 350 from memory 344.Be in these data that are included in the interior consecutive word of output (Outgoing) memory packets of information and be sent to multiplexer 352() through bus 354, under the effect of multiplexer 352, packets of information is collected and is transmitted (as 11 word strings) transmission FIFO to crosspoint 12 or 12A.To its of multiplexer 352 be: the bus 356 that is used for control (under processor program control, packing into wherein) packets of information from FIFO358 through bus 360 and from bus 340 in input; From transmitting conversational guidance 364 through bus 362 and the offset field data of coming; The block verification and, also from table 364 through bus 366; And be used for output information and wrap in loop address on the bus 368, also be to obtain from table 364.

Shown in the plus sige that uses in 370 places, its block verification and be by from data/address bus 354, the input of offset bus 362 and through bus 372 from the accumulation of table 364 and operation verification with form.Along with each word is transmitted, increase gradually from the skew that table 364 obtains through bus 362, the symbol of this situation in 374 shows.Word of every transmission, the quantity of spare word to be transmitted all will reduce in the block, and this shows with symbol in 376.At last, produce an address by adder 378, initial data writes memory 344 from reading the address, and this adder receives from conversational guidance 364(through bus 380) base address and skew (from bus 362) and on bus 382, transmit the result of addition.

Figure 13 has illustrated in a different mode and has realized said process, its data are from the flow direction right side, a left side, from read the memory write address (bus 322) that address (bus 322) and the use of data (bus 354) flow direction receive conversational guidance 313 source end and use transmission conversational guidance 364 configuration information bag P (this packets of information is passed through network).

On the transmission limit, from Figure 13 as seen, insert seat number (on bus 329, from Fig. 1 program scheduler 328) inquiry transmission conversational guidance 364, so that base address, skew, block length, the destination address (comprising type, loop address and slotting seat number) of waiting to be imported into each packets of information to be provided, 11 words of the data relevant with that packets of information are provided on bus 354.Data in each packets of information be used to constitute as the transmission block verification that has shown and.The skew (as shown in 386) that is used for each packets of information is by incremental computations, and and base address (shown in 388) provide along bus 322 together and read to store the address.Shown in 390, when each packets of information was sent, remaining block length reduced.

On the transmission limit, as as shown in 392, the block verification that is added up and from the data that are used for each packets of information be used for the data indicated above the table 364 of each packets of information, preferably shown in dotted line 394, verification and in comprise offset field, like this, even data are constants, the block verification that adds up and in also always exist variable.

Receiving the limit, number (number) field (from packets of information, drawing) of the dialogue on bus 306 once more question blank to provide base address, the block limit, the block verification that is added up and and the length that remains block.Arrive the data of waiting to be abolished false address with permission in effectively session field is included in.

Be added to base address (as shown in 396) so that the memory of write address to the device interface to be provided in the visit of memory on the bus 310 or skew on bus 322.8 words that are included in the data in the packets of information are sent to by the indicated address of the signal on the bus 322 and offer the verification of operation block and (shown in 397) of being calculated along bus 312.Foregoing such, this skew is delivered to block verification and calculating (shown in dashed lines 398) as an input, and goes to monitor that as a calibration equipment block limit is not exceeded (as shown in 400).At last, as shown in 401, for each packets of information, the number of the packets of information that is received (or by data length of data accumulated piece) is increased.

Industrial applicibility

The industrial applicibility of the present invention and embodiment has shown.Yet those skilled in the art will propose many diverse ways, in these methods, without prejudice to disclosed principle and below in the claim under the desired situation, can apply the present invention in the practice.For example, one and half serials (92) interchanger is used for described packets of information and with operation 30 nanoseconds of cycle times (33.3 megahertz), the data transmission bauds of 3.2Gb/S will be arranged.To see that also directly memory transmits principle does not need only to utilize improved interchanger, otherwise or, though only be to make up also to obtain disclosed sufficient benefit and advantage here.

Claims

1, a kind of packets of information swap data communication system has used a kind of packets of information in order to transmit computer data, it is characterized in that each packets of information contains:

The data field of a regular length is used for the user data segment that will be transmitted by packets of information in system;

One first address field, be used to be identified in the target place addressable storage buffer and

One second address field is used for pointing out the destination address at the storage buffer that is used for above-mentioned data segment.

2, in the packets of information switching system of claim 1, wherein

Said data field less than 560 bits and wherein

Said second address field shows in said target storage buffer the skew from a base address.

3, in the packets of information switching system of claim 1 or 2, use one to have a plurality of packets of information interchangers that are connected a crosspoint on the loop, in order to center on the transmission packets of information of this loop from one to another, crosspoint is also connected to node, this node merges and mask data, to reach the purpose that between terminal part that is connected to node and interchanger, exchanges, wherein

This packets of information contains a three-address field, in order to pointing out the loop address of target crosspoint,

Under conflict free situation between the packets of information, this crosspoint inserts packets of information the loop and packets of information is shifted out the loop,

If crosspoint is in busy condition, the packets of information to their addressing can not be shifted out the loop and pass through they arrival node separately, they mark these packets of information so that it can turn back to here around this loop.

4, as desired in the packet switching network of this kind of use packets of information in claim 1 or 2, the method from a source storage buffer to a data block of target storage buffer transfer comprises the steps:

To write the data field of continuous information bag from the continuous fixed length segment of block data

To write from the skew of each data segment of base address in the buffer of source in second address field of the packets of information that comprises that section and

Be identified in the target buffer in first address field of each packets of information,

By this network transmit said packets of information and

When it arrives target, the data segment of each packets of information is written in the address of the above-mentioned buffer that is identified, this address is by a skew in each packets of information second address field and a base address combination expression in target buffer.

5, according to a kind of method of claim 4, comprise the steps:

When continuous data segment being written in the continuous information bag at source place, set up one transmit the block verification and,

When continuous data segment is write target buffer, set up one receive the block verification and,

Send from the source one or more show block transmit target and transmit transmission block verification and packets of information.

Relatively transmit and receive at the target place block verification and and

According to result relatively, in a packets of information from the target to the source, send replying of a positive or negative.

6, according to claim 3,4 or 5 be used for by a packet switching network, a plurality of dialogues at place, one or more sources and between a plurality of dialogues at one or more targets place method of transferring data, comprise the steps:

For at the storage buffer of per half session establishment at each source and target place and provide its identifier,

Set up in each source of number being inquired about by source dialogue and to include the question blank of respective sources snubber base location, and be used for reading the question blank of continuous data segment increment skew from said source and said first and second destination addresses,

By inquiring about this table, and first and second destination addresses are write a packets of information and read the relative offset address that is used for being included in above-mentioned packets of information data segment from this table, form a plurality of packets of information with respect to the source dialogue,

Utilization is read in a data segment the said packets of information from the source memory from base address and offset address that the source question blank obtains,

Each by target dialogue number inquire about and comprise that the target place of respective buffer base address sets up a question blank,

First address field of reading the received information bag with recognition objective dialogue number and be used for the respective buffer of related data and read second address field in order to the skew determining to be applied and

The query aim question blank is with the base address that obtains this block and will receive data segment and write the target memory, utilizes by this and shows resulting base address and remove to determine write address the target memory from the skew that this packets of information obtains.

7, according to a kind of method of claim 6, wherein,

Before said block transmission, a call setup packets of information is delivered to target from the source, shows that dialogue or buffer number and block length are transmitted and wherein

When receiving the call setup packets of information in target, designated at the buffer of the definite length in target place, its base address is recorded in the target query table, and by identification receive dialogue number inquiry and

A response packet is sent to the source from target, is assigned to the target buffer of dialogue with identification.

8, one is used for data from being sent to data transmission system at the second addressable memory of second place unit at the first addressable memory of primary importance unit by packets of information exchange communication network, and desired this packets of information includes in the claim 1 or 2 of use:

Merging in the primary importance unit (dress bag) device, be used for reading continuous data segment and be used for said data segment is counted continuous packets of information together with memory access from said first memory, this memory access indicates in first memory luxuriant how extensive boundless and indistinct  of each data

Separation in Unit second (unpacking) device, be used for from the above-mentioned memory access the packets of information that receives continuously, obtaining the address in the second addressable memory and be used for each data segment is write from continuous packets of information the above-mentioned address of the second addressable memory.

9, be used for according to Claim 8 from a kind of data transmission system of the first addressable memory, wherein to second addressable memory transmission data block

Said merging (dress bag) device comprises:

Be used for determining skew and described skew being counted the circuit of each packets of information as above-mentioned memory access according to the base address of this block at first memory of each data segment,

Be used for when each packets of information is sent out, setting up one merge the block verification and and be used for after the final data section of said block is read, the final circuit that merges verification and count the packets of information that shows this block end.

Said separation (unpacking) device comprises:

Be used for from received packets of information, obtaining being used for the offset address of data segment, according to said skew and base address calculate memory address and with data segment write said memory address circuit and

The circuit that is provided is used for producing one and transmits employed negative response packets of information and produce an employed affirmative acknowledgement packets of information in the equalized signals incident in non-equalized signals incident.

10, a kind of device that terminal part is connected to packet switching network, used desired this packets of information in claim 1 or 2, this device is used for transmitting and receiving swap data between the storage buffer by this network, and it is included in desired merging in claim 8 or 9 (dress bag) and separates (unpacking) device.

11, in the exchange of the pointed packets of information of claim 2, wherein this information be surrounded by one comprise the title of loop address field and type field and therein this packet length information be the several times of length for heading, it is improved to:

Each crosspoint can be from deleting packets of information to the loop of upstream crosspoint addressing, unless this packets of information protected by the address and/or the type field of a modification,

Busy crosspoint is incorporated into the packets of information that this loop is returned in attempt with such modification,

All crosspoints with such correction be incorporated into by they produce and in the packets of information of upstream units addressing and

In the loop, checkpoint is included in the first crosspoint place, loop or in its front, thereby by through the above-mentioned modification of deletion in the packets of information here.

12, in the packets of information exchange of claim 11, wherein improvement is:

Aforementioned correction realizes by the set of round Q-character in the type field of packets of information or bit, and owing to resetting of said round Q-character eliminated

Hope to other crosspoint of the broadcasting group addressing of other unit that has a single packets of information at built-in needed (RTB) Q-character of broadcasting of type field or bit and to go to checkpoint be the packet addressing of cancellation RTB Q-character and replacement broadcast feature position

All crosspoints duplicate all broadcast message bags from this loop and by they next unit to the loop, the broadcast message bag is removed from the loop by checkpoint,

By before it, by replacing the address of checkpoint with the address of busy unit oneself, the busy unit of receiving broadcasting information bag changes paying originally of broadcast message bag or it, and it will not received by the unit of back like this,

Received busy unit, the front of containing itself address and amended broadcast message bag the output of this packet replication, be sent to the next unit in this loop with its address of replacement, address of this checkpoint and the broadcast message bag that will be restored to it.

13, offer the packets of information interchanger that aforementioned any claim middle finger that type information bag described in aforementioned any claim uses goes out pattern, this interchanger has a plurality of crosspoints in loop that are connected to so that transmit packets of information around this loop from one to another ground, each crosspoint be suitable for from a junction associated that is used to transmit to other unit input information bag and from this loop to above-mentioned node output information bag, each crosspoint comprises:

A loop input and a loop output and a variable-length and retainable maintenance fifo buffer and the full detail bag that between input of said loop and loop output, connects,

One is connected to loop input and suitable identical with packet header length at least receiving register to junction associated output information bag,

One commutative is connected to the output register of loop output, and be used to transmit packets of information and be input to crosspoint from junction associated,

And control logic device, be used for:

The title of each packets of information that enters is read into receiving register,

Realize the transmission of top packets of information from the output register to the loop,

Be implemented to of the transmission of the packets of information that enters of described element address to junction associated,

Be scavenged into the packets of information of upstream units addressing,

Be sent to the packets of information of downstream units addressing or be buffered in keep among the FIFO after packets of information, up to the transmission of finishing an initial information bag be used for

Except when when realizing the modification of described packet header, can not be sent to junction associated to the packets of information of described element address beyond, this packets of information will be cushioned to guarantee their return loops, transmit said packets of information then to this loop output.

14, a packets of information interchanger according to claim 13, wherein this loop is that a wide serial loop and a crosspoint of 1 bit is separated on the telecommunication conductor of loop regionally, it is characterized in that each crosspoint comprises directly (not delay) line in parallel with said maintenance FIFO, like this, if an initial information bag does not shift out the loop, packets of information that enters will directly enter loop output and control logic wherein and immediately the packets of information of a correction be packed into the loop from keeping FIFO after crosspoint enters the loop in the initial part of that packets of information.

15, according to a packets of information interchanger of claim 13, interchanger wherein is a mini-plant part, loop wherein be one at least with title in the parallel loop of the same multi-thread number of bit number.

16, according to claim 13, a packets of information interchanger of 14 or 15, thereby it is characterized in that wherein not near crosspoint between be provided with one or more loops and connect and make the unit got involved by bypass and wherein be in by the control logic of the upstream units of bypass condition and be implemented to by of the exchange of the packets of information of downstream, the unit addressing of other crosspoint of bypass to other unit, utilization is selected to be sent to the loop by the packets of information of bypass by the control logic of the downstream termination point place crosspoint of bypass.

17, packet switching network is characterized in that using the packet format of the regular length of a title that contains an initial address field and a type field, and wherein the length of packets of information is the integral multiple of length for heading.

18, packet switching network is characterized in that having used the desired the sort of packets of information of aforesaid right requirement, packets of information interchanger, packets of information crosspoint and/or crosspoint interface device.

19, for contain title, short and the plug-type packets of information interchanger of the employed full buffer of regular length packets of information, loop configuration and register is characterized by the loop and has the as many parallel line of the bit number that resembles in title at least.

20, the arbitrary characteristic that includes in specification or claim or here in fact set forth or the packets of information interchanger of a plurality of characteristics, crosspoint, switching method and/or network all belong to the present invention.