CN103794570A - Chip packaging structure and manufacturing method of circuit board for packaging - Google Patents
Chip packaging structure and manufacturing method of circuit board for packaging Download PDFInfo
- Publication number
- CN103794570A CN103794570A CN201210495592.XA CN201210495592A CN103794570A CN 103794570 A CN103794570 A CN 103794570A CN 201210495592 A CN201210495592 A CN 201210495592A CN 103794570 A CN103794570 A CN 103794570A
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- Prior art keywords
- chip
- heat conduction
- heat
- projection
- bonding area
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- Pending
Links
- 238000004806 packaging method and process Methods 0.000 title claims abstract description 38
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 19
- 238000000034 method Methods 0.000 claims abstract description 18
- 229920002120 photoresistant polymer Polymers 0.000 claims description 34
- 238000003466 welding Methods 0.000 claims description 34
- 238000007789 sealing Methods 0.000 claims description 18
- 238000000059 patterning Methods 0.000 claims description 14
- 239000013078 crystal Substances 0.000 claims description 9
- 229910000679 solder Inorganic materials 0.000 claims description 9
- 239000000463 material Substances 0.000 claims description 8
- 238000007747 plating Methods 0.000 claims description 4
- 239000004593 Epoxy Substances 0.000 claims description 3
- 239000002184 metal Substances 0.000 claims description 3
- 150000001875 compounds Chemical class 0.000 claims description 2
- 238000005538 encapsulation Methods 0.000 description 11
- 238000001816 cooling Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000015654 memory Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap
Landscapes
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
The invention discloses a chip packaging structure and a manufacturing method of a circuit board for packaging. The chip packaging structure comprises a circuit board, a chip structure and a heat conducting cover. The circuit board is provided with a chip joint area, a heat conduction joint area which is not overlapped with the chip joint area, a conductive pattern, a heat conduction pattern, a plurality of conductive pseudo-convex blocks, a plurality of first heat conduction pseudo-convex blocks and a plurality of second heat conduction pseudo-convex blocks. The conductive pattern is located in the chip bonding region. The thermally conductive pattern extends from the die bond pad to the thermally conductive bond pad. The conductive dummy bump and the first conductive dummy bump are located in the chip bonding region, and the second conductive dummy bump is located in the conductive bonding region. The chip structure is electrically coupled to the conductive dummy bumps and thermally coupled to the first conductive dummy bumps. The heat conducting cover covers the chip structure and is thermally coupled to the second heat conducting pseudo-bumps. A method for manufacturing the circuit board for packaging the chip packaging structure is also provided.
Description
Technical field
The present invention relates to a kind of encapsulating structure and wiring board manufacture method, and particularly relate to the manufacture method of a kind of chip-packaging structure and sealing wire road plate thereof.
Background technology
In semiconductor industry, the production of integrated circuit (Integrated Circuits, IC), is mainly divided into two stages: the making of integrated circuit and the encapsulation of integrated circuit etc.Bare chip completes via steps such as wafer (Wafer) making, circuit design, photomask making and cut crystals, and each bare chip being formed by wafer cutting, after being electrically connected with external signal via the weld pad on bare chip, then with adhesive material, bare chip is being coated.The object of encapsulation is to prevent that bare chip is subject to the impact of moisture, heat, noise, and provides bare chip and external circuit, such as and printed circuit board (PCB) or other sealing wire base boards between the medium that is electrically connected, so complete the encapsulation step of integrated circuit.
In order to connect above-mentioned bare chip and sealing wire base board, conventionally can use wire or projection as the medium engaging.Along with the increase of chip integration, multi-chip module (Multi-Chip Module, MCM) encapsulation becomes the main trend of following encapsulation kenel gradually.Multi-chip module encapsulation can be by multiple chip-stacked being encapsulated on a sealing wire base board.But, in the encapsulation of above-mentioned multi-chip module, due to multiple arrangements of chips closely and when operation each chip all can produce heat, the heat that therefore produced encapsulates much higherly more than one chip.If can not effectively solve the heat dissipation problem of multi-chip module, will cause module excess Temperature, finally can cause chip to operate.Therefore, how to improve the important topic that radiating efficiency is multi-chip module encapsulation.
Summary of the invention
The object of the present invention is to provide a kind of chip-packaging structure, it has high cooling efficiency.
A further object of the present invention is to provide the manufacture method of a kind of sealing wire road plate, and its produced sealing wire road plate can help encapsulation chip cooling thereon.
For reaching above-mentioned purpose, the present invention proposes a kind of chip-packaging structure, and it comprises a wiring board, a chip structure and a conductive cover.Wiring board has a chip bonding area, is not overlapped in a heat conduction bonding land of chip bonding area, a conductive pattern, a heat conducting pattern, multiple conduction are intended projection, projections are intended in multiple the first heat conduction and projection is intended in multiple the second heat conduction.Conductive pattern is positioned at chip bonding area.Heat conducting pattern extends to heat conduction bonding land from chip bonding area.Conduction intends projection and the first heat conduction plan projection is positioned at chip bonding area, and the second heat conduction plan projection is positioned at heat conduction bonding land.Chip structure is electrically coupled to conduction and intends projection, and heat is coupled to the first heat conduction plan projection.Conductive cover covers in chip structure, and heat is coupled to the second heat conduction plan projection.
The present invention proposes a kind of sealing wire road board fabrication method, and it comprises the following steps.First, provide a wiring board.Wiring board has a chip bonding area, is not overlapped in a heat conduction bonding land, a heat conducting pattern and a welding resisting layer of chip bonding area.Heat conducting pattern extends to heat conduction bonding land from chip bonding area.Welding resisting layer has at least one the first anti-welding opening and at least one the second anti-welding opening.The first anti-welding opening exposes the part heat conducting pattern of position in chip bonding area, and the second anti-welding opening exposes the part heat conducting pattern of position in heat conduction bonding land.Then, form a patterning photoresist layer on welding resisting layer.Patterning photoresist layer has one first photoresist opening and one second photoresist opening.The first photoresist opening and the second photoresist opening expose respectively the first anti-welding opening and the second anti-welding opening.Fill Heat Conduction Material in the first photoresist opening and the second photoresist opening, to form, projection is intended in one first heat conduction and projection is intended in one second heat conduction simultaneously.Then, remove patterning photoresist layer.
Based on above-mentioned, the present invention is divided into wiring board the chip bonding area and the heat conduction bonding land that do not overlap each other, and utilization is extended to the heat conducting pattern of heat conduction bonding land and is intended projection with the first heat conduction that its heat couples by chip bonding area, the heat energy that chip structure is produced conducts to the second heat conduction plan projection that is positioned at heat conduction bonding land from chip bonding area, again by with the second heat conduction intend conductive cover that projection heat couples by thermal energy conduction to outside, to dispel the heat.Therefore, the invention provides the extra heat conduction path of chip structure, and then improve the radiating efficiency of chip-packaging structure.
For above-mentioned feature and advantage of the present invention can be become apparent, special embodiment below, and coordinate appended accompanying drawing to be described in detail below.
Accompanying drawing explanation
Fig. 1 is the partial cutaway schematic of a kind of chip-packaging structure of one embodiment of the invention;
Fig. 2 is that the chip-packaging structure of Fig. 1 is in the local enlarged diagram of region A;
Fig. 3 is a kind of chip bonding area of wiring board and the schematic top plan view of heat conduction bonding land of one embodiment of the invention;
Fig. 4 is a kind of chip bonding area of wiring board and the schematic top plan view of heat conduction bonding land of another embodiment of the present invention;
Fig. 5 A to Fig. 5 F is the generalized section of a kind of sealing wire road board fabrication method of one embodiment of the invention.
Main element symbol description
100: chip-packaging structure
110: wiring board
111: chip bonding area
112: heat conduction bonding land
113: conductive pattern
114: heat conducting pattern
115: conduction is intended projection
Projection is intended in heat conduction in 116: the first
Projection is intended in heat conduction in 117: the second
120: chip structure
130: conductive cover
132: shoulder
140: solder projection
150: heat-conducting layer
160: radiating fin
170: welding resisting layer
172: the first anti-welding openings
174: the second anti-welding openings
180: patterning photoresist layer
182: the first photoresist openings
184: the second photoresist openings
190: electroplate inculating crystal layer
Embodiment
Fig. 1 is the partial cutaway schematic according to a kind of chip-packaging structure of one embodiment of the invention.Fig. 2 is that the chip-packaging structure of Fig. 1 is in the local enlarged diagram of region A.Referring to Fig. 1 and Fig. 2, in the present embodiment, chip-packaging structure 100 comprises a wiring board 110, a chip structure 120 and a conductive cover 130.Wiring board 110 has a chip bonding area 111, is not overlapped in a heat conduction bonding land 112 of chip bonding area 111, a conductive pattern 113, a heat conducting pattern 114, multiple conduction are intended projection 115, projections 116 are intended in multiple the first heat conduction and projection 117 is intended in multiple the second heat conduction.Conductive pattern 113 is positioned at chip bonding area 111, and in other embodiments of the invention, conductive pattern 113 also can be extended to outside chip bonding area 111 by chip bonding area 111, to be electrically connected with other external circuits.114 of heat conducting pattern extend to heat conduction bonding land 112 from chip bonding area 111.
Fig. 3 is the schematic top plan view according to the chip bonding area of a kind of wiring board of one embodiment of the invention and heat conduction bonding land.Fig. 4 is the schematic top plan view according to the chip bonding area of a kind of wiring board of another embodiment of the present invention and heat conduction bonding land.In the present embodiment, the chip bonding area 111 of wiring board 110 and heat conduction bonding land 112 can mode as shown in Figure 3 configure, and this means, heat conduction bonding land 112 is around surrounding's setting of chip bonding area 111, and heat conduction bonding land 112 is not overlapping with chip bonding area 111.In addition, the chip bonding area 111 of wiring board 110 and heat conduction bonding land 112 also can mode as shown in Figure 4 configure, and this means, heat conduction bonding land 112 is discontinuously around chip bonding area 111.In the embodiment that other do not illustrate of the present invention, heat conduction bonding land 112 more can only be arranged at chip bonding area 111 a wherein side and not around chip bonding area 111.Should be noted that at this, Fig. 3 and Fig. 4 are only in order to illustrate, and the present invention does not limit the relation that arranges between heat conduction bonding land 112 and chip bonding area 111.As long as heat conduction bonding land 112 is not overlapping with chip bonding area 111, and can make heat conducting pattern 114 extend to heat conduction bonding land from chip bonding area 111, all in protection scope of the present invention.
Actual, conductive pattern 113 and heat conducting pattern 114 can be same patterned metal layer, that is to say, conductive pattern 113 and heat conducting pattern 114 can be formed via patterning step by same metal level simultaneously.In the present embodiment, heat conducting pattern 114 is for example dummy pattern (dummy pattern) or grounding pattern, and this means, heat conducting pattern 114 not can be and makees with All other routes the pattern being electrically connected, or the pattern being connected with the potential reference point of wiring board 110.As shown in Figure 2, conduction intends projection 115 and the first heat conduction plan projection 116 is positioned at chip bonding area 111, and the second heat conduction plan projection 117 is positioned at heat conduction bonding land 112.In the present embodiment, chip-packaging structure, more comprises multiple solder projections 140, and chip structure 120 can be connected to conduction via solder projection 140 and intend projection 115 and the first heat conduction plan projection 116.So, chip structure 120 can be electrically coupled to conduction via part solder projection 140 and intend projection 115, and is coupled to the first heat conduction plan projection 116 via other solder projection 140 heat.
Hold above-mentionedly, conductive cover 130 covers in chip structure 120, and heat is coupled to the second heat conduction and intends projection 117.In the present embodiment, conductive cover 130 can be coupled to the second heat conduction via heat-conducting layer 150 heat and intend projection 117, and wherein, the material of heat-conducting layer 150 comprises the Heat Conduction Material such as epoxy compounds (epoxy) or scolder (solder).Specifically, conductive cover 130 can have a shoulder 132, and shoulder 132 heat are overlapped on the edge of chip structure 120, and the heat energy that therefore chip structure 120 produces also can conduct to conductive cover 130 by shoulder 132, i.e. another heat conduction path.In addition, chip-packaging structure 100 more comprises at least one radiating fin 160, and it is connected with conductive cover 130, and the heat energy that chip is produced can conduct to conductive cover 130, then dissipates to outside via radiating fin 160.In the present embodiment, chip structure 120 can comprise sequentially stacking multiple chips, and in other words, chip structure 120 can be a multi-chip stacking structure.Particularly, the Multichip stacking encapsulation of the present embodiment can comprise multiple Dynamic Random Access Memories (dynamic random access memory, DRAM) chip and a logic chip.Generally speaking, logic chip be in chip structure 120 from the nearest chip of wiring board 110, and the heat energy that the heat energy that logic chip produces produces compared with dram chip is conventionally large.So, the heat conduction path that the heat energy producing from the nearest chip of wiring board 110 just can form by the first heat conduction plan projection 116, heat conducting pattern 114 and the second heat conduction plan projection 117 to conductive cover 130, up conducts to heat energy and reduce by multiple chips of its top the conductive cover 130 that covers chip structure 120 by thermal energy conduction.
So arrange, the heat energy that chip structure 120 produces, can via with its heat couple first heat conduction intend projection 116 conduct to heat conducting pattern 114, and heat conducting pattern 114 conducts to heat energy the second heat conduction that is positioned at heat conduction bonding land 112 again and intends projection 117 from chip bonding area 111, then via with the second heat conduction intend conductive cover 130 that projection 117 heat couple by thermal energy conduction to outside.Therefore, the present embodiment provides chip-packaging structure 100 another heat conduction paths, and then has promoted the radiating efficiency of chip-packaging structure 100.
Fig. 5 A to Fig. 5 F is the generalized section according to a kind of sealing wire road board fabrication method of one embodiment of the invention.It should be noted that at this, the present embodiment only in order to illustrate previous embodiment chip-packaging structure 100 part make flow process, namely in previous embodiment in order to encapsulation wiring board part make flow process.First the sealing wire road board fabrication method of the present embodiment comprises the following steps:, a wiring board 110 is as shown in Figure 5A provided.Wiring board 110 has a chip bonding area 111, is not overlapped in a heat conduction bonding land 112, a heat conducting pattern 114 and a welding resisting layer 170 of chip bonding area 111.Heat conducting pattern 114 extends to heat conduction bonding land 112 from chip bonding area 111.Welding resisting layer 170 has at least one the first anti-welding opening 172 and at least one the second anti-welding opening 174, wherein, the first anti-welding opening 172 exposes the part heat conducting pattern 114 of position in chip bonding area 111, and the second anti-welding opening 174 exposes the part heat conducting pattern 114 of position in heat conduction bonding land 112.
Hold above-mentionedly, please continue with reference to Fig. 5 B, form one and electroplate inculating crystal layer 190, wherein, electroplate inculating crystal layer 190 overlay pattern photoresist layers 180 and the heat conducting pattern 114 that is exposed on.Then, more as shown in Figure 5 C, form a patterning photoresist layer 180 in welding resisting layer 170 and cover on the plating inculating crystal layer 190 of welding resisting layer 170.Patterning photoresist layer 180 has one first photoresist opening 182 and one second photoresist opening 184.The first photoresist opening 182 and the second photoresist opening 184 expose respectively the first anti-welding opening 172 and the second anti-welding opening 174.Then, referring again to Fig. 5 D, electroplate by electroplating inculating crystal layer 190, to fill Heat Conduction Material in the first photoresist opening 182 and the second photoresist opening 184 simultaneously, to form, projection 116 is intended in one first heat conduction and projection 117 is intended in one second heat conduction.Then, referring to Fig. 5 E and Fig. 5 F, remove patterning photoresist layer 180, afterwards, then remove on welding resisting layer 170 and not intended projection 116 by the first heat conduction and the parcel plating inculating crystal layer 190 that projection 117 is covered is intended in the second heat conduction.So, complete the first heat conduction in chip-packaging structure 100 simultaneously and intend projection 116 and the second heat conduction and intend the making of projection 117.In the present embodiment, conduction plan projection 115 can form with the first heat conduction plan projection 116 and the second heat conduction plan projection 117 simultaneously.
In sum, the present invention is divided into wiring board the chip bonding area and the heat conduction bonding land that do not overlap each other, and utilization is extended to the heat conducting pattern of heat conduction bonding land and is intended projection with the first heat conduction that its heat couples by chip bonding area, the heat energy that chip structure is produced conducts to the second heat conduction plan projection that is positioned at heat conduction bonding land from chip bonding area, again by with the second heat conduction intend conductive cover that projection heat couples by thermal energy conduction to outside, to dispel the heat.Therefore, the invention provides the extra heat conduction path of chip structure, and then improve the radiating efficiency of chip-packaging structure.
Although disclosed the present invention in conjunction with above embodiment; but it is not in order to limit the present invention; under any, in technical field, be familiar with this operator; without departing from the spirit and scope of the present invention; can do a little change and retouching, thus protection scope of the present invention should with enclose claim was defined is as the criterion.
Claims (20)
1. a chip-packaging structure, comprising:
Wiring board, projection is intended in the heat conduction bonding land, conductive pattern, heat conducting pattern, multiple conduction that have chip bonding area, is not overlapped in this chip bonding area, projections are intended in multiple the first heat conduction and projection is intended in multiple the second heat conduction, this conductive pattern is positioned at this chip bonding area, this heat conducting pattern extends to this heat conduction bonding land from this chip bonding area, those conductions intend projection and those the first heat conduction plan projection is positioned at this chip bonding area, and those second heat conduction plan projections are positioned at this heat conduction bonding land;
Chip structure, is electrically coupled to those conductions and intends projection, and heat is coupled to those first heat conduction plan projections; And
Conductive cover, covers in this chip structure, and heat is coupled to those second heat conduction plan projections.
2. chip-packaging structure as claimed in claim 1, wherein this heat conducting pattern is dummy pattern (dummy pattern) or grounding pattern.
3. chip-packaging structure as claimed in claim 1, wherein this conductive pattern and this heat conducting pattern are same patterned metal layer.
4. chip-packaging structure as claimed in claim 1, wherein this conductive cover has a shoulder, and this shoulder heat is overlapped on the edge of this chip structure, and forms another heat conduction path.
5. chip-packaging structure as claimed in claim 1, also comprises:
Multiple solder projections, this chip structure is electrically coupled to those conductions via those solder projections of part and intends projection, and this chip structure is coupled to those first heat conduction plan projections via other those solder projection heat.
6. chip-packaging structure as claimed in claim 1, also comprises:
Multiple heat-conducting layers, this conductive cover is coupled to those second heat conduction via those heat-conducting layer heat and intends projection.
7. chip-packaging structure as claimed in claim 6, wherein the material of those heat-conducting layers comprises epoxy compounds or scolder.
8. chip-packaging structure as claimed in claim 1, wherein this heat conduction bonding land is around surrounding's setting of this chip bonding area.
9. chip-packaging structure as claimed in claim 1, wherein this heat conduction bonding land is discontinuously around surrounding's setting of this chip bonding area.
10. chip-packaging structure as claimed in claim 1, wherein this heat conduction bonding land is arranged at a wherein side of this chip bonding area.
11. chip-packaging structures as claimed in claim 1, wherein this chip structure comprises sequentially stacking multiple chips.
12. chip-packaging structures as claimed in claim 11, wherein this chip structure comprises a logic chip, this logic chip is from the nearest chip of this wiring board in those chips.
13. chip-packaging structures as claimed in claim 1, also comprise:
At least one radiating fin, is connected with this conductive cover.
14. 1 kinds of sealing wire road board fabrication methods, comprising:
One wiring board is provided, this wiring board has chip bonding area, is not overlapped in heat conduction bonding land, heat conducting pattern and the welding resisting layer of this chip bonding area, this heat conducting pattern extends to this heat conduction bonding land from this chip bonding area, this welding resisting layer has at least one the first anti-welding opening and at least one the second anti-welding opening, this first anti-welding opening exposes position this heat conducting pattern of part in this chip bonding area, and this second anti-welding opening exposes position this heat conducting pattern of part in this heat conduction bonding land;
Form a patterning photoresist layer on this welding resisting layer, this patterning photoresist layer has the first photoresist opening and the second photoresist opening, and this first photoresist opening and this second photoresist opening expose respectively this first anti-welding opening and this second anti-welding opening;
Fill Heat Conduction Material in this first photoresist opening and this second photoresist opening, to form, projection is intended in one first heat conduction and projection is intended in one second heat conduction simultaneously; And
Remove this patterning photoresist layer.
15. sealing wire as claimed in claim 14 road board fabrication methods, wherein those heat conducting pattern are dummy pattern (dummy pattern) or grounding pattern.
16. sealing wire as claimed in claim 14 road board fabrication methods, also comprise:
Form this patterning photoresist layer on this welding resisting layer before, form one and electroplate inculating crystal layer, cover this patterning photoresist layer and this heat conducting pattern of being exposed on; And
After removing this patterning photoresist layer, remove on this welding resisting layer and do not intended by this first heat conduction plan projection and this second heat conduction this plating inculating crystal layer of part that projection covered.
17. sealing wire as claimed in claim 14 road board fabrication methods, wherein fill the step of this Heat Conduction Material in this first thermal hole and this second thermal hole simultaneously and comprise plating.
18. sealing wire as claimed in claim 14 road board fabrication methods, wherein this heat conduction bonding land is around surrounding's setting of this chip bonding area.
19. sealing wire as claimed in claim 14 road board fabrication methods, wherein this heat conduction bonding land is discontinuously around surrounding's setting of this chip bonding area.
20. sealing wire as claimed in claim 14 road board fabrication methods, wherein this heat conduction bonding land is arranged at a wherein side of this chip bonding area.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW101139966A TW201417649A (en) | 2012-10-29 | 2012-10-29 | Chip package structure and fabricating method of circuit board for packaging |
| TW101139966 | 2012-10-29 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN103794570A true CN103794570A (en) | 2014-05-14 |
Family
ID=50670101
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201210495592.XA Pending CN103794570A (en) | 2012-10-29 | 2012-11-28 | Chip packaging structure and manufacturing method of circuit board for packaging |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN103794570A (en) |
| TW (1) | TW201417649A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20230017688A1 (en) * | 2021-07-16 | 2023-01-19 | Taiwan Semiconductor Manufacturing Company, Ltd. | Chip package structure and method for forming the same |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5619070A (en) * | 1993-12-28 | 1997-04-08 | Kabushiki Kaisha Toshiba | Semiconductor device which radiates heat and applies substrate potential from rear surface of semiconductor chip |
| TW200824072A (en) * | 2006-11-21 | 2008-06-01 | Chipmos Technologies Inc | Carrier film and semiconductor package improving thermal dissipation |
| US20100142155A1 (en) * | 2008-12-04 | 2010-06-10 | Lsi Corporation | Preferentially Cooled Electronic Device |
-
2012
- 2012-10-29 TW TW101139966A patent/TW201417649A/en unknown
- 2012-11-28 CN CN201210495592.XA patent/CN103794570A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5619070A (en) * | 1993-12-28 | 1997-04-08 | Kabushiki Kaisha Toshiba | Semiconductor device which radiates heat and applies substrate potential from rear surface of semiconductor chip |
| TW200824072A (en) * | 2006-11-21 | 2008-06-01 | Chipmos Technologies Inc | Carrier film and semiconductor package improving thermal dissipation |
| US20100142155A1 (en) * | 2008-12-04 | 2010-06-10 | Lsi Corporation | Preferentially Cooled Electronic Device |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20230017688A1 (en) * | 2021-07-16 | 2023-01-19 | Taiwan Semiconductor Manufacturing Company, Ltd. | Chip package structure and method for forming the same |
| US11728284B2 (en) * | 2021-07-16 | 2023-08-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Chip package structure and method for forming the same |
Also Published As
| Publication number | Publication date |
|---|---|
| TW201417649A (en) | 2014-05-01 |
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Application publication date: 20140514 |