CN103794499B - Fin field effect pipe and forming method thereof - Google Patents
Fin field effect pipe and forming method thereof Download PDFInfo
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- CN103794499B CN103794499B CN201210422891.0A CN201210422891A CN103794499B CN 103794499 B CN103794499 B CN 103794499B CN 201210422891 A CN201210422891 A CN 201210422891A CN 103794499 B CN103794499 B CN 103794499B
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- 230000005669 field effect Effects 0.000 title claims abstract description 78
- 238000000034 method Methods 0.000 title claims abstract description 52
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 181
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 181
- 239000010703 silicon Substances 0.000 claims abstract description 181
- 238000000926 separation method Methods 0.000 claims abstract description 69
- 239000000758 substrate Substances 0.000 claims abstract description 22
- 239000012212 insulator Substances 0.000 claims abstract description 19
- 230000015572 biosynthetic process Effects 0.000 claims description 29
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 18
- 239000000463 material Substances 0.000 claims description 16
- 230000008569 process Effects 0.000 claims description 16
- -1 SiCN Inorganic materials 0.000 claims description 9
- 239000000377 silicon dioxide Substances 0.000 claims description 9
- 238000005516 engineering process Methods 0.000 claims description 8
- 230000003647 oxidation Effects 0.000 claims description 8
- 238000007254 oxidation reaction Methods 0.000 claims description 8
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 6
- 229910004541 SiN Inorganic materials 0.000 claims description 5
- 229910003481 amorphous carbon Inorganic materials 0.000 claims description 5
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims description 2
- 229910052799 carbon Inorganic materials 0.000 claims description 2
- 238000005530 etching Methods 0.000 description 11
- 230000008859 change Effects 0.000 description 9
- 238000002955 isolation Methods 0.000 description 6
- 239000004065 semiconductor Substances 0.000 description 6
- 239000007789 gas Substances 0.000 description 5
- 150000002500 ions Chemical class 0.000 description 5
- 229910010271 silicon carbide Inorganic materials 0.000 description 5
- 125000006850 spacer group Chemical group 0.000 description 5
- 238000001020 plasma etching Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000000007 visual effect Effects 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 239000003989 dielectric material Substances 0.000 description 2
- 238000009826 distribution Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000000407 epitaxy Methods 0.000 description 2
- 229910000449 hafnium oxide Inorganic materials 0.000 description 2
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 description 2
- 239000001257 hydrogen Substances 0.000 description 2
- 229910052739 hydrogen Inorganic materials 0.000 description 2
- 230000001788 irregular Effects 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- 229910003978 SiClx Inorganic materials 0.000 description 1
- 229910004481 Ta2O3 Inorganic materials 0.000 description 1
- MCMNRKCIXSYSNV-UHFFFAOYSA-N ZrO2 Inorganic materials O=[Zr]=O MCMNRKCIXSYSNV-UHFFFAOYSA-N 0.000 description 1
- UMVBXBACMIOFDO-UHFFFAOYSA-N [N].[Si] Chemical compound [N].[Si] UMVBXBACMIOFDO-UHFFFAOYSA-N 0.000 description 1
- DUFGEJIQSSMEIU-UHFFFAOYSA-N [N].[Si]=O Chemical compound [N].[Si]=O DUFGEJIQSSMEIU-UHFFFAOYSA-N 0.000 description 1
- 229910001439 antimony ion Inorganic materials 0.000 description 1
- HAYXDMNJJFVXCI-UHFFFAOYSA-N arsenic(5+) Chemical compound [As+5] HAYXDMNJJFVXCI-UHFFFAOYSA-N 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 229910052797 bismuth Inorganic materials 0.000 description 1
- JCXGWMGPZLAOME-UHFFFAOYSA-N bismuth atom Chemical compound [Bi] JCXGWMGPZLAOME-UHFFFAOYSA-N 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- MROCJMGDEKINLD-UHFFFAOYSA-N dichlorosilane Chemical compound Cl[SiH2]Cl MROCJMGDEKINLD-UHFFFAOYSA-N 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(IV) oxide Inorganic materials O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 description 1
- 150000002431 hydrogen Chemical class 0.000 description 1
- 229910001449 indium ion Inorganic materials 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 230000001105 regulatory effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
- H01L29/7855—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with at least two independent gates
Abstract
A kind of fin field effect pipe and forming method thereof, wherein, the fin field effect pipe includes：Silicon-on-insulator substrate, the silicon-on-insulator substrate include top silicon layer, bottom silicon layer and the buried layer between top silicon layer and bottom silicon layer, top silicon layer as fin field effect pipe fin；The second opening of layer surface is buried in exposure in top silicon layer；Positioned at the first separation layer of the side wall of the second opening；The 3rd opening of exposure bottom silicon surface in buried layer, the position of the 3rd opening is corresponding with the position of the second opening；The silicon epitaxial layers of full second opening of filling and the 3rd opening, the top surface of silicon epitaxial layers is higher than the surface of top silicon layer, and silicon epitaxial layers and bottom silicon layer constitute backgate；Positioned at the second separation layer of the top surface of silicon epitaxial layers；Side wall positioned at the surface of the side wall and top silicon layer of the second separation layer and portion of epi silicon layer.When applying voltage in backgate, the threshold voltage of fin field effect pipe is easily controlled.
Description
Technical field
The present invention relates to field of semiconductor fabrication, more particularly to a kind of fin field effect pipe and forming method thereof.
Background technology
With continuing to develop for semiconductor process technique, as process node is gradually reduced, rear grid（gate-last）Technique
It is widely applied, to obtain preferable threshold voltage, improves device performance.But when the characteristic size of device（CD,
Critical Dimension）When further declining, even if using rear grid technique, the structure of conventional metal-oxide-semiconductor field effect transistor is also
Through the demand to device performance, fin formula field effect transistor can not be met（Fin FET）Obtained as the replacement of conventional device
Extensive concern.
Fig. 1 shows a kind of dimensional structure diagram of fin formula field effect transistor of prior art.As shown in figure 1, bag
Include：It is formed with the fin 14 of protrusion in Semiconductor substrate 10, the Semiconductor substrate 10, fin 14 is generally by half-and-half leading
What body substrate 10 was obtained after etching；Dielectric layer 11, covers the one of the surface of the Semiconductor substrate 10 and the side wall of fin 14
Part；Grid structure 12, across top and the side wall on the fin 14, covering the fin 14, grid structure 12 includes
Gate dielectric layer（Not shown in figure）With the gate electrode on gate dielectric layer（Not shown in figure）.
More United States Patent (USP)s that Patent No. " US7868380B2 " is refer on fin formula field effect transistor.
But with the continuous reduction of device size, the more difficult control of threshold voltage of fin formula field effect transistor.
The content of the invention
The problem of present invention is solved is the threshold voltage of preferable control fin field effect pipe.
To solve the above problems, technical solution of the present invention provides a kind of forming method of fin field effect pipe, including：Carry
For silicon-on-insulator substrate, the silicon-on-insulator substrate includes top silicon layer, bottom silicon layer and positioned at top silicon layer and bottom
Buried layer between silicon layer；Hard mask layer is formed on the top silicon layer surface, the hard mask layer has exposed top layer silicon layer
First opening on surface；Along the first opening, the top silicon layer is etched, exposure second opening for burying layer surface is formed；
In side wall the first separation layer of formation of the described second opening；The buried layer is etched along the second opening, exposure bottom silicon layer is formed
3rd opening on surface；The full silicon epitaxial layers of filling, silicon epitaxial layers and bottom silicon in the first opening, the second opening and the 3rd opening
Layer constitutes backgate；In top surface the second separation layer of formation of the silicon epitaxial layers；Remove the hard mask layer, exposure described the
The side wall of two separation layers and portion of epi silicon layer；In the side wall and top of second separation layer and the portion of epi silicon layer of exposure
The surface of layer silicon layer forms side wall；Using the side wall as mask, the top silicon layer is etched, is formed around the silicon epitaxial layers
Fin.
Optionally, the thickness of the hard mask layer is more than or equal to 20 nanometers.
Optionally, the hard mask layer is one or more layers the heap in amorphous carbon, SiN, SiON, SiCN, SiC or BN
Stack structure.
Optionally, the width of the side wall is more than or equal to 10 nanometers.
Optionally, the side wall is one or more layers the stacking knot in amorphous carbon, SiN, SiON, SiCN, SiC or BN
Structure.
Optionally, the material of first separation layer is silica, and the formation process of the first separation layer is thermal oxidation technology.
Optionally, the thickness of first separation layer is more than or equal to 10 angstroms.
Optionally, the material of second separation layer is silica, and the formation process of the second separation layer is thermal oxidation technology.
Optionally, the thickness of second separation layer is more than or equal to 30 angstroms.
Optionally, the foreign ion in the backgate also doped with N-type or p-type.
Optionally, in addition to：In the formation gate dielectric layer of the sidewall surfaces away from the first separation layer side of the fin；Shape
Into the gate electrode across the fin, the gate electrode covers the surface of the gate dielectric layer, the second separation layer and side wall.
Technical solution of the present invention additionally provides a kind of fin field effect pipe, including：Silicon-on-insulator substrate, the insulator
Upper silicon substrate includes top silicon layer, bottom silicon layer and the buried layer between top silicon layer and bottom silicon layer, and top silicon layer is made
For the fin of fin field effect pipe；Exposure second opening for burying layer surface in the top silicon layer；Positioned at described
First separation layer of the side wall of the second opening；The 3rd opening of exposure bottom silicon surface in the buried layer, the 3rd opens
The position of mouth is corresponding with the position of the second opening；The silicon epitaxial layers of filling full second opening and the 3rd opening, epitaxial silicon
The top surface of layer is higher than the surface of top silicon layer, and silicon epitaxial layers and bottom silicon layer constitute backgate；Positioned at the silicon epitaxial layers
Second separation layer of top surface；Positioned at the side wall and the surface of top silicon layer of second separation layer and portion of epi silicon layer
Side wall.
Optionally, the difference of the height on the top surface of the silicon epitaxial layers and top silicon layer surface is more than or equal to 20 nanometers.
Compared with prior art, technical solution of the present invention has advantages below：
The forming method of fin field effect pipe of the present invention, etches the top silicon layer and buried layer of silicon-on-insulator substrate, shape
Into the second opening and the 3rd opening of exposure bottom silicon surface, then full epitaxial silicon is filled in the second opening and the 3rd opening
Layer, silicon epitaxial layers and bottom silicon layer constitute backgate, then form the fin around the silicon epitaxial layers, and technical process is simple, and
And there is the first separation layer and buried layer between fin and backgate, improve the electric isolation performance between backgate and fin.
Further, the first separation layer and the second separation layer are formed by thermal oxidation technology, and processing step is simple, saved into
This.
There is exposure bottom silicon in the fin field effect pipe of the present invention, the top silicon layer and buried layer of silicon-on-insulator substrate
Full silicon epitaxial layers, silicon epitaxial layers and bottom are filled in the second opening and the 3rd opening of layer surface, the second opening and the 3rd opening
Silicon layer constitutes backgate, and remaining Portions of top layer silicon layer is as fin, and fin has around the silicon epitaxial layers between fin and backgate
There are the first separation layer and buried layer, due to the presence of backgate, when applying certain voltage in backgate, the voltage applied in backgate
The formation of inversion layer in fin can be influenceed so that the threshold voltage of fin field effect pipe produces change, as fin field effect plumber
When making, the gate voltage being applied on the grid structure of fin field effect pipe produces change accordingly, due to the presence of backgate so that
The threshold voltage of fin field effect pipe is related to both gate voltages on the voltage and grid structure that apply in backgate, therefore passes through
Regulation is applied to the size of voltage in backgate and positive and negative, can preferably control the threshold voltage of fin field effect pipe, and
Fin is around the silicon epitaxial layers（A part for backgate）, so that threshold voltage being evenly distributed along the surface of fin, separately
There is the first separation layer and buried layer between outer fin and backgate, will not be to fin field effect pipe when applying voltage in backgate
Electric property and working condition produce influence.
Brief description of the drawings
Fig. 1 is the structural representation of prior art fin field effect pipe；
Fig. 2 ~ Figure 14 is the structural representation of fin field effect pipe forming process of the embodiment of the present invention.
Embodiment
The more difficult control of threshold voltage of the FET of the fin field effect pipe of prior art formation.
Therefore, inventor proposes have in a kind of fin field effect pipe, the top silicon layer and buried layer of silicon-on-insulator substrate
Have in the second opening and the 3rd opening of exposed bottom silicon surface, the second opening and the 3rd opening and fill full silicon epitaxial layers, outside
Prolong silicon layer and bottom silicon layer constitutes backgate, remaining Portions of top layer silicon layer is as fin, and fin is around the silicon epitaxial layers, fin
There is the first separation layer and buried layer between backgate, due to the presence of backgate, by applying certain voltage in backgate,
When applying certain voltage in backgate, the voltage applied in backgate can influence the formation of inversion layer in fin, so that fin
The threshold voltage of FET produces change, when fin field effect pipe works, is applied to the grid structure of fin field effect pipe
On gate voltage produce change accordingly, due to the presence of backgate so that applied on the threshold voltage and backgate of fin field effect pipe
Plus voltage it is related to both gate voltages on grid structure, therefore be applied to by regulation the size and just of voltage in backgate
It is negative, it can preferably control the threshold voltage of fin field effect pipe.
In order to facilitate the understanding of the purposes, features and advantages of the present invention, below in conjunction with the accompanying drawings to the present invention
Embodiment be described in detail.When the embodiment of the present invention is described in detail, for purposes of illustration only, schematic diagram can disobey general ratio
Example makees partial enlargement, and the schematic diagram is example, and it should not be limited the scope of the invention herein.In addition, in reality
Border should include the three-dimensional space of length, width and depth in making.
Fig. 2 ~ Figure 14 is the structural representation of fin field effect pipe forming process of the embodiment of the present invention.
First, Fig. 2 and Fig. 3 be refer to, Fig. 3 is that Fig. 2 overlooks the structural representation at visual angle there is provided silicon-on-insulator substrate,
The silicon-on-insulator substrate include top silicon layer 303, bottom silicon layer 301 and positioned at top silicon layer 303 and bottom silicon layer 301 it
Between buried layer 302；Hard mask layer 304 is formed on the surface of top silicon layer 303, there is the hard mask layer 304 exposure to push up
First opening 305 on layer silicon layer 303 surface.
The silicon-on-insulator substrate（Silicon on insulator, SOI）Top silicon layer 303 be subsequently used for being formed
The fin of fin field effect pipe, bottom silicon layer 301 as backgate a part.
The hard mask layer 304 is one or more layers the stacking knot in amorphous carbon, SiN, SiON, SiCN, SiC or BN
Structure, hard mask layer 304 described in the present embodiment is SiN.
The thickness of the hard mask layer 304 is more than or equal to 20 nanometers so that the first opening formed in hard mask layer 304
305 depth is more than or equal to 20 nanometers, the second opening and buried layer subsequently in the first opening 305, top silicon layer 303
When filling full silicon epitaxial layers in the 3rd opening in 302 so that silicon epitaxial layers top surface and the difference in height on top silicon layer surface
More than or equal to 20 nanometers, when using the both sides side wall without mask plasma etching industrial in silicon epitaxial layers and the surface of top silicon layer
When forming side wall, the width of side wall is preferably controlled.
First opening 305 is formed by photoetching and etching technics in the hard mask layer 304, first opening 305
Cross section figure is rectangle, circular or other regular or irregular figures.It is mask etching institute subsequently with hard mask layer 304
Top silicon layer 303 and buried layer 302 are stated, second is formed in top silicon layer 303 and is open, the 3rd is formed in buried layer 302 and is opened
During mouth, the second opening is corresponding with the cross section figure of the 3rd opening and the cross section figure of the first opening 305, the first opening 305,
When second opening in the 3rd opening with filling full silicon epitaxial layers so that the cross section figure of the side wall of silicon epitaxial layers and the first opening
Cross section figure it is corresponding, be rectangle, circular or other regular or irregular figures.In the present embodiment, described first
305 cross section figure of opening is rectangle, and the cross section figure of the side wall for the silicon epitaxial layers being subsequently formed accordingly is also square
Shape.
It is mask with the hard mask layer 304 next referring to Fig. 4, along the first opening 305, etches the top silicon layer
303, form second opening 306 on the exposure surface of buried layer 302.
The plasma in process etching technics of the top silicon layer 303 is etched, what the plasma etch process was used
Gas is Cl2、NF3And SF6。
The shape of cross section of second opening 306 is identical with the shape of cross section of the first opening 305.
Then, Fig. 5 is refer to, in side wall the first separation layer 307 of formation of the described second opening 306.
First separation layer 307 is used for the follow-up silicon epitaxial layers and ring formed in the second opening 306 of electric isolation
Around the fin of the silicon epitaxial layers, prevent on silicon epitaxial layers（A part for backgate）When applying voltage, to fin field effect pipe
Electric property and working condition produce influence, the thickness of first separation layer 307 is more than or equal to 10 angstroms.
In the present embodiment, the material of first separation layer 307 is silica, and the first separation layer 307 passes through thermal oxide the
The Portions of top layer silicon layer 303 of exposure is formed in two openings 306, and processing step is simple, has saved cost.
In other embodiments of the invention, first separation layer is formed by deposition and etching technics, i.e., adopt first
With chemical vapor deposition method in the sidewall surfaces of the first opening, the side wall of the second opening and lower surface and hard mask layer
Surface forms spacer material layer；Then the spacer material layer is etched using without mask plasma etching technique, described the
Side wall the first separation layer of formation of two openings, the first isolation layer segment is located at the side wall of the first opening, the first separation layer
Material is silica, silicon nitride, silicon oxynitride, carborundum or nitrogen silicon oxide carbide, or other suitable materials.
In another embodiment of the invention, first separation layer includes：The oxygen of top silicon layer formation described in thermal oxide
Change layer, and the side wall formed positioned at oxidation layer surface by deposition-etch technique, to improve the isolation effect of the first separation layer.
Then, Fig. 6 is refer to, is mask with the hard mask layer 304, along the etching buried layer of the second opening 306
302, form the 3rd opening 308 on the surface of exposure bottom silicon layer 301.
The shape of cross section of 3rd opening 308 is identical with the shape of cross section of the second opening 306.
The technique for etching the buried layer 302 is plasma etch process, the gas that plasma etch process is used
For CHF3And He.
The step of etching the 3rd opening 308 of the formation of buried layer 302 is opened in the etching formation of top silicon layer 303 second
After mouth 306, the influence to bottom silicon layer 301 when forming the first separation layer 307 is prevented.
Then, Fig. 7 is refer to, in first opening the 305, second opening 306 and the 3rd opening 308（With reference to Fig. 6）Interior filling
Full silicon epitaxial layers 309, silicon epitaxial layers 309 and bottom silicon layer 301 constitute backgate.
The technique for forming the silicon epitaxial layers 309 is selective epitaxy technique, the temperature of the specific selective epitaxy technique
It is 600-1100 degrees Celsius, pressure 1-500 supports, silicon source gas is SiH4Or DCS（Dichlorosilane）, in addition to hydrogen, wherein
The flow of silicon source gas is 1-1000sccm, and the flow of hydrogen is 0.1-50slm.
Also doped with foreign ion in the silicon epitaxial layers 309, the electric property to improve silicon epitaxial layers 309 is described
Foreign ion is the foreign ion for having N-type or p-type, such as：Boron ion, arsenic ion, phosphonium ion, indium ion, antimony ion or bismuth from
Son etc..
Silicon epitaxial layers 309 are formed, silicon epitaxial layers 309 and bottom silicon layer 301 constitute backgate, are surround due to being subsequently formed fin
The silicon epitaxial layers 309, when applying certain voltage in backgate, in the fin of fin field effect pipe the formation of inversion layer with
The gate voltage applied on grid structure is related to the voltage applied in backgate, because the presence of backgate can preferably control fin
The threshold voltage of FET, and fin is around the silicon epitaxial layers 309, so that the threshold voltage of fin field effect pipe
Along the distribution uniform on the surface of fin.
The shape of cross section of the silicon epitaxial layers 309 is rectangle so that the outside side wall of silicon epitaxial layers 309 is apart from follow-up shape
Into fin portion surface distance it is equal, when applying voltage in silicon epitaxial layers 309 so that the voltage of application is to the different position of fin portion surface
The regulating power for putting corresponding threshold voltage is identical, can preferably make threshold voltage being evenly distributed along the surface of fin.
Then, Fig. 8 is refer to, in top surface the second separation layer 3 10 of formation of the silicon epitaxial layers.
Second separation layer 3 10 is used for backgate described in electric isolation and the grid structure being subsequently formed.
In the present embodiment, the material of second separation layer 3 10 is silica, the formation of second separation layer 3 10
Technique is thermal oxidation technology.
The thickness of second separation layer 310 is more than or equal to 30 angstroms so that backgate and the grid structure that is subsequently formed every
From better performances.
In other embodiments of the invention, the second oxide isolation layer silicon layer, silicon nitride layer, silicon oxynitride layer, carbon
The stacked structure of the single or multiple lift of SiClx layer or nitrogen silicon oxycarbide layer.
Formed after the second separation layer 3 10, then, refer to Fig. 9 and Figure 10, Fig. 10 is that the structure at Fig. 9 vertical views visual angle is shown
It is intended to, removes the hard mask layer 304（With reference to Fig. 8）, expose the side of second separation layer 3 10 and portion of epi silicon layer 309
Wall；Formed in the side wall of portion of epi silicon layer 309 and the surface of top silicon layer 303 of second separation layer 3 10 and exposure
Side wall 311.
The material of the side wall 311 is one or more layers the stacking in amorphous carbon, SiN, SiON, SiCN, SiC or BN
Structure.The width of the side wall 3 11 is more than or equal to 10 nanometers, subsequently with side wall 3 11 for top silicon layer described in mask etching
303, during the fin of formation, make the fin to be formed that there is certain width.It should be noted that the width of the side wall 311 is
The Breadth Maximum of side wall bottom.
The detailed process of the side wall 311 formation is：Using chemical vapor deposition method in top silicon layer surface shape
Into spacer material layer, the surface of spacer material layer covering second separation layer 3 10 and side wall and silicon epitaxial layers 309 expose
Side wall；Then, the spacer material layer is etched using without mask plasma etching technique, in second separation layer 310
With the sidewall surfaces formation side wall 3 11 of exposed portion of epi silicon layer 309.Using without mask plasma etching technique from right
Accurate formation side wall 3 11 so that the position of the side wall 311 of the both sides of silicon epitaxial layers 309 and the precision of width are higher, are subsequently formed
During fin so that the position of the fin around silicon epitaxial layers and the precision of width are higher, the performance of fin field effect pipe is improved.
Then, Figure 11 is refer to, is mask with the side wall 311, the top silicon layer 303 is etched（With reference to Fig. 9）, formed
Around the fin 312 of the silicon epitaxial layers 309.
The plasma in process etching technics of the top silicon layer 303 is etched, what the plasma etch process was used
Gas is HBr and Cl2。
Then, Figure 12 is refer to, in the formation grid of the sidewall surfaces away from the side of the first separation layer 307 of the fin 312
Dielectric layer 313.
The material of the gate dielectric layer 313 is silica or high K dielectric material, and the K dielectric materials are HfO2、TiO2、
HfZrO、Ta2O3、ZrO2Or ZrSiO2.The gate dielectric layer 313 can include sandwich construction, such as hafnium oxide and silica or
Person's hafnium oxide and silicon oxynitride.
The gate dielectric layer 313 is formed by thermal oxide or depositing operation.
It is the structural representation that Fig. 13 overlooks visual angle next referring to Fig. 13 and Figure 14, Figure 14, is developed across the fin
The gate electrode 314 in portion 312, the gate electrode 314 covers the gate dielectric layer 313, the second separation layer 3 10 and side wall 3 11
Surface.
The material of the gate electrode 314 is polysilicon or metal, and gate electrode 314 and gate dielectric layer 313 constitute fin
The grid structure of effect pipe.
Formed after gate electrode 314, in addition to：The part side wall 311 of the both sides of gate electrode 314 is removed, fin 3 12 is exposed
The surface at two ends；Then ion implanting is carried out to the exposed two ends of fin 3 12, forms the source/drain region of fin field effect pipe.
The fin field effect pipe of above method formation, refer to Fig. 13 and Figure 14, including：
Silicon-on-insulator substrate, the silicon-on-insulator substrate includes top silicon layer, bottom silicon layer 30 1 and positioned at top layer
Buried layer 302 between silicon layer and bottom silicon layer, top silicon layer as fin field effect pipe fin 3 12；Positioned at the top layer
Exposure second opening for burying layer surface in silicon layer；Positioned at the first separation layer 307 of the side wall of the described second opening；It is located at
3rd opening on the surface of exposure bottom silicon layer 301, the position of the 3rd opening and the position phase of the second opening in the buried layer 302
Correspondence；The silicon epitaxial layers 309 of filling full second opening and the 3rd opening, the top surface of silicon epitaxial layers 309 is higher than top layer
The surface of silicon layer, silicon epitaxial layers 309 and bottom silicon layer 301 constitute backgate；Positioned at the of the top surface of the silicon epitaxial layers 309
Two separation layers 3 10；Positioned at the side wall and the surface of top silicon layer of second separation layer 3 10 and portion of epi silicon layer 309
Side wall 3 11.
Also include：Positioned at the gate dielectric layer of the sidewall surfaces away from the side of the first separation layer 307 of the fin 3 12
313；Across the gate electrode 314 of the fin 312, the gate electrode 314 covers the gate dielectric layer 313, the second separation layer 3
10 and the surface of side wall 3 11.
When fin field effect pipe works, when applying certain voltage in backgate, the voltage applied in backgate can influence fin
The formation of inversion layer in portion, so that the threshold voltage of fin field effect pipe produces change, when fin field effect pipe works,
The gate voltage being applied on the grid structure of fin field effect pipe produces change accordingly, due to the presence of backgate so that fin
The threshold voltage of FET is related to both gate voltages on the voltage and grid structure that apply in backgate, therefore by applying
The size of voltage in backgate and positive and negative, can preferably control the threshold voltage of fin field effect pipe, and the ring of fin 312
Around the silicon epitaxial layers 309, so that the distribution uniform on surface of the threshold voltage of fin field effect pipe along fin 312.
Specifically, when the fin field effect pipe is the fin field effect pipe of N-type, when backgate applies positive voltage, meeting
Increase the threshold voltage of the fin field effect pipe of N-type, and positive voltage is bigger, the threshold voltage of the fin field effect pipe of N-type
It is bigger；When applying negative voltage in backgate, the threshold voltage of the fin field effect pipe of N-type, and negative voltage absolute value can be reduced
Bigger, the threshold voltage of the fin field effect pipe of N-type is also smaller.
When the fin field effect pipe is the fin field effect pipe of p-type, when backgate applies positive voltage, N-type can be reduced
Fin field effect pipe threshold voltage, and positive voltage is bigger, and the threshold voltage of the fin field effect pipe of N-type is also smaller；When
When backgate applies negative voltage, the threshold voltage of the fin field effect pipe of N-type can be increased, and negative voltage absolute value is bigger, N-type
Fin field effect pipe threshold voltage it is also bigger.
To sum up, the forming method of fin field effect of embodiment of the present invention pipe, etches the top silicon layer of silicon-on-insulator substrate
And buried layer, the second opening and the 3rd opening of exposure bottom silicon surface are formed, is then filled out in the second opening and the 3rd opening
Full of silicon epitaxial layers, silicon epitaxial layers and bottom silicon layer constitute backgate, then form the fin around the silicon epitaxial layers, technique mistake
Journey is simple, and has the first separation layer and buried layer between fin and backgate, improve electricity between backgate and fin every
From performance.
Further, the first separation layer and the second separation layer are formed by thermal oxidation technology, and processing step is simple, saved into
This.
There is exposure in the fin field effect pipe of the embodiment of the present invention, the top silicon layer and buried layer of silicon-on-insulator substrate
Full silicon epitaxial layers, silicon epitaxial layers are filled in the second opening and the 3rd opening of bottom silicon surface, the second opening and the 3rd opening
Backgate is constituted with bottom silicon layer, remaining Portions of top layer silicon layer is as fin, and fin is around the silicon epitaxial layers, fin and backgate
Between have the first separation layer and buried layer, due to the presence of backgate, by applying certain voltage in backgate, in backgate
When applying certain voltage, the voltage applied in backgate can influence the formation of inversion layer in fin so that fin field effect pipe
Threshold voltage produces change, when fin field effect pipe works, is applied to the gate voltage on the grid structure of fin field effect pipe
It is corresponding to produce change, due to the presence of backgate so that the voltage that applies on the threshold voltage and backgate of fin field effect pipe and
Both gate voltages on grid structure correlation, therefore be applied to the size of voltage in backgate and positive and negative by regulation, can be compared with
The threshold voltage of good control fin field effect pipe, and fin is around the silicon epitaxial layers（A part for backgate）, so that
Threshold voltage being evenly distributed along the surface of fin is obtained, there is the first separation layer and buried layer between fin and backgate in addition,
When applying voltage in backgate, influence will not be produced on the electric property and working condition of fin field effect pipe.
Although the present invention is disclosed as above with preferred embodiment, it is not for limiting the present invention, any this area
Technical staff without departing from the spirit and scope of the present invention, may be by the methods and techniques content of the disclosure above to this hair
Bright technical scheme makes possible variation and modification, therefore, every content without departing from technical solution of the present invention, according to the present invention
Any simple modifications, equivalents, and modifications made to above example of technical spirit, belong to technical solution of the present invention
Protection domain.
Claims (11)
1. a kind of forming method of fin field effect pipe, it is characterised in that including：
Silicon-on-insulator substrate is provided, the silicon-on-insulator substrate includes top silicon layer, bottom silicon layer and positioned at top silicon layer
Buried layer between bottom silicon layer；
Hard mask layer is formed on the top silicon layer surface, the hard mask layer has the first of exposed top layer silicon surface to open
Mouthful；
Along the first opening, the top silicon layer is etched, exposure second opening for burying layer surface is formed；
In side wall the first separation layer of formation of the described second opening；
The buried layer is etched along the second opening, the 3rd opening of exposure bottom silicon surface is formed；
The full silicon epitaxial layers of filling in the first opening, the second opening and the 3rd opening, silicon epitaxial layers and bottom silicon layer constitute backgate；
In top surface the second separation layer of formation of the silicon epitaxial layers；
Remove the side wall of the hard mask layer, exposure second separation layer and portion of epi silicon layer；
Side wall is formed on the surface of the side wall and top silicon layer of second separation layer and the portion of epi silicon layer of exposure；
Using the side wall as mask, the top silicon layer is etched, the fin around the silicon epitaxial layers is formed.
2. the forming method of fin field effect pipe as claimed in claim 1, it is characterised in that the thickness of the hard mask layer is big
In equal to 20 nanometers.
3. the forming method of fin field effect pipe as claimed in claim 2, it is characterised in that the hard mask layer is amorphous
One or more layers stacked structure in carbon, SiN, SiON, SiCN, SiC or BN.
4. the forming method of fin field effect pipe as claimed in claim 1, it is characterised in that the width of the side wall is more than etc.
In 10 nanometers.
5. the forming method of fin field effect pipe as claimed in claim 4, it is characterised in that the side wall be amorphous carbon,
One or more layers stacked structure in SiN, SiON, SiCN, SiC or BN.
6. the forming method of fin field effect pipe as claimed in claim 1, it is characterised in that the material of first separation layer
For silica, the formation process of the first separation layer is thermal oxidation technology.
7. the forming method of fin field effect pipe as claimed in claim 6, it is characterised in that the thickness of first separation layer
For more than or equal to 10 angstroms.
8. the forming method of fin field effect pipe as claimed in claim 1, it is characterised in that the material of second separation layer
For silica, the formation process of the second separation layer is thermal oxidation technology.
9. the forming method of fin field effect pipe as claimed in claim 8, it is characterised in that the thickness of second separation layer
For more than or equal to 30 angstroms.
10. the forming method of fin field effect pipe as claimed in claim 1, it is characterised in that also doped with N in the backgate
The foreign ion of type or p-type.
11. the forming method of fin field effect pipe as claimed in claim 1, it is characterised in that also include：In the fin
Sidewall surfaces formation gate dielectric layer away from the first separation layer side；It is developed across the gate electrode of the fin, the gate electrode
Cover the surface of the gate dielectric layer, the second separation layer and side wall.
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