CN103778009A - Interrupt processing method and device - Google Patents
Interrupt processing method and device Download PDFInfo
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Abstract
The invention discloses an interrupt processing method and device. The method comprises the steps of step 1, initializing interrupt and the drive program of the interrupt when a system is initialized, and when the interrupt occurs during execution of a current task, storing the context information of the interrupt field into a preset task stack and determining whether the interrupt is a interrupt nesting; step 2, storing the context information of a current task field into the preset task stack and moving a stack pointer (SP) to an interrupt stack; step 3, informing the system to start entering interrupt processing, reading interrupt priority levels, opening the interrupt, enabling the interrupt nesting, and after executing an interrupt processing program, prohibiting the interrupt, informing the system to exit the interrupt processing and determining whether the system is in the interrupt nesting; step 4, recovering the context information of the stored current interrupt field and returning to upper-layer interrupt; step 5, recovering the context information of the stored current task field and returning to the current task.
Description
Technical field
The present invention relates to field of mobile communication, particularly relate to a kind of interruption processing method and device.
Background technology
In the prior art, embedded system, to there being higher requirement in real-time and response speed, is supported the interruptable controller of different priorities, software has also been proposed to support to the requirement of interrupt nesting.Along with the complicacy of embedded system is more and more higher, the introducing of real time operating system is also more and more general, how in real time operating system, to support interrupt nesting to become a difficult problem.
μ COS-II is a real-time multi-task kernel based on preemptive type, curable, can cut out, have high stability and reliability.It always moves the ready task of limit priority.The interrupt nesting number of plies that μ COS-II is supported can be up to 255 layers.
Aspect embedded, without interlocking pipelining-stage microprocessor (Microcomputer without interlockedpipeline stages, referred to as MIPS) 32 series microprocessors are to be only second at present one of ARM processor with the most use, its application covers the various aspects such as game machine, router, laser printer, palm PC.Wherein, the interrupt mode of MIPS32 processor support has following three kinds:
Regular interrupt: support eight independently interrupt bits, do not distinguish priority between interruption, all interruptions have same interruption entrance.
Vector interrupts: support eight independently interrupt bits, do not distinguish priority between interruption, each interruption has the interruption entrance of oneself.
External vector (EIC) is interrupted: support maximum 64 interruptions, between interruption, priority can be set, each interruption has the interruption entrance of oneself.
The interrupt number that regular interrupt and vector interruption are supported is limited, and does not distinguish priority, has limited use in practice, and therefore, following interruption is EIC and interrupts.
In existing implementation, there is μ COS-II to be transplanted to the correlation technique of MIPS, in existing these technology, all not support nested interrupt for interrupting processing, way used is all in the process of handling interrupt, closes global interrupt enable bit, disabled interrupt, after finishing dealing with, opening interruption.Have like this problem, when the interruption of high priority comes temporarily, due to interrupt inhibit, and CPU can not process in time, thereby has affected the real-time of interrupting.
In addition, in μ COS-II, have the interrupt processing mechanism of oneself, but its interruption processing is all carried out on task stack.And EIC supports 64 grades of interruptions, and permission interrupt nesting, if according to the interruption treatment scheme of μ COS-II itself, each task stack must be reserved the space that allows 64 grades of interrupt nestings, this has increased the ram space that task stack takies greatly, has affected the service efficiency of RAM.
Summary of the invention
The invention provides a kind of interruption processing method and device, in prior art, μ COS-II is transplanted to the problem that can not support nested interrupt after MIPS to solve.
The invention provides a kind of interruption processing method, be applicable to based on MIPS32, as processor and the platform using μ COS-II as operating system, to comprise: step 1, in the time that system is carried out initialization, interruption and driver thereof are carried out to initialization, the in the situation that of occurring to interrupt in the time carrying out current task, the contextual information of interrupt spot is saved in the interrupt stack setting in advance, and determines whether interrupt nesting, if the judgment is No, execution step 2, otherwise, execution step 3; Step 2, is saved in the contextual information at current task scene in the task stack setting in advance, and stack pointer SP is moved on to interrupt stack, execution step 3; Step 3, reporting system starts to enter interruption to be processed, and reads interrupt priority level, open interruption, enable interrupt nesting, and in commission break after handling procedure, disabled interrupt, reporting system exits and interrupts processing, and judge whether in interrupt nesting, if the judgment is Yes, execution step 4, otherwise, execution step 5; Step 4 is recovered the contextual information of the current interrupt spot of preserving from interrupt stack, and returns to upper strata interruption and continue to carry out; Step 5 is recovered the contextual information at the current task scene of preserving from task stack, and returns to the current task being interrupted and continue to carry out.
Preferably, in the time that system is carried out initialization, to interrupting and driver carries out initialization and specifically comprises: configure priority and the trigger mode of all interruptions, and forbid all interruptions, wherein, trigger mode comprises: level triggers or edge-triggered; Obtain the interrupt number of all interruptions, corresponding interrupt handling routine is corresponding with interrupt number; Before enabling to interrupt, interrupt handling routine is copied on its corresponding interrupt vector entry address, wherein, between interrupt vector, be spaced apart 32 bytes.
Preferably, the contextual information of interrupt spot is saved in the interrupt stack setting in advance and is specifically comprised: the information in the microprocessor MIPS general-purpose register without inner interlocked pipelining-stage of interrupt spot, status register SR and exception procedure register EPC is saved in the interrupt stack setting in advance.
Preferably, the contextual information at current task scene is saved in the task stack setting in advance and is specifically comprised: successively the information in programmable counter PC, the SP at current task scene, related register and interrupt return address are saved in the task stack setting in advance, wherein related register comprises SR general-purpose register relevant with other; On-the-spot the current task of pointing to last pop down content pointer is saved in predefined function, wherein, the use of popping in the time recovering current task of the on-the-spot pointer of current task.
Preferably, reporting system starts to enter interruption to be processed, read interrupt priority level, open interruption, enable interrupt nesting, and in commission break after handling procedure, disabled interrupt, reporting system exits to interrupt processing and specifically comprises: jump to operating system and interrupt entering OS_IntEnter function, reporting system starts to enter interruption to be processed; The request interrupt priority level RIPL position of reading reason CAUSE register, obtains the priority of interruption, and the priority of interruption is set on the interrupt priority level IPL position of SR; By the KSU position in SR, ERL position and the zero clearing of EXL position; SP is successively decreased, and assigned interrupt storehouse is to the parameter of interrupt handling routine; Obtain the priority of interruption from the IPL position of SR, jump to interrupt handling routine according to this priority and process; Revise the IPL position of SR, and the ERL position of SR and EXL position be set to zero, open interruption simultaneously, enable interrupt nesting; Discharge interrupt stack, and be 1 by the EXL position of SR, disabled interrupt; Jump to system break and exit OS_IntExit function, reporting system exits and interrupts processing.
The present invention also provides a kind of interrupt processing device, be applicable to based on MIPS32 as processor and the platform using μ COS-II as operating system, comprise: initialization module, in the time that system is carried out initialization, carries out initialization to interruption and driver thereof; The first interruption processing module, the in the situation that of for generation interruption in the time carrying out current task, the contextual information of interrupt spot is saved in the interrupt stack setting in advance, and determine whether interrupt nesting, if the judgment is No, call the second interruption processing module, otherwise, the 3rd interruption processing module called; The second interruption processing module, for the contextual information at current task scene being saved in to the task stack setting in advance, and moves on to interrupt stack by stack pointer SP, calls the 3rd interruption processing module; The 3rd interruption processing module, starts to enter for reporting system and interrupts processing, and reads interrupt priority level, open interruption, enable interrupt nesting, and in commission break after handling procedure, disabled interrupt, reporting system exits and interrupts processing, and judge whether in interrupt nesting, if the judgment is Yes, call and interrupt recovering module, otherwise calling task recovers module; Interrupt recovering module, for recover the contextual information of the current interrupt spot of preserving from interrupt stack, and return to upper strata interruption and continue to carry out; Task recovery module, for recover the contextual information at the current task scene of preserving from task stack, and returns to the current task being interrupted and continues to carry out.
Preferably, initialization module specifically for: configure priority and the trigger mode of all interruptions, and forbid all interruptions, wherein, trigger mode comprises: level triggers or edge-triggered; Obtain the interrupt number of all interruptions, corresponding interrupt handling routine is corresponding with interrupt number; Before enabling to interrupt, interrupt handling routine is copied on its corresponding interrupt vector entry address, wherein, between interrupt vector, be spaced apart 32 bytes.
Preferably, the first interruption processing module specifically for: the information in the microprocessor MIPS general-purpose register without inner interlocked pipelining-stage of interrupt spot, status register SR and exception procedure register EPC is saved in the interrupt stack setting in advance.
Preferably, the second interruption processing module specifically for: successively the information in programmable counter PC, the SP at current task scene, related register and interrupt return address are saved in the task stack setting in advance, wherein related register comprises SR general-purpose register relevant with other; On-the-spot the current task of pointing to last pop down content pointer is saved in predefined function, wherein, the use of popping in the time recovering current task of the on-the-spot pointer of current task.
Preferably, the 3rd interruption processing module specifically for: jump to operating system and interrupt entering OS_IntEnter function, reporting system starts to enter and interrupts processing; The request interrupt priority level RIPL position of reading reason CAUSE register, obtains the priority of interruption, and the priority of interruption is set on the interrupt priority level IPL position of SR; By the KSU position in SR, ERL position and the zero clearing of EXL position; SP is successively decreased, and assigned interrupt storehouse is to the parameter of interrupt handling routine; Obtain the priority of interruption from the IPL position of SR, jump to interrupt handling routine according to this priority and process; Revise the IPL position of SR, and the ERL position of SR and EXL position be set to zero, open interruption simultaneously, enable interrupt nesting; Discharge interrupt stack, and be 1 by the EXL position of SR, disabled interrupt; Jump to system break and exit OS_IntExit function, reporting system exits and interrupts processing.
Beneficial effect of the present invention is as follows:
By hew out specially a region in internal memory, use as interrupt stack, there is pop down when interrupt nesting and go out stack operation all only to use interrupt stack, thereby task stack is separated with interrupt stack, make in the time of calculation task storehouse size, do not need the EMS memory occupation that interrupts processing in (comprising interrupt nesting) to calculate in task stack, shared ram space size when only needing consideration task itself and interrupting first, improve the service efficiency of RAM, and then reserved more ram space to upper strata.In addition, the register pop down in all interrupt nestings is all pressed in interrupt stack, greatly reduces for the requirement of task stack memory size like this.
Above-mentioned explanation is only the general introduction of technical solution of the present invention, in order to better understand technological means of the present invention, and can be implemented according to the content of instructions, and for above and other objects of the present invention, feature and advantage can be become apparent, below especially exemplified by the specific embodiment of the present invention.
Accompanying drawing explanation
By reading below detailed description of the preferred embodiment, various other advantage and benefits will become cheer and bright for those of ordinary skills.Accompanying drawing is only for the object of preferred implementation is shown, and do not think limitation of the present invention.And in whole accompanying drawing, represent identical parts by identical reference symbol.In the accompanying drawings:
Fig. 1 is the process flow diagram of the interruption processing method of the embodiment of the present invention;
Fig. 2 is the initialized schematic diagram of the task stack of the embodiment of the present invention;
Fig. 3 is storehouse situation of change schematic diagram while interrupting first in task implementation after interrupt stack and the task stack of the embodiment of the present invention separates;
The schematic diagram of interrupt stack situation of change when Fig. 4 is the interrupt nesting of the embodiment of the present invention;
Fig. 5 is that interrupt stack and the task stack of the embodiment of the present invention separates and while design, interrupt processing flow chart;
Fig. 6 is the structural representation of the interrupt processing device of the embodiment of the present invention.
Embodiment
Exemplary embodiment of the present disclosure is described below with reference to accompanying drawings in more detail.Although shown exemplary embodiment of the present disclosure in accompanying drawing, but should be appreciated that and can realize the disclosure and the embodiment that should do not set forth limits here with various forms.On the contrary, it is in order more thoroughly to understand the disclosure that these embodiment are provided, and can be by the those skilled in the art that conveys to complete the scope of the present disclosure.
In prior art, μ COS-II to be transplanted to the problem that can not support nested interrupt after MIPS in order solving, to be the invention provides a kind of interruption processing method and device, below in conjunction with accompanying drawing and embodiment, the present invention is further elaborated.Should be appreciated that specific embodiment described herein, only in order to explain the present invention, does not limit the present invention.
Embodiment of the method
According to embodiments of the invention, a kind of interruption processing method is provided, be applicable to based on MIPS32 as processor and the platform using μ COS-II as operating system, Fig. 1 is the process flow diagram of the interruption processing method of the embodiment of the present invention, as shown in Figure 1, comprise following processing according to the interruption processing method of the embodiment of the present invention:
Step 101, in the time that system is carried out initialization, interruption and driver thereof are carried out to initialization, the in the situation that of occurring to interrupt in the time carrying out current task, the contextual information of interrupt spot is saved in the interrupt stack setting in advance, and determines whether interrupt nesting, if the judgment is No, execution step 102, otherwise, execution step 103;
Particularly, in step 101, in the time that system is carried out initialization, to interrupting and driver carries out initialization and specifically comprises: the priority and the trigger mode that configure all interruptions, and forbid all interruptions, wherein, trigger mode comprises: level triggers or edge-triggered; Obtain the interrupt number of all interruptions, corresponding interrupt handling routine is corresponding with interrupt number; Before enabling to interrupt, interrupt handling routine is copied on its corresponding interrupt vector entry address, wherein, between interrupt vector, be spaced apart 32 bytes.
The contextual information of interrupt spot is saved in the interrupt stack setting in advance and is specifically comprised: the information in the microprocessor MIPS general-purpose register without inner interlocked pipelining-stage of interrupt spot, status register SR and exception procedure register EPC is saved in the interrupt stack setting in advance.
Step 102, is saved in the contextual information at current task scene in the task stack setting in advance, and stack pointer SP is moved on to interrupt stack, execution step 103;
In step 102, the contextual information at current task scene is saved in the task stack setting in advance and is specifically comprised: successively the information in programmable counter PC, the SP at current task scene, related register and interrupt return address are saved in the task stack setting in advance, wherein related register comprises SR general-purpose register relevant with other; On-the-spot the current task of pointing to last pop down content pointer is saved in predefined function, wherein, the use of popping in the time recovering current task of the on-the-spot pointer of current task.
Step 103, reporting system starts to enter interruption to be processed, and reads interrupt priority level, open interruption, enable interrupt nesting, and in commission break after handling procedure, disabled interrupt, reporting system exits and interrupts processing, and judge whether in interrupt nesting, if the judgment is Yes, execution step 104, otherwise, execution step 105;
Step 103 specifically comprises following processing: 1, jump to operating system and interrupt entering OS_IntEnter function, reporting system starts to enter interruption to be processed; The request interrupt priority level RIPL position of 2, reading reason CAUSE register, obtains the priority of interruption, and the priority of interruption is set on the interrupt priority level IPL position of SR; 3, by the KSU position in SR, ERL position and the zero clearing of EXL position; 4, SP is successively decreased, assigned interrupt storehouse is to the parameter of interrupt handling routine; 5, obtain the priority of interruption from the IPL position of SR, jump to interrupt handling routine according to this priority and process; 6, the IPL position of modification SR, and the ERL position of SR and EXL position are set to zero, open interruption simultaneously, enable interrupt nesting; 7, discharge interrupt stack, and be 1 by the EXL position of SR, disabled interrupt; 8, jump to system break and exit OS_IntExit function, reporting system exits and interrupts processing.
Step 104 is recovered the contextual information of the current interrupt spot of preserving from interrupt stack, and returns to upper strata interruption and continue to carry out;
Step 105 is recovered the contextual information at the current task scene of preserving from task stack, and returns to the current task being interrupted and continue to carry out.
Below in conjunction with accompanying drawing, the technique scheme of the embodiment of the present invention is described in detail.
Fig. 2 is the initialized schematic diagram of the task stack of the embodiment of the present invention, as shown in Figure 2,, is mainly handled as follows during in initialization at task stack: 1, be ready to the state (right value) that when task run starts in the future, CPU register should be located; 2, the programmable counter (PC) of having good positioning, if design data is reasonable, when task is performed, just CPU can be according to the pre-designed row of rowing.
In the time that task is moved first, PC pointer (being mission function pointer) is by navigating to the first row of task code, and because task code was not yet performed, therefore it doesn't matter for other register of the variable in code and CPU, simple method is to be 0 by its tax; Through stacked and pop, now stack pointer (StackPointer, referred to as SP) points to the lowermost end (being exactly last element of the task stack array that defined) of task stack.
By hew out specially a region in internal memory, use as interrupt stack, there is pop down when interrupt nesting and go out stack operation all only to use it.Thereby task stack is separated with interrupt stack, make in the time of calculation task storehouse size, do not need the EMS memory occupation that interrupts processing in (comprising interrupt nesting) to calculate in task stack, shared ram space size when only needing consideration task itself and interrupting first, improve the service efficiency of RAM, and then reserved more ram space to upper strata.
Fig. 3 is storehouse situation of change schematic diagram while interrupting first in task implementation after interrupt stack and the task stack of the embodiment of the present invention separates, as shown in Figure 3, after interrupt stack separates with task stack, in the time occurring to interrupt in tasks carrying process, first, in task stack, PC and SP are by system pop down, then by the related register pop down of CPU, simultaneously by the status register of CPU (Staus Register, referred to as SR) and interrupt return address pop down, on-the-spot last pop down content of pointed of task after task stack pop down, and by this value assignment to OSTCBCur, the use to pop, then SP is adjusted to interrupt stack place.Interrupting in processing procedure, may there is the operation (interrupting the function call of processing) of pop down, the pointer of SP can move thereupon so in this case.
The schematic diagram of interrupt stack situation of change when Fig. 4 is the interrupt nesting of the embodiment of the present invention, as shown in Figure 4, when interrupting occurring when nested, SP has been moved in interrupt stack, only has when interrupting exiting (interrupt nesting outermost layer) just SP to be moved on to task stack.So in the time of interrupt nesting, the same for the processing of interrupting with producing interruption for the first time, difference is: being kept in storehouse is not the register in task run, but register in interrupting processing, and is not to be kept at task stack but in interrupt stack.The EIC pattern of MIPS is supported 64 interrupt sources, can not use for 0 grade, therefore has at most the interrupt nesting of 62 layers.Consider the darkest when nested required storehouse size be: 62*(32*4)=8K, if preserved with task stack, need number of tasks N*8K, the effect of memory optimization it can be seen: the register pop down in all interrupt nestings is all pressed in interrupt stack, greatly reduces like this for the requirement of task stack memory size.
From describing and can find out above, the embodiment of the present invention is improved for the deficiency of transplanting μ COS-II under original MIPS32, and a kind of new interruption processing method is provided, and has improved the response speed of interrupting and the use that has reduced RAM.
Fig. 5 is that interrupt stack and the task stack of the embodiment of the present invention separates while design and interrupt processing flow chart, as shown in Figure 5, specifically comprises following processing:
Step 1, defines an interrupt stack array, during for follow-up underway disconnected processing, preserves the context of nested interrupt.
Step 2, in the time of operating system initialization, before driver initialization, first carries out initialization to interrupting, and configures the priority of all interruptions, and trigger mode (level triggers or edge-triggered), and forbids all interruptions.
Step 3, in the initialization of driver, obtains relevant interrupt number, then that relevant interrupt handling routine is corresponding with interrupt number.Under EIC pattern, the entry address difference that each interruption is corresponding, therefore, the vectorial entry address that must interrupt handling routine be copied to its correspondence before enabling interruption is gone.Interrupt vector is set and is spaced apart 32 bytes, processing code is jump instruction, allows all interruptions all jump in same common treatment flow process.
Step 4, when an interrupt occurs, first saving scene: preserve MIPS general-purpose register and SR, EPC register and wait until on storehouse.Can use these two reservations of K0 and K1 to the special register interrupting, according to ABI standard, t0 ~ t9 register does not need to preserve before use, can preserve them.
Whether step 5, reads the numerical value of OSIntNesting, judge currently in interrupt nesting state, if enter first interruption, preserves task scene in task stack.
Step 6, upgrades stack pointer, makes it be directed to the interrupt stack that step 1 defines.Follow-up like this in there is interruption, just the context interrupting is above kept on this interrupt stack.
Step 7, jumps to OS_IntEnter function, and notice operating system starts to interrupt processing.
Step 8, request interrupt priority level (Requested Interrupt Priority, referred to as the RIPL) numerical value that reads Cause register, obtains the priority of this interruption, this value is set on the IPL position of SR, so only just can be identified by CPU higher than the interruption of this priority.
Step 9, by the KSU position in SR, ERL position and the zero clearing of EXL position.
Step 10, successively decreases stack pointer, distributes the parameter of storehouse to interrupt handling routine.
Step 11, obtains current interrupt priority level, jumps to interrupt handling routine and processes.
Step 12, revises the IPL position in SR, enters kernel pattern: ERL position, EXL position are 0, open interruption simultaneously, allows interrupt nesting.
Step 13, discharges storehouse.
Step 14, revises the EXL position in SR, makes it put 1, disabled interrupt.
Step 15, calls OS_IntExit function, and notice operating system exits interrupts processing, if nested interrupt outermost layer triggers task scheduling one time.
Step 16, judges that by reading OSIntNesting whether interruption is also nested, if there is no interrupt nesting, carries out step 17 and processes, if interrupt nesting carries out step 18 and processes.
Step 20 is recovered the general-purpose register of CPU from interrupt stack.
Step 21, by eret instruction, returns from interruption.
In sum, by means of the technical scheme of the embodiment of the present invention, by hew out specially a region in internal memory, use as interrupt stack, there is pop down when interrupt nesting and go out stack operation all only to use interrupt stack, thereby task stack is separated with interrupt stack, make in the time of calculation task storehouse size, do not need the EMS memory occupation that interrupts processing in (comprising interrupt nesting) to calculate in task stack, shared ram space size when only needing consideration task itself and interrupting first, improve the service efficiency of RAM, and then reserve more ram space to upper strata.In addition, the register pop down in all interrupt nestings is all pressed in interrupt stack, greatly reduces for the requirement of task stack memory size like this.
Device embodiment
According to embodiments of the invention, a kind of interrupt processing device is provided, be applicable to based on MIPS32 as processor and the platform using μ COS-II as operating system, Fig. 6 is the structural representation of the interrupt processing device of the embodiment of the present invention, as shown in Figure 6, comprise according to the interrupt processing device of the embodiment of the present invention: initialization module 60, the first interruption processing module 61, the second interruption processing module 62, the 3rd interruption processing module 63, interruption recover module 64 and task recovery module modules to the embodiment of the present invention below 65 is described in detail.
The first interruption processing module 61, the in the situation that of for generation interruption in the time carrying out current task, the contextual information of interrupt spot is saved in the interrupt stack setting in advance, and determine whether interrupt nesting, if the judgment is No, call the second interruption processing module 62, otherwise, the 3rd interruption processing module 63 called;
The first interruption processing module 61 specifically for: the information in the microprocessor MIPS general-purpose register without inner interlocked pipelining-stage of interrupt spot, status register SR and exception procedure register EPC is saved in the interrupt stack setting in advance.
The second interruption processing module 62, for the contextual information at current task scene being saved in to the task stack setting in advance, and moves on to interrupt stack by stack pointer SP, calls the 3rd interruption processing module 63;
The second interruption processing module 62 specifically for: successively the information in programmable counter PC, the SP at current task scene, related register and interrupt return address are saved in the task stack setting in advance, wherein related register comprises SR general-purpose register relevant with other; On-the-spot the current task of pointing to last pop down content pointer is saved in predefined function, wherein, the use of popping in the time recovering current task of the on-the-spot pointer of current task.
The 3rd interruption processing module 63, starts to enter for reporting system and interrupts processing, and reads interrupt priority level, open interruption, enable interrupt nesting, and in commission break after handling procedure, disabled interrupt, reporting system exits and interrupts processing, and judge whether in interrupt nesting, if the judgment is Yes, call and interrupt recovering module 64, otherwise calling task recovers module 65;
The 3rd interruption processing module 63 specifically for: jump to operating system and interrupt entering OS_IntEnter function, reporting system starts to enter and interrupts processing; The request interrupt priority level RIPL position of reading reason CAUSE register, obtains the priority of interruption, and the priority of interruption is set on the interrupt priority level IPL position of SR; By the KSU position in SR, ERL position and the zero clearing of EXL position; SP is successively decreased, and assigned interrupt storehouse is to the parameter of interrupt handling routine; Obtain the priority of interruption from the IPL position of SR, jump to interrupt handling routine according to this priority and process; Revise the IPL position of SR, and the ERL position of SR and EXL position be set to zero, open interruption simultaneously, enable interrupt nesting; Discharge interrupt stack, and be 1 by the EXL position of SR, disabled interrupt; Jump to system break and exit OS_IntExit function, reporting system exits and interrupts processing.
Interrupt recovering module 64, for recover the contextual information of the current interrupt spot of preserving from interrupt stack, and return to upper strata interruption and continue to carry out;
Below in conjunction with accompanying drawing, the technique scheme of the embodiment of the present invention is described in detail.
Fig. 2 is the initialized schematic diagram of the task stack of the embodiment of the present invention, as shown in Figure 2,, is mainly handled as follows during in initialization at task stack: 1, be ready to the state (right value) that when task run starts in the future, CPU register should be located; 2, the programmable counter (PC) of having good positioning, if design data is reasonable, when task is performed, just CPU can be according to the pre-designed row of rowing.
In the time that task is moved first, PC pointer (being mission function pointer) is by navigating to the first row of task code, and because task code was not yet performed, therefore it doesn't matter for other register of the variable in code and CPU, simple method is to be 0 by its tax; Through stacked and pop, now stack pointer (StackPointer, referred to as SP) points to the lowermost end (being exactly last element of the task stack array that defined) of task stack.
By hew out specially a region in internal memory, use as interrupt stack, there is pop down when interrupt nesting and go out stack operation all only to use it.Thereby task stack is separated with interrupt stack, make in the time of calculation task storehouse size, do not need the EMS memory occupation that interrupts processing in (comprising interrupt nesting) to calculate in task stack, shared ram space size when only needing consideration task itself and interrupting first, improve the service efficiency of RAM, and then reserved more ram space to upper strata.
Fig. 3 is storehouse situation of change schematic diagram while interrupting first in task implementation after interrupt stack and the task stack of the embodiment of the present invention separates, as shown in Figure 3, after interrupt stack separates with task stack, in the time occurring to interrupt in tasks carrying process, first, in task stack, PC and SP are by system pop down, then by the related register pop down of CPU, simultaneously by the status register of CPU (Staus Register, referred to as SR) and interrupt return address pop down, on-the-spot last pop down content of pointed of task after task stack pop down, and by this value assignment to OSTCBCur, the use to pop, then SP is adjusted to interrupt stack place.Interrupting in processing procedure, may there is the operation (interrupting the function call of processing) of pop down, the pointer of SP can move thereupon so in this case.
The schematic diagram of interrupt stack situation of change when Fig. 4 is the interrupt nesting of the embodiment of the present invention, as shown in Figure 4, when interrupting occurring when nested, SP has been moved in interrupt stack, only has when interrupting exiting (interrupt nesting outermost layer) just SP to be moved on to task stack.So in the time of interrupt nesting, the same for the processing of interrupting with producing interruption for the first time, difference is: being kept in storehouse is not the register in task run, but register in interrupting processing, and is not to be kept at task stack but in interrupt stack.The EIC pattern of MIPS is supported 64 interrupt sources, can not use for 0 grade, therefore has at most the interrupt nesting of 62 layers.Consider the darkest when nested required storehouse size be: 62*(32*4)=8K, if preserved with task stack, need number of tasks N*8K, the effect of memory optimization it can be seen: the register pop down in all interrupt nestings is all pressed in interrupt stack, greatly reduces like this for the requirement of task stack memory size.
From describing and can find out above, the embodiment of the present invention is improved for the deficiency of transplanting μ COS-II under original MIPS32, and a kind of new interruption processing method is provided, and has improved the response speed of interrupting and the use that has reduced RAM.
Fig. 5 is that interrupt stack and the task stack of the embodiment of the present invention separates while design and interrupt processing flow chart, as shown in Figure 5, specifically comprises following processing:
Step 1, defines an interrupt stack array, during for follow-up underway disconnected processing, preserves the context of nested interrupt.
Step 2, in the time of operating system initialization, before driver initialization, first carries out initialization to interrupting, and configures the priority of all interruptions, and trigger mode (level triggers or edge-triggered), and forbids all interruptions.
Step 3, in the initialization of driver, obtains relevant interrupt number, then that relevant interrupt handling routine is corresponding with interrupt number.Under EIC pattern, the entry address difference that each interruption is corresponding, therefore, the vectorial entry address that must interrupt handling routine be copied to its correspondence before enabling interruption is gone.Interrupt vector is set and is spaced apart 32 bytes, processing code is jump instruction, allows all interruptions all jump in same common treatment flow process.
Step 4, when an interrupt occurs, first saving scene: preserve MIPS general-purpose register and SR, EPC register and wait until on storehouse.Can use these two reservations of K0 and K1 to the special register interrupting, according to ABI standard, t0 ~ t9 register does not need to preserve before use, can preserve them.
Whether step 5, reads the numerical value of OSIntNesting, judge currently in interrupt nesting state, if enter first interruption, preserves task scene in task stack.
Step 6, upgrades stack pointer, makes it be directed to the interrupt stack that step 1 defines.Follow-up like this in there is interruption, just the context interrupting is above kept on this interrupt stack.
Step 7, jumps to OS_IntEnter function, and notice operating system starts to interrupt processing.
Step 8, request interrupt priority level (Requested Interrupt Priority, referred to as the RIPL) numerical value that reads Cause register, obtains the priority of this interruption, this value is set on the IPL position of SR, so only just can be identified by CPU higher than the interruption of this priority.
Step 9, by the KSU position in SR, ERL position and the zero clearing of EXL position.
Step 10, successively decreases stack pointer, distributes the parameter of storehouse to interrupt handling routine.
Step 11, obtains current interrupt priority level, jumps to interrupt handling routine and processes.
Step 12, revises the IPL position in SR, enters kernel pattern: ERL position, EXL position are 0, open interruption simultaneously, allows interrupt nesting.
Step 13, discharges storehouse.
Step 14, revises the EXL position in SR, makes it put 1, disabled interrupt.
Step 15, calls OS_IntExit function, and notice operating system exits interrupts processing, if nested interrupt outermost layer triggers task scheduling one time.
Step 16, judges that by reading OSIntNesting whether interruption is also nested, if there is no interrupt nesting, carries out step 17 and processes, if interrupt nesting carries out step 18 and processes.
Step 20 is recovered the general-purpose register of CPU from interrupt stack.
Step 21, by eret instruction, returns from interruption.
In sum, by means of the technical scheme of the embodiment of the present invention, by hew out specially a region in internal memory, use as interrupt stack, there is pop down when interrupt nesting and go out stack operation all only to use interrupt stack, thereby task stack is separated with interrupt stack, make in the time of calculation task storehouse size, do not need the EMS memory occupation that interrupts processing in (comprising interrupt nesting) to calculate in task stack, shared ram space size when only needing consideration task itself and interrupting first, improve the service efficiency of RAM, and then reserve more ram space to upper strata.In addition, the register pop down in all interrupt nestings is all pressed in interrupt stack, greatly reduces for the requirement of task stack memory size like this.
The algorithm providing at this is intrinsic not relevant to any certain computer, virtual system or miscellaneous equipment with demonstration.Various general-purpose systems also can with based on using together with this teaching.According to description above, it is apparent constructing the desired structure of this type systematic.In addition, the present invention is not also for any certain programmed language.It should be understood that and can utilize various programming languages to realize content of the present invention described here, and the description of above language-specific being done is in order to disclose preferred forms of the present invention.
In the instructions that provided herein, a large amount of details are described.But, can understand, embodiments of the invention can be put into practice in the situation that there is no these details.In some instances, be not shown specifically known method, structure and technology, so that not fuzzy understanding of this description.
Similarly, be to be understood that, in order to simplify the disclosure and to help to understand one or more in each inventive aspect, in the above in the description of exemplary embodiment of the present invention, each feature of the present invention is grouped together into single embodiment, figure or sometimes in its description.But, the method for the disclosure should be construed to the following intention of reflection: the present invention for required protection requires than the more feature of feature of clearly recording in each claim.Or rather, as reflected in claims below, inventive aspect is to be less than all features of disclosed single embodiment above.Therefore, claims of following embodiment are incorporated to this embodiment thus clearly, and wherein each claim itself is as independent embodiment of the present invention.
Those skilled in the art are appreciated that and can the module in the equipment in embodiment are adaptively changed and they are arranged in one or more equipment different from this embodiment.Module in embodiment or unit or assembly can be combined into a module or unit or assembly, and can put them in addition multiple submodules or subelement or sub-component.At least some in such feature and/or process or unit are mutually repelling, and can adopt any combination to combine all processes or the unit of disclosed all features in this instructions (comprising claim, summary and the accompanying drawing followed) and disclosed any method like this or equipment.Unless clearly statement in addition, in this instructions (comprising claim, summary and the accompanying drawing followed) disclosed each feature can be by providing identical, be equal to or the alternative features of similar object replaces.
In addition, those skilled in the art can understand, although embodiment more described herein comprise some feature rather than further feature included in other embodiment, the combination of the feature of different embodiment means within scope of the present invention and forms different embodiment.For example, in the following claims, the one of any of embodiment required for protection can be used with array mode arbitrarily.
It should be noted above-described embodiment the present invention will be described rather than limit the invention, and those skilled in the art can design alternative embodiment in the case of not departing from the scope of claims.In the claims, any reference symbol between bracket should be configured to limitations on claims.Word " comprises " not to be got rid of existence and is not listed as element or step in the claims.Being positioned at word " " before element or " one " does not get rid of and has multiple such elements.The present invention can be by means of including the hardware of some different elements and realizing by means of the computing machine of suitably programming.In the unit claim of having enumerated some devices, several in these devices can be to carry out imbody by same hardware branch.The use of word first, second and C grade does not represent any order.Can be title by these word explanations.
Claims (10)
1. an interruption processing method, is characterized in that, is applicable to based on MIPS32 as processor and the platform using μ COS-II as operating system, and described method comprises:
Step 1, in the time that system is carried out initialization, interruption and driver thereof are carried out to initialization, the in the situation that of occurring to interrupt in the time carrying out current task, the contextual information of interrupt spot is saved in the interrupt stack setting in advance, and determines whether interrupt nesting, if the judgment is No, execution step 2, otherwise, execution step 3;
Step 2, is saved in the contextual information at current task scene in the task stack setting in advance, and stack pointer SP is moved on to described interrupt stack, execution step 3;
Step 3, reporting system starts to enter interruption to be processed, and reads interrupt priority level, open interruption, enable interrupt nesting, and in commission break after handling procedure, disabled interrupt, reporting system exits and interrupts processing, and judge whether in interrupt nesting, if the judgment is Yes, execution step 4, otherwise, execution step 5;
Step 4 is recovered the contextual information of the described current interrupt spot of preserving from described interrupt stack, and returns to upper strata interruption and continue to carry out;
Step 5 is recovered the contextual information at the described current task scene of preserving from described task stack, and returns to the described current task being interrupted and continue to carry out.
2. the method for claim 1, is characterized in that, in the time that system is carried out initialization, to interrupting and driver carries out initialization and specifically comprises:
Configure priority and the trigger mode of all interruptions, and forbid all interruptions, wherein, described trigger mode comprises: level triggers or edge-triggered;
Obtain the interrupt number of all interruptions, corresponding interrupt handling routine is corresponding with described interrupt number;
Before enabling to interrupt, interrupt handling routine is copied on its corresponding interrupt vector entry address, wherein, between described interrupt vector, be spaced apart 32 bytes.
3. the method for claim 1, it is characterized in that, the contextual information of interrupt spot is saved in the interrupt stack setting in advance and is specifically comprised: the information in the microprocessor MIPS general-purpose register without inner interlocked pipelining-stage of interrupt spot, status register SR and exception procedure register EPC is saved in the interrupt stack setting in advance.
4. the method for claim 1, is characterized in that, the contextual information at current task scene is saved in the task stack setting in advance and is specifically comprised:
Successively the information in programmable counter PC, the SP at current task scene, related register and interrupt return address are saved in the task stack setting in advance, wherein said related register comprises SR general-purpose register relevant with other;
On-the-spot the current task of pointing to last pop down content pointer is saved in predefined function, wherein, the use of popping in the time recovering current task of the on-the-spot pointer of described current task.
5. the method for claim 1, is characterized in that, reporting system starts to enter interruption to be processed, and reads interrupt priority level, opens interruption, enables interrupt nesting, and in commission breaks after handling procedure, disabled interrupt, and reporting system exits to interrupt processing and specifically comprises:
Jump to operating system and interrupt entering OS_IntEnter function, reporting system starts to enter interruption to be processed;
The request interrupt priority level RIPL position of reading reason CAUSE register, obtains the priority of described interruption, and the priority of described interruption is set on the interrupt priority level IPL position of SR;
By the KSU position in SR, ERL position and the zero clearing of EXL position;
SP is successively decreased, distribute the parameter of described interrupt stack to described interrupt handling routine;
Obtain the priority of described interruption from the IPL position of described SR, jump to described interrupt handling routine according to this priority and process;
Revise the IPL position of described SR, and the ERL position of described SR and EXL position be set to zero, open interruption simultaneously, enable interrupt nesting;
Discharge described interrupt stack, and be 1 by the EXL position of described SR, disabled interrupt;
Jump to system break and exit OS_IntExit function, reporting system exits and interrupts processing.
6. an interrupt processing device, is characterized in that, is applicable to based on MIPS32 as processor and the platform using μ COS-II as operating system, and described device comprises:
Initialization module, in the time that system is carried out initialization, carries out initialization to interruption and driver thereof;
The first interruption processing module, the in the situation that of for generation interruption in the time carrying out current task, the contextual information of interrupt spot is saved in the interrupt stack setting in advance, and determine whether interrupt nesting, if the judgment is No, call the second interruption processing module, otherwise, the 3rd interruption processing module called;
The second interruption processing module, for the contextual information at current task scene being saved in to the task stack setting in advance, and moves on to described interrupt stack by stack pointer SP, calls the 3rd interruption processing module;
The 3rd interruption processing module, starts to enter for reporting system and interrupts processing, and reads interrupt priority level, open interruption, enable interrupt nesting, and in commission break after handling procedure, disabled interrupt, reporting system exits and interrupts processing, and judge whether in interrupt nesting, if the judgment is Yes, call and interrupt recovering module, otherwise calling task recovers module;
Interrupt recovering module, for recover the contextual information of the described current interrupt spot of preserving from described interrupt stack, and return to upper strata interruption and continue to carry out;
Task recovery module, for recover the contextual information at the described current task scene of preserving from described task stack, and returns to the described current task being interrupted and continues to carry out.
7. device as claimed in claim 6, is characterized in that, described initialization module specifically for:
Configure priority and the trigger mode of all interruptions, and forbid all interruptions, wherein, described trigger mode comprises: level triggers or edge-triggered;
Obtain the interrupt number of all interruptions, corresponding interrupt handling routine is corresponding with described interrupt number;
Before enabling to interrupt, interrupt handling routine is copied on its corresponding interrupt vector entry address, wherein, between described interrupt vector, be spaced apart 32 bytes.
8. device as claimed in claim 6, is characterized in that, described the first interruption processing module specifically for:
Information in the microprocessor MIPS general-purpose register without inner interlocked pipelining-stage of interrupt spot, status register SR and exception procedure register EPC is saved in the interrupt stack setting in advance.
9. device as claimed in claim 6, is characterized in that, described the second interruption processing module specifically for:
Successively the information in programmable counter PC, the SP at current task scene, related register and interrupt return address are saved in the task stack setting in advance, wherein said related register comprises SR general-purpose register relevant with other;
On-the-spot the current task of pointing to last pop down content pointer is saved in predefined function, wherein, the use of popping in the time recovering current task of the on-the-spot pointer of described current task.
10. device as claimed in claim 6, is characterized in that, described the 3rd interruption processing module specifically for:
Jump to operating system and interrupt entering OS_IntEnter function, reporting system starts to enter interruption to be processed;
The request interrupt priority level RIPL position of reading reason CAUSE register, obtains the priority of described interruption, and the priority of described interruption is set on the interrupt priority level IPL position of SR;
By the KSU position in SR, ERL position and the zero clearing of EXL position;
SP is successively decreased, distribute the parameter of described interrupt stack to described interrupt handling routine;
Obtain the priority of described interruption from the IPL position of described SR, jump to described interrupt handling routine according to this priority and process;
Revise the IPL position of described SR, and the ERL position of described SR and EXL position be set to zero, open interruption simultaneously, enable interrupt nesting;
Discharge described interrupt stack, and be 1 by the EXL position of described SR, disabled interrupt;
Jump to system break and exit OS_IntExit function, reporting system exits and interrupts processing.
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| CN107003965A (en) * | 2014-12-23 | 2017-08-01 | 英特尔公司 | Interrupted to user class application transmission |
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| CN106528461A (en) * | 2015-09-14 | 2017-03-22 | 三星电子株式会社 | Storage device and interrupt generation method thereof |
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| CN112685147A (en) * | 2019-10-18 | 2021-04-20 | 龙芯中科技术股份有限公司 | Interrupt response method, device and readable storage medium |
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| US11880706B2 (en) | 2021-02-22 | 2024-01-23 | Nanjing qinheng Microelectronics Co., Ltd. | Interrupt control system and method based on RISC-V |
| CN112559047A (en) * | 2021-02-22 | 2021-03-26 | 南京沁恒微电子股份有限公司 | RISC-V based interrupt control system and method |
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| CN113377511A (en) * | 2021-06-09 | 2021-09-10 | 杭州电子科技大学 | System and method for implementing interrupt nesting in an ARMv7 processor emulation system |
| CN113377511B (en) * | 2021-06-09 | 2024-03-26 | 杭州电子科技大学 | System and method for implementing interrupt nesting in ARMv7 processor simulation system |
| CN116382856A (en) * | 2023-06-02 | 2023-07-04 | 麒麟软件有限公司 | Method for enhancing system instantaneity based on virtualized nesting |
| CN116382856B (en) * | 2023-06-02 | 2023-09-26 | 麒麟软件有限公司 | Method for enhancing system instantaneity based on virtualized nesting |
| CN117193979A (en) * | 2023-09-08 | 2023-12-08 | 上海合芯数字科技有限公司 | Independent interrupt stack-based task processing method, device, terminal equipment and medium |
| CN117193979B (en) * | 2023-09-08 | 2024-02-23 | 上海合芯数字科技有限公司 | Independent interrupt stack-based task processing method, device, terminal equipment and medium |
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