CN103762838B - Enabling starting circuit used for high voltage DC-DC circuit - Google Patents
Enabling starting circuit used for high voltage DC-DC circuit Download PDFInfo
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- CN103762838B CN103762838B CN201410014358.XA CN201410014358A CN103762838B CN 103762838 B CN103762838 B CN 103762838B CN 201410014358 A CN201410014358 A CN 201410014358A CN 103762838 B CN103762838 B CN 103762838B
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Abstract
The invention discloses an enabling starting circuit used for a high voltage DC-DC circuit. According to the enabling starting circuit, a threshold voltage of a first NMOS serves as a first threshold, when a voltage of an EN pin of an enabling comparator is lower than the threshold voltage of the first NMOS, a whole system is stopped, and therefore the turn-off current of the system is zero; when the voltage of the EN pin is higher than the threshold voltage of the first NMOS, a loop is started, the loop can provide starting power for a band-gap reference circuit, the band-gap reference circuit can provide an accurate reference voltage for the enabling comparator after being started, and therefore the enabling comparator can monitor the voltage of the EN pin; when the voltage of the EN pin is larger than the threshold voltage, a whole subsequent DC-DC system is started, and the function of enabling an enabling threshold to be accurate is achieved; meanwhile, as the loop can control the voltage applied to the grid of the first NMOS, a bias current of the first NMOS can be controlled, a working current of the enabling starting circuit can be further controlled to be constant, and the working current cannot be changed along with changes of the input voltage of the EN pin.
Description
Technical field
The present invention relates to a kind of enable start-up circuit in high voltage DC-DC circuit, for height
In pressure dc-dc adhesive integrated circuit, it is achieved zero cut-off current and accurately enable threshold value and perseverance
Fixed operating current, and operating current is not with input voltage (VIN) and Enable Pin (EN) electricity
Buckling.
Background technology
In existing high pressure dc-dc adhesive integrated circuit, the maximum gate source of high-voltage MOSFET it
Between voltage Vgs be typically only capable to tolerate 5V voltage and between maximum drain-source voltage Vds can tolerate 5V extremely
The high pressure of 40V (or higher).Owing to there is no the 5V voltage of outside input, in order to realize precisely making
Can the enable that used of threshold value and start-up circuit, generally be required for consuming certain static state at off state
Electric current, such as ADP2301, when EN=0, reference voltage and enable comparator are work. or be
Realize zero cut-off current and cannot realize precisely enabling threshold value, such as LM2734, just with
The threshold voltage (cannot accomplish precisely) of MOSFET realizes turning off.Another way foot uses high pressure
JFET (such as MP1484) produces 5V voltage at chip internal, the most both can realize zero cut-off current
Can also realize precisely enabling, however it is necessary that use high pressure JFET, this can increase the processing step of production,
Increase production cost.
Summary of the invention
The problems referred to above existed due to prior art, the purpose of the present invention is to propose to a kind of high pressure
Enable start-up circuit in DC-DC circuit, it can solve problem above.
For achieving the above object, the present invention can be achieved by the following technical programs:
The positive input of one comparator is applied to the grid of the first NMOS tube by the first resistance R1,
The drain electrode of this NMOS tube connects after passing sequentially through the first PMOS and the second PMOS that source electrode is connected
Receiving the input of band-gap reference circuit, this band-gap reference circuit exports a reference voltage to described comparison
The reverse input end of device；
Described first resistance connects the drain electrode of the second NMOS tube, and the source electrode of this second NMOS tube is by the
Two resistance are connected to the 3rd end of band-gap reference circuit, and the source electrode of this first NMOS tube passes through the 3rd resistance
Connecting the 3rd end of described band-gap reference circuit, the drain electrode of described second PMOS is sequentially connected with the 3rd
After the source electrode of PMOS, the 3rd NMOS tube, the 4th NMOS tube, the 5th NMOS tube, the 5th
The source electrode of NMOS tube connects the 3rd end of this band-gap reference circuit described, the wherein leakage of the 3rd PMOS
Pole is connected with the drain electrode of the 3rd NMOS tube, the source electrode of the 3rd NMOS tube and the 4th NMOS tube
Drain electrode be connected, the source electrode of the 4th NMOS tube is connected with the drain electrode of the 5th PMOS；
The drain electrode of described second PMOS connects the source electrode of the 4th PMOS, the 4th PMOS
Drain electrode is connected to the grid of described second NMOS tube, and the drain electrode of the 4th PMOS is permanent by one
Stream source is connected to the 3rd end of described band-gap reference circuit, the grid of the 4th PMOS and described the
The grid of three PMOS is connected；
The above first PMOS, the 3rd PMOS, the 3rd NMOS tube, the 4th NMOS tube,
The grid of the 5th NMOS tube is connected with drain electrode.
As further characteristic of the invention, between the source electrode of described first PMOS and its grid, with
And between the source electrode of described PMOS and its grid, it is respectively equipped with the 4th resistance, and this first PMOS
The grid of grid and the second PMOS is connected.
As further characteristic of the invention, the positive input of described comparator passes sequentially through source electrode
The 6th NMOS tube, the 7th NMOS tube, the 8th NMOS tube and the 9th NMOS tube being connected with drain electrode
After, the 3rd end of described band-gap reference circuit it is connected to by the source electrode of the 9th NMOS tube, and should
The drain and gate of the NMOS tube of the six, the seven, the eight, the 9th is connected
Owing to using above technical scheme, the enable in high voltage DC-DC circuit of the present invention starts
Circuit, utilize the threshold voltage of the first NMOS tube as first threshold, when the EN foot enabling comparator
Voltage less than the threshold voltage of the first NMOS tube time, close whole system, the shutoff of such system
Electric current is just zero, when threshold value the first NMOS tube voltage that the voltage of EN foot is higher than, starts a ring
Road, this loop can provide one to start power supply supply band-gap reference circuit, and band-gap reference circuit starts
The most just can provide one accurately reference voltage Vbg to enable comparator, so enable comparator
Just can monitor the voltage of EN foot, when the voltage of EN foot is more than this enable threshold voltage, just start
Follow-up whole DC-DC system, it is achieved precisely enable the function of threshold value；The most above-mentioned loop can be controlled
System is applied to the voltage of the first NMOS tube grid, thus can control its bias current, and then controls
Enable the operating current of start-up circuit, be allowed to constant, and not with the change of input voltage EN foot voltage
And change.The present invention both can realize zero cut-off current, it is also possible to realizes enabling threshold value accurately, with
Time can control operating current and be allowed to constant, not with input voltage and Enable Pin change in voltage, with this
Simultaneously, it is not necessary to use high pressure JFET, use standard process flows and device to realize, reduce
Production cost.
Accompanying drawing explanation
Below according to the drawings and specific embodiments, the invention will be further described:
Fig. 1 is the circuit diagram of the present invention
Detailed description of the invention
As it is shown in figure 1, the enable start-up circuit in high voltage DC-DC circuit of the present invention, one
The positive input EN of comparator is applied to the grid of the first NMOS tube N1 by the first resistance R1,
The drain electrode of this NMOS tube N1 passes sequentially through the first PMOS P1 and the 2nd PMOS that source electrode is connected
The input of band-gap reference circuit BG it is connected to, this band-gap reference circuit BG output one ginseng after pipe P2
Examine the voltage vbg reverse input end to comparator；First resistance R1 connects the second NMOS tube N2
Drain electrode, the source electrode of this second NMOS tube N2 is connected to band-gap reference circuit BG by the second resistance R2
The 3rd end, the source electrode of this first NMOS tube N1 by the 3rd resistance R3 connect band-gap reference circuit BG
The 3rd end, the drain electrode of the second PMOS P2 be sequentially connected with the source electrode of the 3rd PMOS P3, the 3rd
After NMOS tube N3, the 4th NMOS tube N4, the 5th NMOS tube N5, the source of the 5th NMOS tube N5
Pole connects the 3rd end of this band-gap reference circuit BG, the wherein drain electrode and the 3rd of the 3rd PMOS P3
The drain electrode of NMOS tube N3 is connected, the source electrode of the 3rd NMOS tube N3 and the 4th NMOS tube N4
Drain electrode be connected, the source electrode of the 4th NMOS tube N4 is connected with the drain electrode of the 5th PMOS P5
Connect；The drain electrode of the second PMOS P2 connects the source electrode of the 4th PMOS P4, the 4th PMOS
The drain electrode of P4 is connected to the grid of the second NMOS tube N2, and the drain electrode of the 4th PMOS P4 is led to
Cross a constant-current source and be connected to the 3rd end of band-gap reference circuit BG, the grid of the 4th PMOS P4
It is connected with the grid of the 3rd PMOS P3；The above first PMOS P1, the 3rd PMOS
P3, the 3rd NMOS tube N3, the 4th NMOS tube N4, the grid of the 5th NMOS tube N5 and drain electrode phase
Connect.
In the present embodiment, between the source electrode of the first PMOS P1 and its grid, and described 2nd PMOS
The 4th resistance R4, and the grid of this first PMOS P1 it are respectively equipped with between the source electrode of pipe P2 and its grid
Pole is connected with the grid of the second PMOS P2；The positive input EN of comparator passes sequentially through source
Pole with drain electrode be connected the 6th NMOS tube N6, the 7th NMOS tube N7, the 8th NMOS tube N8 and
After 9th NMOS tube N9, it is connected to band-gap reference circuit BG by the source electrode of the 9th NMOS tube N9
The 3rd end, and the drain and gate of the NMOS tube of the six, the seven, the eight, the 9th is connected.
The present invention is when implementing, and EN foot voltage is applied to the grid of N1 by resistance R1, when EN foot
When voltage is less than the threshold voltage of N1, N1 does not has electric current pass through, thus P1 and P2 is all in pass
Disconnected state, BG_VDD is 0, and band-gap reference circuit (BG) is in non-powered state, hence without quiet
State electric current, follow-up whole system is also at off state, hence without quiescent current, it is achieved zero closes
Power-off stream.
When EN foot voltage gradually rises, during threshold voltage more than N1, N1 turns on, and electric current passes through
N1, the size of electric current is (Vg (N1)-Vth (N1))/R3, and P1 is turned on by this electric current.The electric current of P2 is
The mirror image of P1, this electric current obtained certain voltage by P3/N7/N8/N9, BG_VDD are upper before this, because of
And band-gap reference circuit BG starts to start.Band-gap reference circuit BG can shunt part stream after starting
Enter the electric current of P3.The electric current of P3 can be mirrored to P4, when the voltage of EN foot is the highest when, and P4
Electric current less than the current source of its drain terminal, thus the grid voltage of N2 is relatively low, and N2 is closed.
When the voltage of EN foot is further continued for rising, the electric current of P4 also can follow rising, until and its drain terminal
Current source is equal, and now N2 begins to turn on, and is pulled down by the grid voltage of N1, to maintain loop
Balance.
After this, it is further continued for raising the voltage of EN foot, then will not make the electric current liter in N1～P4
Height, the grid voltage of N1 keeps constant, it is achieved that constant operating current.
After band-gap reference circuit BG starts, Vbg exports a reference voltage accurately, after supply
EN comparator, EN comparator monitoring EN foot voltage, when EN foot voltage higher than threshold value time,
Then start follow-up whole system, it is thus achieved that enable threshold function accurately.
When the effect of the resistance that the grid of P1 and P2 is connect is such that in N1 shutoff, P1 and P2 also locates
In reliable turn-off state.
The effect of N3, N4, N5, N6 be when EN voltage rise too high time, the voltage of clamper EN foot,
So in actual application, EN foot directly can be received a PMOS by a resistance by client
Pipe and source electrode VIN (high pressure) foot of the second PMOS, help the design of client's simplified system.
The effect of P3, N7, N8, N9 is the voltage of clamper BG_VDD so that its voltage is generally in
(Vgs refers to the gate source voltage of N3/N4/N5/P3 to 4*Vgs.The gate source voltage of metal-oxide-semiconductor can be by its electricity
Stream and threshold voltage substantially determine, about 0.7-1V) voltage, it is ensured that band-gap reference has enough electricity
Source voltage can start, and is also prevented from the overtension of BG_VDD simultaneously.
But, above-mentioned detailed description of the invention is exemplary, is to preferably make this area skill
Art personnel are it will be appreciated that this patent, it is impossible to be not understood as including this patent the restriction of scope；As long as
Any equivalent change made according to spirit disclosed in this patent or modification, each fall within this patent and include
Scope.
Claims (3)
1. the enable start-up circuit in high voltage DC-DC circuit, it is characterised in that:
The positive input of one comparator is applied to the grid of the first NMOS tube, this NMOS tube by the first resistance R1
Drain electrode pass sequentially through the first PMOS and the second PMOS that source electrode is connected after be connected to the defeated of band-gap reference circuit
Entering end, this band-gap reference circuit exports the reference voltage reverse input end to described comparator；
Described first resistance connects the drain electrode of the second NMOS tube, and the source electrode of this second NMOS tube is by the second resistance even
Receiving the 3rd end of band-gap reference circuit, the source electrode of this first NMOS tube connects described band-gap reference by the 3rd resistance
3rd end of circuit, the drain electrode of described second PMOS is sequentially connected with the source electrode of the 3rd PMOS, the 3rd NMOS
After pipe, the 4th NMOS tube, the 5th NMOS tube, the source electrode of the 5th NMOS tube connects this band-gap reference electricity described
3rd end on road, wherein the drain electrode of the 3rd PMOS is connected with the drain electrode of the 3rd NMOS tube, the 3rd NMOS
The source electrode of pipe is connected with the drain electrode of the 4th NMOS tube, the source electrode of the 4th NMOS tube and the 5th NMOS tube
Drain electrode be connected；
The drain electrode of described second PMOS connects the source electrode of the 4th PMOS, and the drain electrode of the 4th PMOS is even
Receive the grid of described second NMOS tube, and the drain electrode of the 4th PMOS is connected to described band by a constant-current source
3rd end of gap reference circuit, the grid of the 4th PMOS is connected with the grid of described 3rd PMOS；
The above first PMOS, the 3rd PMOS, the 3rd NMOS tube, the 4th NMOS tube, the 5th
The grid of NMOS tube is connected with drain electrode.
Enable start-up circuit the most according to claim 1, it is characterised in that: the source of described first PMOS
Between pole and its grid, and between the source electrode of described second PMOS and its grid, be respectively equipped with the 4th resistance, and this first
The grid of PMOS and the grid of the second PMOS are connected.
Enable start-up circuit the most according to claim 1 and 2, it is characterised in that: described comparator is just
To input pass sequentially through source electrode with drain electrode be connected the 6th NMOS tube, the 7th NMOS tube, the 8th NMOS tube
After the 9th NMOS tube, it is connected to the 3rd end of described band-gap reference circuit by the source electrode of the 9th NMOS tube,
And the drain and gate of the NMOS tube of the six, the seven, the eight, the 9th is connected.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410014358.XA CN103762838B (en) | 2014-01-13 | 2014-01-13 | Enabling starting circuit used for high voltage DC-DC circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410014358.XA CN103762838B (en) | 2014-01-13 | 2014-01-13 | Enabling starting circuit used for high voltage DC-DC circuit |
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| Publication Number | Publication Date |
|---|---|
| CN103762838A CN103762838A (en) | 2014-04-30 |
| CN103762838B true CN103762838B (en) | 2017-01-11 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN201410014358.XA Active CN103762838B (en) | 2014-01-13 | 2014-01-13 | Enabling starting circuit used for high voltage DC-DC circuit |
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Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN114050715B (en) * | 2021-08-16 | 2024-07-16 | 西安鼎芯微电子有限公司 | High-voltage starting circuit with constant current function |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102200795A (en) * | 2010-03-25 | 2011-09-28 | 上海沙丘微电子有限公司 | High voltage band-gap reference and starting circuit |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20080157746A1 (en) * | 2006-12-29 | 2008-07-03 | Mediatek Inc. | Bandgap Reference Circuits |
| KR100940151B1 (en) * | 2007-12-26 | 2010-02-03 | 주식회사 동부하이텍 | Bandgap Voltage Reference Circuit |
| TWI356576B (en) * | 2008-04-23 | 2012-01-11 | Niko Semiconductor Co Ltd | High voltage start-up circuit with constant curren |
| KR101365100B1 (en) * | 2009-10-28 | 2014-02-20 | 아이와트 인크. | Low power consumption start-up circuit with dynamic switching |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102200795A (en) * | 2010-03-25 | 2011-09-28 | 上海沙丘微电子有限公司 | High voltage band-gap reference and starting circuit |
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Address after: 226017 Nantong science and Technology Industrial Park, Su Tong Road, Jiangsu, No. 14, No. 16 Patentee after: Dioo Microelectronic Co., Ltd. Address before: 201103, building 603, building 2, Hongqiao International Business Plaza, 2679 Hechuan Road, Shanghai, Minhang District Patentee before: Dioo Microelectronic Co., Ltd. |
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Address after: No.16, wei14 Road, Sutong science and Technology Industrial Park, Nantong, Jiangsu Province Patentee after: Jiangsu Dior Microelectronics Co., Ltd Address before: 226017 Nantong science and Technology Industrial Park, Su Tong Road, Jiangsu, No. 14, No. 16 Patentee before: DIAO MICROELECTRONICS Co.,Ltd. |
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Address after: 6 / F, building 8, Zilang science and Technology City, Nantong Innovation Zone, 60 Chongzhou Avenue, Nantong City, Jiangsu Province 226000 Patentee after: Jiangsu Dior Microelectronics Co., Ltd Address before: No.16, wei14 Road, Sutong science and Technology Industrial Park, Nantong, Jiangsu Province Patentee before: Jiangsu Dior Microelectronics Co., Ltd |