CN103761468A - Micro control chip provided with double CPUs (central processing units) - Google Patents
Micro control chip provided with double CPUs (central processing units) Download PDFInfo
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- CN103761468A CN103761468A CN201410015387.8A CN201410015387A CN103761468A CN 103761468 A CN103761468 A CN 103761468A CN 201410015387 A CN201410015387 A CN 201410015387A CN 103761468 A CN103761468 A CN 103761468A
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- 239000013078 crystal Substances 0.000 claims description 5
- 238000004519 manufacturing process Methods 0.000 claims description 2
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
- G06F21/60—Protecting data
- G06F21/604—Tools and structures for managing or administering access control systems
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- G—PHYSICS
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- G06Q—INFORMATION AND COMMUNICATION TECHNOLOGY [ICT] SPECIALLY ADAPTED FOR ADMINISTRATIVE, COMMERCIAL, FINANCIAL, MANAGERIAL OR SUPERVISORY PURPOSES; SYSTEMS OR METHODS SPECIALLY ADAPTED FOR ADMINISTRATIVE, COMMERCIAL, FINANCIAL, MANAGERIAL OR SUPERVISORY PURPOSES, NOT OTHERWISE PROVIDED FOR
- G06Q20/00—Payment architectures, schemes or protocols
- G06Q20/38—Payment protocols; Details thereof
- G06Q20/382—Payment protocols; Details thereof insuring higher security of transaction
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06Q—INFORMATION AND COMMUNICATION TECHNOLOGY [ICT] SPECIALLY ADAPTED FOR ADMINISTRATIVE, COMMERCIAL, FINANCIAL, MANAGERIAL OR SUPERVISORY PURPOSES; SYSTEMS OR METHODS SPECIALLY ADAPTED FOR ADMINISTRATIVE, COMMERCIAL, FINANCIAL, MANAGERIAL OR SUPERVISORY PURPOSES, NOT OTHERWISE PROVIDED FOR
- G06Q20/00—Payment architectures, schemes or protocols
- G06Q20/38—Payment protocols; Details thereof
- G06Q20/40—Authorisation, e.g. identification of payer or payee, verification of customer or shop credentials; Review and approval of payers, e.g. check credit lines or negative lists
- G06Q20/401—Transaction verification
- G06Q20/4014—Identity check for transactions
- G06Q20/40145—Biometric identity checks
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Abstract
The invention discloses a micro control chip provided with double CPUs (central processing units). The micro control chip comprises a first central processing unit, a second central processing unit and a central processing unit isolator. The first central processing unit is used for controlling an internal connection interface and an outlet of the micro control chip, and the second central processing unit serves as a coprocessor for the first central processing unit; provided with data features required by level-3 encryption module certification, the first central processing unit is in data communication with the second central processing unit through an asynchronous transceiver transmitter interface; the first central processing unit is disconnected from the second central processing unit through the central processing unit isolator so as to disconnect a memory subsystem between the first central processing unit and the second central processing unit. The micro control chip provided with the double CPUs can be deployed in any environments, so that development cost of safety equipment market can be greatly lowered, and development time can be saved.
Description
Technical Field
The invention relates to the technical field of electronics, in particular to a micro control chip with double CPUs (central processing units).
Background
At present, two main modes for completing online bank payment in a bank system are that one mode is a U-shaped mode, and the other mode is that confirmation is completed by using a mobile phone short message and an electronic password card distributed by a bank to complete payment. The inventor considers that the confirmation is completed by the electronic password card distributed by the bank after analyzing the prior art, and for the consumer, the electronic password card can only be deployed in a specific environment because the electronic password card is distributed by the bank, so that a technician is required to develop the electronic password card specially for the business of the bank, the development cost is increased, and the development time is saved.
Disclosure of Invention
To solve the problems of the prior art, embodiments of the present invention provide a micro control chip having dual Central Processing Units (CPUs). The technical scheme is as follows:
in one aspect, there is provided a micro control chip having a dual CPU, including: the micro control chip with the dual CPU comprises: the system comprises a first central processing unit, a second central processing unit and a central processing unit isolator; wherein,
the first central processing unit is used for controlling an internal connection interface and an output port of the micro control chip; the second central processing unit is a coprocessor of the first central processing unit, has data characteristics required by authentication of a 3-level encryption module, generates an encrypted random confirmation code according to an authorized payment protocol after identity authentication of a user, and sends the random confirmation code to a payment system through a universal asynchronous transceiver interface under the control of the first central processing unit;
the central processing unit isolator disconnects the first central processing unit from the second central processing unit, and disconnects a memory subsystem between the first central processing unit and the second central processing unit.
The technical scheme provided by the embodiment of the invention has the following beneficial effects:
the random confirmation code is sent to the payment system under the control of the first central processing unit, and the level 3 encryption module of the second central processing unit ensures the security of online payment of the user; the functions of the first central processing unit and the second central processing unit are divided into definite time division, so that the micro control chip with double CPUs can be deployed in any environment, the development cost of the safety equipment market is greatly reduced, and the development time is saved.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
FIG. 1 is a schematic structural diagram of a micro control chip with dual CPUs according to an embodiment of the present invention;
fig. 2 is a schematic structural diagram of an electronic payment system to which the embodiment of the present invention is applied.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
Example one
FIG. 1 is a schematic structural diagram of a micro control chip with dual CPUs according to an embodiment of the present invention; referring to fig. 1, a micro control chip 100 with dual CPUs provided in the embodiment of the present invention specifically includes: a first central processing unit 11, a second central processing unit 12, a central processor isolator 13.
The first central processing unit 11 is used for controlling the internal connection interface and the output port of the micro control chip 100; the second central processing unit 12 is a coprocessor of the first central processing unit 11, has data characteristics required for authentication of a 3-level encryption module, generates an encrypted random confirmation code according to an authorized payment protocol after identity authentication of a user is performed, and sends the random confirmation code to a payment system through a universal asynchronous receiver transmitter interface under the control of the first central processing unit 12;
the cpu isolator 13 disconnects the first cpu 11 from the second cpu 12, disconnecting the memory subsystem between the first cpu 11 and the second cpu 12.
The micro control chip with double CPUs provided by the embodiment of the invention ensures the safety of online payment of users by sending the random confirmation code to the payment system under the control of the first central processing unit 11 and the 3-level encryption module of the second central processing unit 12; by clearly dividing the functions of the first central processing unit 11 and the second central processing unit 12, the micro control chip with dual CPUs can be deployed in any environment, thereby greatly reducing the development cost of the safety equipment market and saving the development time.
Further, in the first embodiment, the memory subsystems of the first cpu 11 and the second cpu 12 are configured to: the memory device includes a command buffer memory of a first set byte, a data memory bank of a second set byte, a bus memory bank of a third set byte, an embedded flash memory of a fourth set byte, and an external memory interface for accessing an external device, where the first set byte, the second set byte, the third set byte, and the fourth set byte may be set according to a specific storage space, for example, the first set byte may be specifically 16KB, the second set byte may be specifically 32KB, the third set byte may be specifically 32KB, and the fourth set byte may be specifically 512 KB; the first cpu 11 and the second cpu 12 both execute commands from the corresponding bus banks, and the data banks and the bus banks form a continuous address space within a range from the data banks.
Further, in the first embodiment, the first central processing unit 11 and the second central processing unit 12 share the same clock source, and the first central processing unit 11 and the second central processing unit 12 each include an independent clock divider to set their respective clock frequencies; the clock divider is controlled by the peripheral bus interface of each central processing unit.
Further, in the first embodiment, the micro control chip 100 has three main clock sources, which include an external crystal clock and two internal oscillators, and further, the frequency of the crystal clock may be 13.56MHz, and the frequency of the internal oscillator may be 20 MHz; the first central processing unit 11 and the second central processing unit 12 move according to the crystal clock; after start-up, the first central processing unit 11 and the second central processing unit 12 can choose to switch to one of the two internal oscillators.
Further, in the first embodiment, the first central processing unit 11 and the second central processing unit 12 each control an independent 4-bit frequency divider to obtain respective derived clocks from the internal oscillator, and the clock frequencies of the derived clocks can move in the range of 192MHZ to 12 MHZ; the internal oscillator is employed for low power operation.
Further, in the first embodiment, the micro control chip 100 further includes a 5-socket debug interface for enabling debug settings; the debug interface of the first central processing unit 11 and the debug interface of the second central processing unit 12 are daisy-chained together; when the micro control chip 100 is in the development mode, the debugging interface is connected with the first central processing unit 11 and the second central processing unit 12; when the micro control chip 100 sets the start production mode, the debug interface of the second central processing unit 12 is removed.
Further, in the first embodiment, the debugging setting includes: scan test, boundary scan test between input and output, built-in self test of the memory of the static memory on all chips; the debug interface is not bonded to pins on the packaged device as a pad for wafer level probing.
Further, in the first embodiment, the micro-controller chip 100 stores 256-bit electric fuses as a unique ID or serial number; the electrical fuses are used for interface control of the internal die.
Further, in the first embodiment, the partition of the electrical fuse is 7 partitions in a 32-bit section, and is used for storing data of a user; each partition writes a corresponding protection program to prevent the data from being written.
Further, in the first embodiment, the electrical fuse is controlled by the second cpu 12.
Example two
FIG. 2 is a schematic diagram of an electronic payment system to which embodiments of the present invention are applicable; referring to fig. 2, an electronic payment system 200 provided in the embodiment of the present invention specifically includes: a mobile terminal 21, a payment system 22; the mobile terminal 21 is provided with the micro control chip 100 with dual CPUs in the first embodiment, and the payment system 22 may specifically be a bank authorized payment confirmation system; the mobile terminal 21 is also provided with a fingerprint authentication device 211 and a communication interface 212. This is explained below with reference to fig. 1.
When the user realizes payment through the internet, the mobile terminal 21 receives the confirmation information from the payment system 22, inputs a short message code through the mobile terminal 21, and sends the short message code to the payment system 22 through the communication interface 212 under the control of the first central processing unit 11 in the micro control chip 100 to complete the first step of confirmation; the user is authenticated by the fingerprint authentication device 211, and after the user authentication is passed, the second central processing unit 12 generates the encrypted random confirmation code according to the authorized payment protocol permitted by the payment system 22, and sends the random confirmation code to the payment system 22 through the communication interface 212 under the control of the first central processing unit 11, so as to complete the second step of confirmation. When the payment system 22 receives the short message code and the random confirmation code, corresponding deduction operation is performed from the online account corresponding to the user.
The electronic payment system provided by the embodiment of the invention respectively sends the short message code and the random confirmation code to the payment system 22 under the control of the first central processing unit 11, and confirms the user through the fingerprint authentication device 211, thereby realizing two-step confirmation, and ensuring the safety of online payment of the user; since the mobile terminal 21 is provided with the micro control chip 100 with dual CPUs in the first embodiment, a transaction can be completed through one mobile terminal 21 in the embodiment of the present invention, and convenience and rapidness are realized on the basis of ensuring transaction security.
Further, in the second embodiment, the communication interface 212 may specifically be a SIM card and/or Wifi or other communication interfaces accessing to a network, and may utilize the data transmission/Wifi network connection function of the SIM card to implement communication confirmation with the bank authorized payment confirmation system 22, so as to implement two-step confirmation and complete effective payment.
In addition, the mobile terminal 21 is configured as a main microcomputer control center of the embedded system, and the output ports (e.g., the communication interface 212) of the mobile terminal 21 are controlled by the first central processing unit 11. The first central processing unit 11 and the second central processing unit 12 inhibit the operation of the debug interface by the electrical fuse program and the binding program.
By utilizing the embodiment of the invention, firstly, the bank authorized payment confirmation system 22 can carry out deduction operation after the identity of the user is authenticated in two steps, thereby realizing double guarantee of the safety of user payment; secondly, the system is connected with a bank authorized payment confirmation system 22, payment is completed through an authorized payment protocol confirmed by the bank, and the micro control chip 100 with double CPUs is deployed on the mobile terminal 21, so that the development cost of the mobile terminal 21 is greatly reduced, and the development time is saved; in addition, the mobile terminal 21 is an integrated electronic device for online payment, so that convenience and rapidness are realized on the basis of ensuring the safety of transactions.
The above-mentioned serial numbers of the embodiments of the present invention are merely for description and do not represent the merits of the embodiments.
It will be understood by those skilled in the art that all or part of the steps for implementing the above embodiments may be implemented by hardware, or may be implemented by a program instructing relevant hardware, where the program may be stored in a computer-readable storage medium, and the above-mentioned storage medium may be a read-only memory, a magnetic disk or an optical disk, etc.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents, improvements and the like that fall within the spirit and principle of the present invention are intended to be included therein.
Claims (10)
1. A micro control chip with dual CPUs, comprising: the system comprises a first central processing unit, a second central processing unit and a central processing unit isolator; wherein,
the first central processing unit is used for controlling an internal connection interface and an output port of the micro control chip; the second central processing unit is a coprocessor of the first central processing unit, has data characteristics required by authentication of a 3-level encryption module, generates an encrypted random confirmation code according to an authorized payment protocol after identity authentication of a user, and sends the random confirmation code to a payment system through a universal asynchronous transceiver interface under the control of the first central processing unit;
the central processing unit isolator disconnects the first central processing unit from the second central processing unit, and disconnects a memory subsystem between the first central processing unit and the second central processing unit.
2. The micro control chip with dual CPUs as in claim 1, wherein the memory subsystem of the first and second CPU units is configured to:
the device comprises a first byte-set instruction buffer memory, a second byte-set data memory bank, a third byte-set bus memory bank, a fourth byte-set embedded flash memory and an external memory interface for accessing an external device;
the first central processing unit and the second central processing unit both execute commands from the respective corresponding bus banks, and the data banks and the bus banks form a continuous address space within a range from the data banks.
3. The micro control chip with dual CPUs as in claim 1,
the first central processing unit and the second central processing unit share the same clock source, and both the first central processing unit and the second central processing unit comprise independent clock frequency dividers for setting respective clock frequencies; the clock divider is controlled by the peripheral bus interface of each central processing unit.
4. The micro control chip with dual CPUs as in claim 3, wherein the micro control chip has three master clock sources including an external crystal clock and two internal oscillators; the first central processing unit and the second central processing unit move according to the crystal clock; after startup, the first central processing unit and the second central processing unit may select one of the two internal oscillators to be switched to.
5. The micro control chip with dual CPUs as in claim 4,
the first central processing unit and the second central processing unit each control an independent 4-bit frequency divider to derive respective derived clocks from the internal oscillator; the internal oscillator is employed for low power operation.
6. The micro control chip with dual CPUs as in claim 1,
the micro control chip also comprises a debugging interface with 5 sockets, and the debugging interface is used for starting debugging setting;
the debugging interface of the first central processing unit and the debugging interface of the second central processing unit are linked together in a daisy shape; when the micro control chip is in an expansion mode, the debugging interface is connected with the first central processing unit and the second central processing unit; when the micro control chip sets a production start mode, the debugging interface of the second central processing unit is removed.
7. The micro control chip with dual CPUs as in claim 6,
the debugging settings include: scan test, boundary scan test between input and output, built-in self test of the memory of the static memory on all chips; the debug interface is not bonded to pins on the packaged device as a pad for wafer level probing.
8. The micro control chip with dual CPUs as in any one of claims 1-7,
the micro control chip stores 256-bit electric fuses as unique ID or serial numbers; the electrical fuses are used for interface control of the internal die.
9. The micro control chip with dual CPUs as in claim 8,
the partition of the electric fuse is 7 partitions of a 32-bit section and is used for storing data of a user; each partition writes a corresponding protection program to prevent the data from being written.
10. The micro control chip with dual CPUs according to claim 9, wherein the electrical fuse is controlled by the second central processing unit.
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN105844318A (en) * | 2015-01-14 | 2016-08-10 | 南通格物电子科技有限公司 | Radio frequency identification tag, tag identification method, tag identification device and tag reader |
| CN108073543A (en) * | 2016-11-12 | 2018-05-25 | 北京迪文科技有限公司 | A kind of 8051 processors realize multinuclear interconnection SOC |
| WO2020015003A1 (en) * | 2018-07-16 | 2020-01-23 | 杨俊佳 | Chip based on local data transmission, and electronic device containing chip |
| CN110858254A (en) * | 2018-08-22 | 2020-03-03 | 北京芯愿景软件技术股份有限公司 | Safety chip |
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| CN101009556A (en) * | 2007-01-08 | 2007-08-01 | 中国信息安全产品测评认证中心 | Intelligent card and U disk compound device and its access security improvement method based on bidirectional authentication mechanism |
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| CN105844318A (en) * | 2015-01-14 | 2016-08-10 | 南通格物电子科技有限公司 | Radio frequency identification tag, tag identification method, tag identification device and tag reader |
| CN108073543A (en) * | 2016-11-12 | 2018-05-25 | 北京迪文科技有限公司 | A kind of 8051 processors realize multinuclear interconnection SOC |
| WO2020015003A1 (en) * | 2018-07-16 | 2020-01-23 | 杨俊佳 | Chip based on local data transmission, and electronic device containing chip |
| CN110858254A (en) * | 2018-08-22 | 2020-03-03 | 北京芯愿景软件技术股份有限公司 | Safety chip |
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Application publication date: 20140430 |