CN103746709B - Device for quasi-cyclic low-density parity check - Google Patents
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Abstract
The invention is applicable to the technical field of storage and provides a device for quasi-cyclic low-density parity check. The device comprises a variable node processing unit used for receiving codeword information of a to-be-decoded code and first information data which is returned by check node updating units after the check node updating units execute an update operation, and transmitting the codeword information to a first shift circuit; multiple layers of check node updating units, of which each layer of check node updating unit updates the codeword information and transmits the first information data obtained after updating to the variable node processing unit; the first shift circuit used for transmitting the codeword information to the check node updating units and returning the first information data obtained by the check node updating units after updating to the variable node processing unit; and a judgment output unit used for, after the device completes an iterative operation, judging and checking second information data obtained by the variable node processing unit after the variable node processing unit updates the first information data, and carrying out shift operation and outputting the second information data. Thus, the use of a hardware circuit for realizing a transitive relation is reduced, and the operating frequency of a decoder is accelerated.
Description
Technical field
The present invention relates to technical field of memory, more particularly, to a kind of device of quasi-circulating low-density parity check.
Background technology
Ldpc(low density parity check code, the decoder of low-density checksum) can be according to being
System bandwidth demand carries out paralell design with bandwidth, bandwidth and the proportional relation of chip area required for realizing.Current ssd
(solid state disk, solid state hard disc) controller reaches 1gb/s even more high to the decoding bandwidth requirement of ldpc, ldpc's
Decoder area and power consumption are referred to as constraining the principal element of ldpc bandwidth lifting.A kind of typical ldpc interpretation method is that layering is translated
Code method, in existing implementation method, is iterated computing with layer for order.Current layer obtains variable letter from variable node
Breath, according to the computing carrying out data after the relation displacement of variable node and current layer check-node, shifts extensive again after the completion of computing
Arrive initial order again and data is returned to variable node.In the process, the data of variable node needs to be shifted twice.
A set of shift circuit can be used, shift circuit is taken in displacement timesharing twice, so can bring extra decoding latency；Or make
Complete to shift with two sets of shift circuits, so can bring extra hardware circuit consumption.No matter adopted which kind of method, all cannot
The length of increase critical path avoiding, increase postpone, or increase chip area and power consumption.
As shown in figure 1, being a kind of traditional qc-ldpc(quasi-cyclic low density parity check
Code, the decoder of low-density checksum) structure, code word is stored in vnu(variable node when initial
Processing unit, variable node unit) in, during each layer of interative computation, according to the variable node of current layer
Unit vnu and cnu(check node updating units, check node unit) between relation, variable node information
Data passes to check node unit after shift_l circuit shift.After the completion of the check node unit of current layer updates,
According to the relation of current layer check-node and variable node, the information of check-node and the symbol letter of corresponding variable node
Breath passes to variable node by shift_r.Every time after the completion of iteration, made decisions according to the information of updated variable node
Verification.
In summary, existing quasi-circulating low-density parity check method in actual use it is clear that exist inconvenient and scarce
Fall into, it is therefore necessary to being improved.
Content of the invention
For above-mentioned defect, it is an object of the invention to provide a kind of device of quasi-circulating low-density parity check, with
Reduce the use of the hardware circuit realizing transitive relation, reduce chip area and power consumption, accelerate decoder operating frequency.
To achieve these goals, the present invention provides a kind of device of quasi-circulating low-density parity check, comprising:
Variable node unit, is connected with the first shift circuit, check node unit and judgement output unit respectively, described
Variable node unit receives codeword information to be decoded and the execution of described check node unit updates the first letter of return after operation
Breath data, and described codeword information is sent to the first shift circuit, and be sent to after the renewal of described first information data
Described judgement output unit；
Multilamellar check node unit, every layer of check node unit respectively with the first shift circuit and described variable node list
Unit connects, and described check node unit updates to the execution of described codeword information and operates, and the first information number that will obtain after updating
According to being sent to described variable node unit；
First shift circuit, is connected with described variable node unit and described check node unit respectively, described first shifting
Position circuit, while described codeword information is sent to described check node unit, obtains after described check node unit is updated
The first information data obtaining returns in described variable node unit；
Judgement output unit, is connected with described variable node unit, and described judgement output unit completes one in described device
Update, to described variable node unit, the second information data obtaining after described first information data after secondary interative computation to sentence
Determine and verify, and carry out output after shifting function.
According to described device, described device executes decoding operation in units of layer；During described decoding operation,
Whole variable node in every layer of check-node updating in corresponding check node unit and described variable node unit.
According to described device, described first shift circuit is according to the pass of described variable node and the check-node of current layer
Described codeword information is carried out being sent to described check node unit after shifting function by system.
According to described device, the relation of the check-node of described variable node and current layer includes pass between layers
It is information；Described relation information is stored in the internal memory of matrix information.
According to described device, the described first information data that described check node unit obtains after updating is by described
When first shift circuit is sent to described variable node unit, described first shift circuit allows the described of described variable node unit
First information data order is consistent with the data order of described variable node unit.
According to described device, the described first information data that described check node unit obtains after updating is sent to
During described variable node unit, shifting function is not carried out to described first information data.
According to described device, described judgement output unit includes:
Judge module, is connected with described variable node unit and the second shift circuit, completes an iteration in described device
After computing, the second information data receiving described variable node unit transmission is made decisions, obtain decoding result data, and will
Described decoding result data is sent to the second shift circuit；
Second shift circuit, is connected to described judging module, by described decoding result data according to current variable node with
Relation between initializaing variable node sequence exports after being shifted.
According to described device, each layer of decoding operation is divided into multiple cycles to carry out, each period treatment tentation data
Variable node.
The device of the quasi-circulating low-density parity check that the present invention provides achieves improved hierarchical decoder method, Jing Guo
The variable node information of one shift circuit writes back the information to variable node, in variable node while passing to check-node
The corresponding relation of the information data of data and check-node is consistent.After the completion of the check-node of current layer updates, school
Test nodal information and the symbolic information of variable node is directly passed to variable node, due to the now order of variable node and verification
The order of node is consistent, and data can directly carry out transmitting computing, without extra shifting function.Iteration completes
Afterwards, the information data of variable node is made decisions with verification, displacement exports after recovering initial order.Therefore, the present invention provides
The device of quasi-circulating low-density parity check during carrying out decoding operation, transmit between the layers by information node information
When do not need to return to the order of most original, directly transmitted using the relation between layer and layer and calculated.In iterative process
In data when be out of order, and entirely different with the initial order of variable node, at the end of iteration, recover initially suitable
Sequence.So it can be avoided that in an iterative process for keeping data order and the repetition shifting function that carries out, reduce chip area and
Power consumption, lifts the hardware speed of service.And the matrix information that the described device that the present invention provides is deposited is not original matrix letter
Breath, but the relation information between layer and layer；The use of the hardware circuit realizing transitive relation can be reduced, reduce chip area
And power consumption, accelerate decoder operating frequency.
Brief description
Fig. 1 is the apparatus structure schematic diagram of the quasi-circulating low-density parity check providing in prior art；
Fig. 2 is the apparatus structure schematic diagram of the quasi-circulating low-density parity check that first embodiment of the invention provides；
Fig. 3 is the apparatus structure schematic diagram of the quasi-circulating low-density parity check that second embodiment of the invention provides；
Fig. 4 is the apparatus structure schematic diagram of the quasi-circulating low-density parity check that third embodiment of the invention provides.
Specific embodiment
In order that the objects, technical solutions and advantages of the present invention become more apparent, below in conjunction with drawings and Examples, right
The present invention is further elaborated.It should be appreciated that specific embodiment described herein is only in order to explain the present invention, and
It is not used in the restriction present invention.
Referring to Fig. 2, in the first embodiment of the present invention, there is provided a kind of device of quasi-circulating low-density parity check
100, comprising:
Variable node unit 10, respectively with the first shift circuit 20, check node unit 30 and judgement output unit 40
Connect, described variable node unit 10 receives codeword information to be decoded and described check node unit 30 execution updates after operating
The first information data returning, and described codeword information is sent to the first shift circuit 20, and by described first information number
According to update after be sent to described judgement output unit 40；
Multilamellar check node unit 30, every layer of check node unit 30 respectively with the first shift circuit 20 and described variable
Node unit 10 connects, and described check node unit 30 updates to the execution of described codeword information and operates, and will obtain after updating
First information data is sent to described variable node unit 10；
First shift circuit 20, is connected with described variable node unit 10 and described check node unit 30 respectively, described
First shift circuit 20 while described codeword information is sent to described check node unit 30, by described check-node list
The first information data that unit 30 obtains after updating returns in described variable node unit 10；
Judgement output unit 40, is connected with described variable node unit 10, and described judgement output unit 40 is in described device
After completing an iteration computing, described variable node unit 10 is updated with the second Information Number obtaining after described first information data
According to making decisions and verify, and export after carrying out shifting function.
In this embodiment, the device 100 of quasi-circulating low-density parity check carries out hierarchical decoder computing.Specifically standard is followed
The device 100 of ring low-density checksum executes decoding operation in units of layer；During described decoding operation, every layer more
Newly whole variable node in the check-node in corresponding check node unit 30 and described variable node unit 10.Starting
When carrying out decoding operation, variable node unit 10 receives codeword information to be decoded, then described codeword information is sent to
One shift circuit 20.First shift circuit 20, will while described codeword information is sent to described check node unit 30
The first information data that described check node unit 30 obtains after updating returns in described variable node unit 10；First displacement
Described codeword information is carried out passing after shifting function by circuit 20 according to the relation of described variable node and the check-node of current layer
Deliver to the check node unit 30 of current layer.Wherein, the relation of the check-node of described variable node and current layer include layer with
Relation information between layer；Described relation information is stored in the internal memory of matrix information.Then, the check node unit of current layer
30 pairs of described codeword information execution update and operate, and the first information data that will obtain after updating is sent to described variable node list
Unit 10；Check node unit 30 updates operation to the execution of described codeword information, and the first information data biography that will obtain after updating
Deliver to described variable node unit 10.Judgement output unit 40 is after described device completes an iteration computing to described variable section
The second information data that dot element 10 obtains after updating described first information data makes decisions and verifies, and carries out shifting function
After export.Thus, the device 100 of quasi-circulating low-density parity check achieves improved hierarchical decoder method, it can be avoided that
The repetition shifting function carrying out for keeping data order in iterative process, reduces chip area and power consumption, and lifting hardware runs
Speed.Wherein, while from variable node unit 10 transmission codeword information to the first shift circuit 20, variable section will also be transmitted
Point information.First information data includes check-node information and symbolic information.Second information data includes variable node Information Number
According to this and check information data etc..
In addition, in one embodiment of the invention, described first letter that check node unit 30 obtains after updating
Breath data is when being sent to described variable node unit 10 by described first shift circuit 20, and described first shift circuit 20 allows variable
The described first information data order of node unit 10 and the data order of described variable node unit 10 are consistent, and thus may be used
Directly to enter row operation, save circuit overhead.
Referring to Fig. 3, in the second embodiment of the present invention, judgement output unit 40 includes:
Judge module 41, is connected with described variable node unit 10 and the second shift circuit 42, completes one in described device
After secondary interative computation, the second information data receiving described variable node unit 10 transmission is made decisions, obtain decoding number of results
According to, and described decoding result data is sent to the second shift circuit 42；
Second shift circuit 42, is connected to described judging module, by described decoding result data according to current variable node
Relation and initializaing variable node sequence between exports after being shifted.
In this embodiment, the described first information data that check node unit 30 obtains after updating is sent to described
During variable node unit 10, shifting function is not carried out to described first information data.After completing an iteration computing, in output
During decoding result data, just this data is shifted.Preferably, each layer of decoding operation is divided into multiple cycles to carry out, often
The variable node of individual period treatment tentation data.Specifically, the variable node number of each period treatment is above-mentioned according to system
Layer operation, can be carried out according to system bandwidth demand piecemeal, a number of variable node information of every piece of correspondence.I.e. each layer
Updating operation can be divided into multiple cycles to carry out, a number of variable node of each period treatment, thus realize to performance and
The compromise further of chip cost.In each layer of operation, the check-node data of this layer is believed according to all of variable node
Breath data is updated, and if in having carried out piecemeal operation in layer, the renewal of check-node data will divide multiple cycles to complete.
Therefore, the device 100 execution decoding operation of the quasi-circulating low-density parity check that the multiple embodiment of the present invention provides
It is belonging to hierarchical decoder.Variable node data transmit between the layers when it is not necessary to return to the initially suitable of variable node
Sequence, directly according to relation transmission data between layers.In the internal memory of storage matrix information, deposit is not the former of matrix
Beginning information, but matrix transitive relation information between layers.At the end of decoding, using 42 decodings of the second shift circuit
Result returns to initial order, and the data of this second shift circuit 42 is the decoding result after judgement, the decoding being used
Circuit is simple more than decoding circuit between layers.Therefore, device 100 device of quasi-circulating low-density parity check can have
The reduction chip area of effect, reduces chip area, lifts the decoder speed of service.
Referring to Fig. 4, in the third embodiment of the present invention, there is provided the device 100 of quasi-circulating low-density parity check.?
In this embodiment, write back while passing to check-node to variable node, variable through the variable node information of shift_l
The corresponding relation of the information data of the information data in node and check-node is consistent.Update in the check-node of current layer
After the completion of, the symbolic information of check-node information and variable node is directly passed to variable node, due to now variable node
Order and the order of check-node be consistent, data can directly carry out transmitting computing, without extra displacement behaviour
Make.After the completion of iteration, verification is made decisions to the information data of variable node, displacement exports after recovering initial order.
Specifically, vnu is variable node unit 10, deposits all variable node information.Cnu is check node unit 30,
Deposit the check-node information of current operation layer.Shift_l is the first shift circuit 20, executes multiple inputs, each input bag
Shifting function containing multi-bit data.Shift is the second shift circuit 42, executes multiple inputs, and each input comprises 1 bit number
According to shifting function.Decision executes the judgement to variable node data and verification operation.First, code word to be decoded is believed
Breath is written to vnu(variable node unit 10)；Then, execute layer operation, according to the pass of variable node and current layer check-node
System, passes to check-node, described relation information is stored in internal memory, in real time from internal memory after variable node data is shifted
Read and execute corresponding shifting function to shift_l；Hereafter, check-node (i.e. check node unit 30) execution updates operation；
Terminal check node updates the data after updating and symbolic information transmission back to variable node (i.e. variable node unit 10).?
After the completion of an iteration, decision module (i.e. judge module 41) is entered to the data of variable node (i.e. variable node unit 10)
Row judgement and verification, are then passed through displacement output, the foundation of displacement is between current variable node and initializaing variable node sequence
Relation, described relation information deposits in internal memory.
The data of variable node, after shift_l displacement, is consistent with the ordering relation of the check-node of current layer,
Variable node data after number of times displacement writes back in vnu.After the completion of current layer iteration, obtain the check-node number that have updated
Order according to, the number of times now order of check-node data and current layer check-node is consistent, and is directly passed to vnu to change
Amount node is updated, and the variable node data order after renewal keeps constant.So far complete the interative computation of current layer, open
Begin the interative computation of next layer, the variable node data of current layer through shift(the second shift circuit 42) shift_l(
One shift circuit 20) pass to the check-node of next layer, in order to allow the data order of variable node and the verification section of next layer
Dot sequency is consistent, shift(the second shift circuit 42) shift_l(the first shift circuit 20) execute is current layer number evidence
Order arrives the displacement of next layer data order.
In sum, the device of the quasi-circulating low-density parity check that the present invention provides achieves improved hierarchical decoder side
Method, writes back to variable node, variable section through the variable node information of the first shift circuit while passing to check-node
The corresponding relation of the information data of the information data in point and check-node is consistent.Update in the check-node of current layer
Cheng Hou, is directly passed to variable node the symbolic information of check-node information and variable node, due to now variable node
The order of order and check-node is consistent, and data can directly carry out transmitting computing, without extra shifting function.
After the completion of iteration, verification is made decisions to the information data of variable node, displacement exports after recovering initial order.Therefore, this
, during carrying out decoding operation, information node information is in layer and layer for the device of the quasi-circulating low-density parity check of bright offer
Between transmit when do not need to return to the order of most original, directly transmitted using the relation between layer and layer and calculated.?
It is out of order during data in iterative process, and entirely different with the initial order of variable node, at the end of iteration, recover
Initial order.So it can be avoided that the repetition shifting function carrying out for keeping data order in an iterative process, reduce chip
Area and power consumption, lift the hardware speed of service.And the matrix information that the described device that the present invention provides is deposited is not original
Matrix information, but the relation information between layer and layer；The use of the hardware circuit realizing transitive relation can be reduced, reduce core
Piece area and power consumption, accelerate decoder operating frequency.
Certainly, the present invention also can have other various embodiments, in the case of without departing substantially from present invention spirit and its essence, ripe
Know those skilled in the art and work as and various corresponding changes and deformation can be made according to the present invention, but these corresponding changes and change
Shape all should belong to the protection domain of appended claims of the invention.
Claims (7)
1. a kind of device of quasi-circulating low-density parity check is it is characterised in that include:
Variable node unit, is connected with the first shift circuit, check node unit and judgement output unit, described variable respectively
Node unit receives codeword information to be decoded and the execution of described check node unit updates the first information number of return after operation
According to, and described codeword information is sent to the first shift circuit, and described by being sent to after the renewal of described first information data
Judgement output unit；
Multilamellar check node unit, every layer of check node unit is connected with the first shift circuit and described variable node unit respectively
Connect, described check node unit updates operation to the execution of described codeword information, and the first information data biography that will obtain after updating
Deliver to described variable node unit；
First shift circuit, is connected with described variable node unit and described check node unit respectively, described first displacement electricity
Road, while described codeword information is sent to described check node unit, obtains after described check node unit is updated
First information data returns in described variable node unit；
Judgement output unit, is connected with described variable node unit, and described judgement output unit completes once to change in described device
For after computing to described variable node unit update described first information data after obtain the second information data make decisions and
Verification, and carry out output after shifting function；
When the described first information data that described check node unit obtains after updating is sent to described variable node unit,
Shifting function is not carried out to described first information data.
2. device according to claim 1 is it is characterised in that described device executes decoding operation in units of layer；Institute
During stating decoding operation, in every layer of check-node and described variable node unit updating in corresponding check node unit
Whole variable nodes.
3. device according to claim 2 is it is characterised in that described first shift circuit according to described variable node and is worked as
Described codeword information is carried out being sent to described check node unit after shifting function by the relation of the check-node of front layer.
4. device according to claim 3 is it is characterised in that the relation of the check-node of described variable node and current layer
Including relation information between layers；Described relation information is stored in the internal memory of matrix information.
5. device according to claim 1 it is characterised in that described check node unit will update after obtain described in
When first information data is sent to described variable node unit by described first shift circuit, described first shift circuit allows described
The described first information data order of variable node unit and the data order of described variable node unit are consistent.
6. device according to claim 1 is it is characterised in that described judgement output unit includes:
Judge module, is connected with described variable node unit and the second shift circuit, completes an iteration computing in described device
Afterwards the second information data receiving described variable node unit transmission is made decisions, obtain decoding result data, and will be described
Decoding result data is sent to the second shift circuit；
Second shift circuit, is connected to described judge module, by described decoding result data according to current variable node with initial
Relation between variable node order exports after being shifted.
7. device according to claim 2 is it is characterised in that each layer of decoding operation is divided into multiple cycles to carry out, often
The variable node of individual period treatment tentation data.
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| CN101777920A (en) * | 2009-12-24 | 2010-07-14 | 北京韦加航通科技有限责任公司 | Coding method and coding and decoding device of low-density parity check code |
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| CN101777920A (en) * | 2009-12-24 | 2010-07-14 | 北京韦加航通科技有限责任公司 | Coding method and coding and decoding device of low-density parity check code |
Non-Patent Citations (2)
| Title |
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| QC-LDPC码的研究与FPGA实现;梁晓东;《中国优秀硕士学位论文全文数据库信息科技辑》;20101215;第31页第4.3.1节、第33-36页4.3.2节，图4.9 * |
| 准循环低密度校验码译码器的设计与实现;何庆涛;《中国优秀硕士学位论文全文数据库信息科技辑》;20090115;第43页5.3.1节、第44页5.3.2节、第45-46页5.3.3节，图5.7 * |
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