CN103745928A - Preparation method of transistor with stressed channel and transistor with stressed channel - Google Patents
Preparation method of transistor with stressed channel and transistor with stressed channel Download PDFInfo
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- CN103745928A CN103745928A CN201310720622.7A CN201310720622A CN103745928A CN 103745928 A CN103745928 A CN 103745928A CN 201310720622 A CN201310720622 A CN 201310720622A CN 103745928 A CN103745928 A CN 103745928A
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- 238000002360 preparation method Methods 0.000 title claims abstract description 11
- 239000010410 layer Substances 0.000 claims abstract description 121
- 239000011241 protective layer Substances 0.000 claims abstract description 32
- 239000000758 substrate Substances 0.000 claims abstract description 15
- 239000000463 material Substances 0.000 claims description 27
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 20
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 10
- 239000000377 silicon dioxide Substances 0.000 claims description 10
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 10
- 230000000694 effects Effects 0.000 claims description 8
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims description 6
- 229910052804 chromium Inorganic materials 0.000 claims description 5
- 229910052737 gold Inorganic materials 0.000 claims description 5
- 229910052763 palladium Inorganic materials 0.000 claims description 5
- 229910052697 platinum Inorganic materials 0.000 claims description 5
- 229910052719 titanium Inorganic materials 0.000 claims description 5
- 229910052721 tungsten Inorganic materials 0.000 claims description 5
- 238000000034 method Methods 0.000 abstract description 8
- 238000009413 insulation Methods 0.000 abstract 2
- 239000004065 semiconductor Substances 0.000 description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 238000012536 packaging technology Methods 0.000 description 1
- 239000002210 silicon-based material Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
- H01L29/7845—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being a conductive material, e.g. silicided S/D or Gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
- H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Materials Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Thin Film Transistor (AREA)
- Formation Of Insulating Films (AREA)
Abstract
The invention provides a preparation method of a transistor with a stressed channel and the transistor with the stressed channel. The method comprises the following steps: providing a substrate which comprises a device layer; forming a transistor, including a source electrode and a drain electrode formed in the device layer and a grid electrode formed on the surface of the device layer; forming an insulation protective layer on the surface of the device layer; forming a stress layer on the surface of the insulation protective layer; suspending the device layer where there is a conducting channel of the grid electrode of the transistor such that the device layer is curled under the action of the stress layer, thus leading to tensile strain of the conducting channel of the grid electrode of the transistor. The invention has advantages as follows: the device layer where there is the grid electrode is curled freely and the device layer undergoes strain under the action of the tensile strain; and as the strain is introduced by physical deformation, strain is stable and is not easy to disappear.
Description
Technical field
The present invention relates to field of semiconductor devices, relate in particular to and a kind ofly there is the transistor preparation method of strained-channel and there is the transistor of strained-channel.
Background technology
Along with dwindling of dimensions of semiconductor devices, traditional body silicon materials are just approaching physics limit.But the requirement that MOS device drive current is promoted is but more and more higher.In order to improve the usefulness of MOS device, strained silicon technology is adopted the driving force with motor current by industry.
So-called strain gauge technique is to introduce stress at the conducting channel place of MOS device, makes the semi-conducting material generation strain at this place, and then improves the technology of the carrier mobility of conducting channel.The carrier mobility that improves conducting channel is conducive to improve the drive current of MOS device.
In the prior art, by introduce dissimilar materials in substrate, for example, in silicon substrate, introducing germanium silicon layer, and then make semi-conducting material generation strain by lattice mismatch stress, is a kind of technology the most generally adopting.But the method complex process and cost costliness, and strain gauge material is difficult to keep strain regime in follow-up semiconductor planar technique and packaging technology always.
Therefore, how in the conducting channel of MOS device, to introduce stable stress, make the semi-conducting material generation strain of conducting channel, be prior art problem demanding prompt solution.
Summary of the invention
Technical problem to be solved by this invention is that providing a kind of can introduce the transistor preparation method with strained-channel of stable stress and have the transistor of strained-channel in the conducting channel of MOS device.
In order to address the above problem, the invention provides a kind of transistor preparation method with strained-channel, comprise the steps: to provide substrate, described substrate comprises the buried regions of supporting layer, support layer surface and the device layer on buried regions surface; Form transistor, be included in and in device layer, form source electrode and drain electrode, and form grid on device layer surface; On device layer surface, form insulating protective layer, described insulating protective layer also covers described grid; On described insulating protective layer surface, form stressor layers, described stressor layers can be introduced tensile stress in device layer; By the mode of removing part of devices layer and part buried regions, make the device layer of transistor gate conducting channel position unsettled, device layer occurs curling under the effect of stressor layers, thereby makes transistor gate conducting channel generation tensile strain.
Optionally, the material of described device layer is monocrystalline silicon, and the material of described strained layer is selected from one or more in W, Ti, Cr, Pt, Au, Pd.
Optionally, the material of described buried regions is selected from the one in silica and silicon nitride.
Optionally, the material of described insulating protective layer is selected from the one in silica and silicon nitride.
The present invention further provides a kind of transistor with strained-channel, comprised substrate and transistor, described substrate comprises the buried regions of supporting layer, support layer surface and the device layer on buried regions surface; Described transistor is included in source electrode and the drain electrode in device layer, and the grid on device layer surface; In device layer surface coverage, have insulating protective layer, described insulating protective layer also covers described grid; Described insulating protective layer surface coverage has stressor layers, and described stressor layers is introduced tensile stress in device layer; The device layer of transistor gate conducting channel position is because part of devices layer and part buried regions are removed and unsettled, and it is curling that device layer occurs under the effect of stressor layers, thereby make transistor gate conducting channel generation tensile strain.
Optionally, the material of described device layer is monocrystalline silicon, and the material of described strained layer is selected from one or more in W, Ti, Cr, Pt, Au, Pd.
Optionally, the material of described buried regions is selected from the one in silica and silicon nitride.
Optionally, the material of described insulating protective layer is selected from the one in silica and silicon nitride.
The invention has the advantages that, the device layer of grid region is freely curling, and device layer, under the effect of tensile stress, strain occurs, and this strain is introduced by physical deformation, and therefore strain stable is difficult for disappearing.
Accompanying drawing explanation
It shown in accompanying drawing 1, is the implementation step schematic diagram of the specific embodiment of the invention.
Accompanying drawing 2A is to shown in accompanying drawing 2E being the process chart of the specific embodiment of the invention.
Embodiment
Below in conjunction with accompanying drawing, the transistorized embodiment that has the transistor preparation method of strained-channel and have a strained-channel provided by the invention is elaborated.
Shown in accompanying drawing 1, be the implementation step schematic diagram of the specific embodiment of the invention, comprise: step S10, substrate is provided, described substrate comprises the buried regions of supporting layer, support layer surface and the device layer on buried regions surface; Step S11, forms transistor, is included in and in device layer, forms source electrode and drain electrode, and form grid on device layer surface; Step S12, forms insulating protective layer on device layer surface, and described insulating protective layer also covers described grid; Step S13, forms stressor layers on described insulating protective layer surface, and described stressor layers can be introduced tensile stress in device layer; Step S14, makes the device layer of transistor gate conducting channel position unsettled by the mode of removing part of devices layer and part buried regions, and device layer occurs curling under the effect of stressor layers, thereby makes transistor gate conducting channel generation tensile strain.
Accompanying drawing 2A is to shown in accompanying drawing 2E being the process chart of the specific embodiment of the invention.
Shown in accompanying drawing 2A, refer step S10, provides substrate 200, and described substrate comprises the buried regions 202 of supporting layer 201, support layer surface and the device layer 203 on buried regions surface.The material of described supporting layer 201 and device layer 203 can be any one the common semi-conducting material including monocrystalline silicon.The material of described buried regions 202 can be the one in silica and silicon nitride.The material of described buried regions 202 should be with the material difference of device layer 203 and supporting layer 201, so that can selective removal in subsequent technique.
Shown in accompanying drawing 2B, refer step S11, forms transistor, is included in device layer 203 and forms source electrode 211 and drain 212, and form grids 213 on device layer 203 surfaces.Source electrode 211 and drain electrode 212 are by form source dopant region 2111 and drain doping region territory 2121 by doping in device layer 203, and forming source electrode 2112 and drain electrode 2122, grid 213 forms at device layer 203 superficial growth gate dielectric layers 2131 and gate electrode 2132.The material that the material of gate electrode 2132 can adopt metal level to be ductile, can guarantee can not rupture in the situation that generation is curling.
Shown in accompanying drawing 2C, refer step S12, forms insulating protective layer 220 on the surface of device layer 203, and described insulating protective layer 220 also covers described grid 213.The material of described insulating protective layer 220 is selected from the one in silica and silicon nitride.The object of described insulating protective layer 220 is to guarantee to isolate between source electrode 2112, drain electrode 2122 and gate electrode 2132, can not be short-circuited in the surface of device layer 203.Insulating protective layer 220 in this step can be continuous or patterned.
Shown in accompanying drawing 2D, refer step S13, forms stressor layers 230 on described insulating protective layer 220 surfaces, and described stressor layers 230 can be introduced tensile stress in device layer 203.In the execution mode that is monocrystalline silicon at the material of device layer 203, the material of described stressor layers 230 can be for example one or more in W, Ti, Cr, Pt, Au, Pd.Stressor layers 230 in this step can be continuous or patterned.
Shown in accompanying drawing 2E, refer step S14, by the mode of removing part of devices layer 203 and part buried regions 202, make the device layer of transistor gate conducting channel position unsettled, device layer occurs curling under the effect of stressor layers, thereby makes transistor gate conducting channel generation tensile strain.Described removal part of devices layer 203 should at least be removed the device layer 203 around source electrode 211, drain electrode 212 and 213 3 sides of grid, make grid 213 regions can be freely curling, and guarantee source electrode 211, drain electrode 212 and the structural integrity of grid 213, can not destroy transistor arrangement.Described removal part buried regions 202 should be removed device layer 203 buried regions 202 of part institute circle zone and remove, to guarantee that grid 213 regions can be freely curling.Device layer 203 is insulated protective layer 220 and stressor layers 230 covers; therefore should form patterned insulating protective layer 220 and stressor layers 230 when forming insulating protective layer 220 and stressor layers 230; retain corrosion window; can also form continuous insulating protective layer 220 and stressor layers 230, and in this step the insulating protective layer of corresponding part 220 and stressor layers 230 be removed.Grid 213 and corresponding device layer 203 occur curling after, under the effect of tensile stress, there is strain in device layer 203.And this strain is introduced by physical deformation, therefore strain stable, is difficult for disappearing.
The above is only the preferred embodiment of the present invention; it should be pointed out that for those skilled in the art, under the premise without departing from the principles of the invention; can also make some improvements and modifications, these improvements and modifications also should be considered as protection scope of the present invention.
Claims (8)
1. a transistor preparation method with strained-channel, is characterized in that, comprises the steps:
Substrate is provided, and described substrate comprises the buried regions of supporting layer, support layer surface and the device layer on buried regions surface;
Form transistor, be included in and in device layer, form source electrode and drain electrode, and form grid on device layer surface;
On device layer surface, form insulating protective layer, described insulating protective layer also covers described grid;
On described insulating protective layer surface, form stressor layers, described stressor layers can be introduced tensile stress in device layer;
By the mode of removing part of devices layer and part buried regions, make the device layer of transistor gate conducting channel position unsettled, device layer occurs curling under the effect of stressor layers, thereby makes transistor gate conducting channel generation tensile strain.
2. the transistor preparation method with strained-channel according to claim 1, is characterized in that, the material of described device layer is monocrystalline silicon, and the material of described strained layer is selected from one or more in W, Ti, Cr, Pt, Au, Pd.
3. the transistor preparation method with strained-channel according to claim 1, is characterized in that, the material of described buried regions is selected from the one in silica and silicon nitride.
4. the transistor preparation method with strained-channel according to claim 1, is characterized in that, the material of described insulating protective layer is selected from the one in silica and silicon nitride.
5. there is a transistor for strained-channel, comprise substrate and transistor, it is characterized in that,
Described substrate comprises the buried regions of supporting layer, support layer surface and the device layer on buried regions surface;
Described transistor is included in source electrode and the drain electrode in device layer, and the grid on device layer surface;
In device layer surface coverage, have insulating protective layer, described insulating protective layer also covers described grid;
Described insulating protective layer surface coverage has stressor layers, and described stressor layers is introduced tensile stress in device layer;
The device layer of transistor gate conducting channel position is because part of devices layer and part buried regions are removed and unsettled, and it is curling that device layer occurs under the effect of stressor layers, thereby make transistor gate conducting channel generation tensile strain.
6. the transistor with strained-channel according to claim 5, is characterized in that, the material of described device layer is monocrystalline silicon, and the material of described strained layer is selected from one or more in W, Ti, Cr, Pt, Au, Pd.
7. the transistor with strained-channel according to claim 5, is characterized in that, the material of described buried regions is selected from the one in silica and silicon nitride.
8. the transistor with strained-channel according to claim 5, is characterized in that, the material of described insulating protective layer is selected from the one in silica and silicon nitride.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310720622.7A CN103745928B (en) | 2013-12-24 | 2013-12-24 | There is the transistor preparation method of strained-channel and there is the transistor of strained-channel |
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| CN201310720622.7A CN103745928B (en) | 2013-12-24 | 2013-12-24 | There is the transistor preparation method of strained-channel and there is the transistor of strained-channel |
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| CN103745928A true CN103745928A (en) | 2014-04-23 |
| CN103745928B CN103745928B (en) | 2016-08-24 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109166790A (en) * | 2018-07-28 | 2019-01-08 | 西安交通大学 | A method of utilizing perovskite oxide piezoelectric membrane on metal stresses layer removing graphene |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1507071A (en) * | 2002-12-12 | 2004-06-23 | �Ҵ���˾ | Field effect transistor with stressed channel and producing method thereof |
| WO2004089811A2 (en) * | 2003-04-11 | 2004-10-21 | Paul Scherrer Institut | Method for manufacturing an electro-mechanical component and an electro-mechanical component, such as a strained si fin-fet |
| CN1790715A (en) * | 2004-12-15 | 2006-06-21 | 国际商业机器公司 | Structure and method to generate local mechanical gate stress for MOSFET channel mobility modification |
| CN101170066A (en) * | 2006-10-24 | 2008-04-30 | 联华电子股份有限公司 | Semiconductor component and its making method |
| JP2008203102A (en) * | 2007-02-20 | 2008-09-04 | Osaka Univ | Method for manufacturing cantilever beam and force sensor |
| CN102130058A (en) * | 2010-01-19 | 2011-07-20 | 中芯国际集成电路制造(上海)有限公司 | CMOS (Complementary Metal Oxide Semiconductor) transistor and manufacturing method thereof |
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- 2013-12-24 CN CN201310720622.7A patent/CN103745928B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1507071A (en) * | 2002-12-12 | 2004-06-23 | �Ҵ���˾ | Field effect transistor with stressed channel and producing method thereof |
| WO2004089811A2 (en) * | 2003-04-11 | 2004-10-21 | Paul Scherrer Institut | Method for manufacturing an electro-mechanical component and an electro-mechanical component, such as a strained si fin-fet |
| CN1790715A (en) * | 2004-12-15 | 2006-06-21 | 国际商业机器公司 | Structure and method to generate local mechanical gate stress for MOSFET channel mobility modification |
| CN101170066A (en) * | 2006-10-24 | 2008-04-30 | 联华电子股份有限公司 | Semiconductor component and its making method |
| JP2008203102A (en) * | 2007-02-20 | 2008-09-04 | Osaka Univ | Method for manufacturing cantilever beam and force sensor |
| CN102130058A (en) * | 2010-01-19 | 2011-07-20 | 中芯国际集成电路制造(上海)有限公司 | CMOS (Complementary Metal Oxide Semiconductor) transistor and manufacturing method thereof |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109166790A (en) * | 2018-07-28 | 2019-01-08 | 西安交通大学 | A method of utilizing perovskite oxide piezoelectric membrane on metal stresses layer removing graphene |
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