CN103744624A - System architecture for realizing selective upgrade of data cached in SSD (Solid State Disk) of storage system - Google Patents

System architecture for realizing selective upgrade of data cached in SSD (Solid State Disk) of storage system Download PDF

Info

Publication number
CN103744624A
CN103744624A CN201410011514.7A CN201410011514A CN103744624A CN 103744624 A CN103744624 A CN 103744624A CN 201410011514 A CN201410011514 A CN 201410011514A CN 103744624 A CN103744624 A CN 103744624A
Authority
CN
China
Prior art keywords
data
module
upgrading
data block
ssd
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201410011514.7A
Other languages
Chinese (zh)
Other versions
CN103744624B (en
Inventor
温源
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Inspur Electronic Information Industry Co Ltd
Original Assignee
Inspur Electronic Information Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Inspur Electronic Information Industry Co Ltd filed Critical Inspur Electronic Information Industry Co Ltd
Priority to CN201410011514.7A priority Critical patent/CN103744624B/en
Publication of CN103744624A publication Critical patent/CN103744624A/en
Application granted granted Critical
Publication of CN103744624B publication Critical patent/CN103744624B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Abstract

The invention discloses system architecture for realizing selective upgrade of data cached in an SSD (Solid State Disk) of a storage system. In the system architecture, a data selective upgrade algorithm is adopted, initially-hit data blocks are saved in a queue named candidate upgrade queue, the hitting times of hit blocks in each candidate upgrade queue are tracked, and hit data blocked are cached from an HDD (Hard Disk Drive) into an SSD cache when an upgrade limit is reached, thereby fulfilling the aims of delaying the cached data, reducing writing operation, and prolonging the service life of the SSD. By adopting the system architecture, selective upgrade of the data cached in the SSD can be ensured, data are cached efficiently, and the demand of a user on a high-performance storage system is met.

Description

A kind of system architecture that realizes the data cached selectivity upgrading of storage system SSD
Technical field
The present invention relates to a kind of system architecture that realizes the data selection upgrading of storage system SSD buffer memory, be generally used in storage system, aim to provide the system architecture of the data cached selectivity upgrading of a kind of SSD.
Technical background
Along with the progress of society, need data message to be processed more and more, data volume is explosive growth.This has brought problems to traditional storage system.Heritage storage system is generally used mechanical type hard disk (HDD), and the performance of heritage storage system has become bottleneck.Nearly 2 years, SSD was that solid storage hard disk starts to rise.On the one hand, SSD itself has the features such as quick random access, low power consuming, ultralight ultra-thin, less trouble (on-mechanical parts).On the other hand, due to technical development, it is little that SSD has solved capacity gradually, the slow-footed problem of sequential access.Currently marketed up-to-date SSD, single-deck capacity reaches several TB, and the SSD handling capacity of PCIE interface surpasses 1GB/s, and IOPS reaches hundreds of thousands/s.SSD performance surpasses traditional mechanical hard disk comprehensively, and the key indexs such as its access speed, response time significantly surpass traditional mechanical hard disk especially.
But because therefore the price of SSD will can meet the performance requirement of current data processing using SSD as buffer memory far away higher than HDD hard disk, can not improve storage system cost again.
SSD has some characteristics, and the one, SSD has age limit, and SSD has the problem of erasable number of times restriction, and it is once erasable that each write operation all can cause SSD to carry out, so the quantity of write operation can directly affect erasable number of times, thereby affects the life-span of SSD; The capacity of the 2nd, SSD is also far smaller than HDD hard disk, so SSD space is extremely precious.
Summary of the invention
The technical problem to be solved in the present invention is:
The data selection upgrading of SSD buffer memory is badly in need of solving two problems, and the one, solve SSD life problems, how to reduce the write operation to SSD, thereby extend the life-span of SSD; The 2nd, how effectively to utilize the space of SSD, guarantee the data of buffer memory most worthy.
The system architecture of upgrading by the data selection of this storage system SSD buffer memory, can realize the data cached dynamic update of SSD, significantly reduces the SSD amount of writing, increase and write hit rate, extend the life-span of SSD, efficiently utilize the storage space of SSD, meet the high performance demand of storage system.
The technical solution adopted in the present invention is:
A system architecture that realizes the data cached selectivity upgrading of storage system SSD, this system architecture is supported in different operating system, realizes the data cached selectivity upgrading of SSD.This system architecture adopts data selection upgrading algorithm, the data block of hitting is for the first time kept to a candidate by name upgrades in the queue of queue, utilize to follow the trail of the hit count that each candidate upgrades and hits piece in queue, when reaching upgrading limit value, just can by the data block of hitting from HDD hard disk cache to SSD buffer memory, thereby realize delay buffer data, reduce write operation, extend the target in SSD life-span;
This system comprises: 1) data query cache module; 2) candidate's upgrade data enquiry module; 3) candidate's upgrade data processing module; 4) upgrading limit value statistical module; 5) Data Migration module; 6) hit count adjusting module, wherein:
Whether module 1) data query cache module, be responsible for inquiry in data cached queue and exist to data block, if existed, and the position of direct return data piece in SSD buffer memory; If do not exist, return to zero;
Whether module 2) candidate's upgrade data enquiry module, be responsible for inquiry in candidate upgrades queue and exist to data block, if existed, returns to the hit count of given data block; If do not exist, return to zero;
Module 3) candidate's upgrade data processing module, the operation that responsible candidate upgrades given data block hit count increase and again joins the team;
Module 4) upgrading limit value statistical module, statistics upgrading limit value, first calculate the average hits of all data blocks of institute's buffer memory in data cached queue, computing formula is the number of hitting sum/data block of upgrading basic restrictions=data block, upgrading basic restrictions is a value dynamically changing, foundation as data upgrading, in addition, upgrading limit value has respectively an acquiescence bonus values for reading and writing, read acquiescence bonus values and be less than and write acquiescence bonus values, this is because SSD buffer memory is more suitable for as reading buffer memory.Final upgrading limit value can judge read-write situation, and its value is the summation of upgrading basic restrictions and read-write acquiescence bonus values, and the data block of only having hit count to be greater than this value just can be buffered to SSD buffer memory;
Module 5) Data Migration module, is responsible for data block to be copied to SSD buffer memory from HDD;
Module 6) hit count adjusting module, be responsible for the adjustment of the hit count of all data blocks of hitting, it is an independent thread, undertaken by user's fixed time, the time that generally selection business is few carries out, because the hit count of data block only can increase, therefore this module can reduce the upgrade hit count of data block in queue of data cached queue and candidate dynamically, minimizing value is the upgrade average hits of all data blocks of queue of candidate, data block hit count adjustment calculation formula is current hit count-minimizing value, if institute's result of calculation is less than or equal to 0, the hit count of this data block is adjusted into 1, guarantee the rationality of hit count.
Described framework data selection upgrading overall flow is as follows:
1, when there being read-write IO to arrive, calling module 1) inquire about data block that this read-write IO is corresponding whether in SSD buffer memory, if exist, the position of direct return data piece in SSD buffer memory; If do not exist, return to zero, illustrate that this data block likely needs upgrading, needs calling module 2);
2, module 2) can in candidate upgrades queue, inquire about and whether exist according to data block corresponding to read-write IO, meeting calling module 3 after poll-final) according to returning results, handle accordingly;
3, module 3) according to module 2) return results, if return to zero, this data block miss mistake is before described, this data block be joined to candidate and upgrade in queue, and hit count is designated as to 1; If return to non-zero, illustrate that this data block was hit, the hit count that rreturn value is this data block, and calling module 4) obtain upgrading limit value;
4, module 3) judge whether this upgrading of this data block, if the hit count of this data block is less than upgrading limit value, the hit count of this data block is added in the lump and again joined the team; If the hit count of this data block is more than or equal to upgrading limit value, the hit count of this data block is added to one, and calling module 5);
5, module 4) calculate upgrading basic restrictions now, and judge the type of this read-write IO, if upgrading basic restrictions and the summation that reads acquiescence bonus values are returned in read operation, and calling module 3); If write operation, returns to upgrading basic restrictions and writes the summation of giving tacit consent to bonus values, and calling module 3);
6, module 5) complete Data Migration, and this data block is deleted from candidate's queue of upgrading, be added in data cached queue.
According to the real-time condition of SSD buffer memory, dynamically adjust upgrading limit value, realize the data cached selectivity upgrading of SSD, thereby guarantee the data buffer storage of storage system hottest point, to SSD buffer memory, to avoid the waste in SSD space, utilize efficiently SSD spatial cache.
Beneficial effect of the present invention is:
Adopt system architecture of the present invention, can guarantee the selectivity upgrading that SSD is data cached, efficiently data cached, meet the demand of user to High Performance Cache and Memory System.Realize the data cached selectivity upgrading of SSD, according to the real-time condition of SSD buffer memory, dynamically adjust upgrading limit value, delay data and enter SSD buffer memory, significantly reduce the amount of writing of SSD, guarantee that the data in buffer memory are exactly the data of hottest point, extend the life-span of SSD, guarantee the efficient utilization of SSD spatial cache, the whole performance of storage system that improves.
Therefore adopt this system architecture, the data cached selectivity of storage system SSD that realizes that can be efficient, intelligent is upgraded.
Accompanying drawing explanation
Fig. 1 is data selection upgrading overall flow schematic diagram of the present invention;
Fig. 2 is candidate's upgrade data treatment scheme schematic diagram;
Fig. 3 is that hit count is adjusted schematic flow sheet.
Embodiment
With reference to the accompanying drawings, by embodiment, the present invention is further described:
Embodiment of the present invention is simple, only system module program of the present invention need to be installed in LINUX kernel.According to the present invention, SSD caching system can be realized data cached selectivity upgrading automatically, when storage system need to be upgraded when data cached, SSD caching system can intelligence carry out Data Migration operation, data are copied to SSD buffer memory from HDD, meet the data selection upgrade feature of SSD caching system.
A system architecture that realizes the data cached selectivity upgrading of storage system SSD, this system architecture is supported in different operating system, realizes the data cached selectivity upgrading of SSD.This system architecture adopts data selection upgrading algorithm, the data block of hitting is for the first time kept to a candidate by name upgrades in the queue of queue, utilize to follow the trail of the hit count that each candidate upgrades and hits piece in queue, when reaching upgrading limit value, just can by the data block of hitting from HDD hard disk cache to SSD buffer memory, thereby realize delay buffer data, reduce write operation, extend the target in SSD life-span;
This system comprises: 1) data query cache module; 2) candidate's upgrade data enquiry module; 3) candidate's upgrade data processing module; 4) upgrading limit value statistical module; 5) Data Migration module; 6) hit count adjusting module, wherein:
Whether module 1) data query cache module, be responsible for inquiry in data cached queue and exist to data block, if existed, and the position of direct return data piece in SSD buffer memory; If do not exist, return to zero;
Whether module 2) candidate's upgrade data enquiry module, be responsible for inquiry in candidate upgrades queue and exist to data block, if existed, returns to the hit count of given data block; If do not exist, return to zero;
Module 3) candidate's upgrade data processing module, the operation that responsible candidate upgrades given data block hit count increase and again joins the team;
Module 4) upgrading limit value statistical module, statistics upgrading limit value, first calculate the average hits of all data blocks of institute's buffer memory in data cached queue, computing formula is the number of hitting sum/data block of upgrading basic restrictions=data block, upgrading basic restrictions is a value dynamically changing, foundation as data upgrading, in addition, upgrading limit value has respectively an acquiescence bonus values for reading and writing, read acquiescence bonus values and be less than and write acquiescence bonus values, this is because SSD buffer memory is more suitable for as reading buffer memory.Final upgrading limit value can judge read-write situation, and its value is the summation of upgrading basic restrictions and read-write acquiescence bonus values, and the data block of only having hit count to be greater than this value just can be buffered to SSD buffer memory;
Module 5) Data Migration module, is responsible for data block to be copied to SSD buffer memory from HDD;
Module 6) hit count adjusting module, be responsible for the adjustment of the hit count of all data blocks of hitting, it is an independent thread, undertaken by user's fixed time, the time that generally selection business is few carries out, because the hit count of data block only can increase, therefore this module can reduce the upgrade hit count of data block in queue of data cached queue and candidate dynamically, minimizing value is the upgrade average hits of all data blocks of queue of candidate, data block hit count adjustment calculation formula is current hit count-minimizing value, if institute's result of calculation is less than or equal to 0, the hit count of this data block is adjusted into 1, guarantee the rationality of hit count.
As shown in Figure 1, described framework data selection upgrading overall flow is as follows:
1, when there being read-write IO to arrive, calling module 1) inquire about data block that this read-write IO is corresponding whether in SSD buffer memory, if exist, the position of direct return data piece in SSD buffer memory; If do not exist, return to zero, illustrate that this data block likely needs upgrading, needs calling module 2);
2, module 2) can in candidate upgrades queue, inquire about and whether exist according to data block corresponding to read-write IO, meeting calling module 3 after poll-final) according to returning results, handle accordingly;
3, module 3) according to module 2) return results, if return to zero, this data block miss mistake is before described, this data block be joined to candidate and upgrade in queue, and hit count is designated as to 1; If return to non-zero, illustrate that this data block was hit, the hit count that rreturn value is this data block, and calling module 4) obtain upgrading limit value;
4, module 3) judge whether this upgrading of this data block, if the hit count of this data block is less than upgrading limit value, the hit count of this data block is added in the lump and again joined the team; If the hit count of this data block is more than or equal to upgrading limit value, the hit count of this data block is added to one, and calling module 5);
5, module 4) calculate upgrading basic restrictions now, and judge the type of this read-write IO, if upgrading basic restrictions and the summation that reads acquiescence bonus values are returned in read operation, and calling module 3); If write operation, returns to upgrading basic restrictions and writes the summation of giving tacit consent to bonus values, and calling module 3);
6, module 5) complete Data Migration, and this data block is deleted from candidate's queue of upgrading, be added in data cached queue.
According to the real-time condition of SSD buffer memory, dynamically adjust upgrading limit value, realize the data cached selectivity upgrading of SSD, thereby guarantee the data buffer storage of storage system hottest point, to SSD buffer memory, to avoid the waste in SSD space, utilize efficiently SSD spatial cache.
As shown in Figure 2, candidate's upgrade data treatment scheme is:
1, module 3) according to module 2) return results, if return to zero, this data block miss mistake is before described, this data block be joined to candidate and upgrade in queue, and hit count is designated as to 1;
If 2 return to non-zero, illustrate that this data block was hit, the hit count that rreturn value is this data block, and calling module 4) obtain upgrading limit value;
3, relatively hits and upgrading limit value, if hits are less than or equal to upgrading limit value, the hits of saying this data block add in the lump joins the team again;
If 4 hits are greater than upgrading limit value, the hits of this data block are added to one, and calling data transferring module 5).
As shown in Figure 3, hit count adjustment flow process is:
1, module 6) obtain the upgrade average hits of all data blocks of queue of candidate;
2, take out node in data cached queue in turn, reduce these node hits and again join the team;
3, judge whether that all adjustment is complete, as no, repeat previous step;
4, as complete in whole adjustment, take out candidate's node in queue of upgrading in turn;
5, decision node hit count deducts on average to hit whether be less than 1, in this way, makes this node hit count equal 1 and also again joins the team;
6,, as no, reduce these node hits and again join the team;
7, judge whether that all adjustment is complete, as no, return to step 4;
8, as complete in whole adjustment, flow process completes.

Claims (3)

1. realize the system architecture that the data cached selectivity of storage system SSD is upgraded for one kind, it is characterized in that: this system architecture adopts data selection upgrading algorithm, the data block of hitting is for the first time kept to a candidate by name upgrades in the queue of queue, utilize to follow the trail of the hit count that each candidate upgrades and hits piece in queue, when reaching upgrading limit value, just can by the data block of hitting from HDD hard disk cache to SSD buffer memory, thereby realize delay buffer data, reduce write operation, extend the target in SSD life-span;
This system comprises: 1) data query cache module; 2) candidate's upgrade data enquiry module; 3) candidate's upgrade data processing module; 4) upgrading limit value statistical module; 5) Data Migration module; 6) hit count adjusting module, wherein:
Whether module 1) data query cache module, be responsible for inquiry in data cached queue and exist to data block, if existed, and the position of direct return data piece in SSD buffer memory; If do not exist, return to zero;
Whether module 2) candidate's upgrade data enquiry module, be responsible for inquiry in candidate upgrades queue and exist to data block, if existed, returns to the hit count of given data block; If do not exist, return to zero;
Module 3) candidate's upgrade data processing module, the operation that responsible candidate upgrades given data block hit count increase and again joins the team;
Module 4) upgrading limit value statistical module, statistics upgrading limit value, first calculate the average hits of all data blocks of institute's buffer memory in data cached queue, computing formula is the number of hitting sum/data block of upgrading basic restrictions=data block, upgrading basic restrictions is a value dynamically changing, foundation as data upgrading, in addition, upgrading limit value has respectively an acquiescence bonus values for reading and writing, reading acquiescence bonus values is less than and writes acquiescence bonus values, final upgrading limit value can judge read-write situation, its value is the summation of upgrading basic restrictions and read-write acquiescence bonus values, the data block of only having hit count to be greater than this value just can be buffered to SSD buffer memory,
Module 5) Data Migration module, is responsible for data block to be copied to SSD buffer memory from HDD;
Module 6) hit count adjusting module, be responsible for the adjustment of the hit count of all data blocks of hitting, it is an independent thread, undertaken by user's fixed time, data block hit count adjustment calculation formula is current hit count-minimizing value, if institute's result of calculation is less than or equal to 0, the hit count of this data block is adjusted into 1, guarantee the rationality of hit count.
2. a kind of system architecture that realizes the data cached selectivity upgrading of storage system SSD according to claim 1, is characterized in that, described framework data selection upgrading overall flow is as follows:
A, when there being read-write IO to arrive, calling module 1) inquire about data block that this read-write IO is corresponding whether in SSD buffer memory, if exist, the position of direct return data piece in SSD buffer memory; If do not exist, return to zero, illustrate that this data block likely needs upgrading, needs calling module 2);
B, module 2) can in candidate upgrades queue, inquire about and whether exist according to data block corresponding to read-write IO, meeting calling module 3 after poll-final) according to returning results, handle accordingly;
C, module 3) according to module 2) return results, if return to zero, this data block miss mistake is before described, this data block be joined to candidate and upgrade in queue, and hit count is designated as to 1; If return to non-zero, illustrate that this data block was hit, the hit count that rreturn value is this data block, and calling module 4) obtain upgrading limit value;
D, module 3) judge whether this upgrading of this data block, if the hit count of this data block is less than upgrading limit value, the hit count of this data block is added in the lump and again joined the team; If the hit count of this data block is more than or equal to upgrading limit value, the hit count of this data block is added to one, and calling module 5);
E, module 4) calculate upgrading basic restrictions now, and judge the type of this read-write IO, if upgrading basic restrictions and the summation that reads acquiescence bonus values are returned in read operation, and calling module 3); If write operation, returns to upgrading basic restrictions and writes the summation of giving tacit consent to bonus values, and calling module 3);
F, module 5) complete Data Migration, and this data block is deleted from candidate's queue of upgrading, be added in data cached queue.
3. a kind of system architecture that realizes the data cached selectivity upgrading of storage system SSD according to claim 1, is characterized in that: according to the real-time condition of SSD buffer memory, dynamically adjust upgrading limit value, realize the data cached selectivity upgrading of SSD.
CN201410011514.7A 2014-01-10 2014-01-10 A kind of system architecture for realizing the data cached selectivity upgradings of storage system SSD Active CN103744624B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201410011514.7A CN103744624B (en) 2014-01-10 2014-01-10 A kind of system architecture for realizing the data cached selectivity upgradings of storage system SSD

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201410011514.7A CN103744624B (en) 2014-01-10 2014-01-10 A kind of system architecture for realizing the data cached selectivity upgradings of storage system SSD

Publications (2)

Publication Number Publication Date
CN103744624A true CN103744624A (en) 2014-04-23
CN103744624B CN103744624B (en) 2017-09-22

Family

ID=50501645

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201410011514.7A Active CN103744624B (en) 2014-01-10 2014-01-10 A kind of system architecture for realizing the data cached selectivity upgradings of storage system SSD

Country Status (1)

Country Link
CN (1) CN103744624B (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112106018A (en) * 2018-05-09 2020-12-18 美光科技公司 Memory buffer management and bypass
US11355169B2 (en) 2018-05-09 2022-06-07 Micron Technology, Inc. Indicating latency associated with a memory request in a system
US11604606B2 (en) 2018-05-09 2023-03-14 Micron Technology, Inc. Prefetch signaling in memory system or subsystem
US11822477B2 (en) 2018-05-09 2023-11-21 Micron Technology, Inc. Prefetch management for memory

Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102203749A (en) * 2010-12-31 2011-09-28 华为技术有限公司 Writing method and device of solid state driver under multi-level cache
KR20110115759A (en) * 2010-04-16 2011-10-24 성균관대학교산학협력단 Buffer cache managing method using ssd(solid state disk) extension buffer and apparatus for using ssd(solid state disk) as extension buffer
CN102760101A (en) * 2012-05-22 2012-10-31 中国科学院计算技术研究所 SSD-based (Solid State Disk) cache management method and system
CN102779017A (en) * 2012-06-29 2012-11-14 华中科技大学 Control method of data caching area in solid state disc
CN102799535A (en) * 2012-06-29 2012-11-28 记忆科技(深圳)有限公司 Solid-state disk and data processing method thereof
CN102831088A (en) * 2012-07-27 2012-12-19 国家超级计算深圳中心(深圳云计算中心) Data migration method and device based on mixing memory
US20130145094A1 (en) * 2010-05-13 2013-06-06 Takehiko Kurashige Information Processing Apparatus and Driver
CN103186350A (en) * 2011-12-31 2013-07-03 北京快网科技有限公司 Hybrid storage system and hot spot data block migration method
CN103257935A (en) * 2013-04-19 2013-08-21 华中科技大学 Cache management method and application thereof

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20110115759A (en) * 2010-04-16 2011-10-24 성균관대학교산학협력단 Buffer cache managing method using ssd(solid state disk) extension buffer and apparatus for using ssd(solid state disk) as extension buffer
US20130145094A1 (en) * 2010-05-13 2013-06-06 Takehiko Kurashige Information Processing Apparatus and Driver
CN102203749A (en) * 2010-12-31 2011-09-28 华为技术有限公司 Writing method and device of solid state driver under multi-level cache
CN103186350A (en) * 2011-12-31 2013-07-03 北京快网科技有限公司 Hybrid storage system and hot spot data block migration method
CN102760101A (en) * 2012-05-22 2012-10-31 中国科学院计算技术研究所 SSD-based (Solid State Disk) cache management method and system
CN102779017A (en) * 2012-06-29 2012-11-14 华中科技大学 Control method of data caching area in solid state disc
CN102799535A (en) * 2012-06-29 2012-11-28 记忆科技(深圳)有限公司 Solid-state disk and data processing method thereof
CN102831088A (en) * 2012-07-27 2012-12-19 国家超级计算深圳中心(深圳云计算中心) Data migration method and device based on mixing memory
CN103257935A (en) * 2013-04-19 2013-08-21 华中科技大学 Cache management method and application thereof

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
SAI HUANG 等: "Improving Flash-based Disk Cache with Lazy Adaptive Replacement", 《MASS STORAGE SYSTEMS AND TECHNOLOGIES(MSST),2013 IEEE 29TH SYMPOSIUM ON》 *
李东阳 等: "基于固态硬盘的云存储分布式缓存策略", 《计算机工程》 *

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112106018A (en) * 2018-05-09 2020-12-18 美光科技公司 Memory buffer management and bypass
US11340830B2 (en) 2018-05-09 2022-05-24 Micron Technology, Inc. Memory buffer management and bypass
US11355169B2 (en) 2018-05-09 2022-06-07 Micron Technology, Inc. Indicating latency associated with a memory request in a system
US11604606B2 (en) 2018-05-09 2023-03-14 Micron Technology, Inc. Prefetch signaling in memory system or subsystem
US11822477B2 (en) 2018-05-09 2023-11-21 Micron Technology, Inc. Prefetch management for memory
US11915788B2 (en) 2018-05-09 2024-02-27 Micron Technology, Inc. Indication in memory system or sub-system of latency associated with performing an access command

Also Published As

Publication number Publication date
CN103744624B (en) 2017-09-22

Similar Documents

Publication Publication Date Title
US10204039B2 (en) Host controlled hybrid storage device
CN103136121B (en) Cache management method for solid-state disc
CN103777905B (en) Software-defined fusion storage method for solid-state disc
US9477607B2 (en) Adaptive record caching for solid state disks
CN104834607A (en) Method for improving distributed cache hit rate and reducing solid state disk wear
CN104536701A (en) Realizing method and system for NVME protocol multi-command queues
CN105138292A (en) Disk data reading method
CN103744624A (en) System architecture for realizing selective upgrade of data cached in SSD (Solid State Disk) of storage system
US20190050340A1 (en) Invalidating track format information for tracks in cache
CN103678166A (en) Method and system for using solid-state disk as cache of computer
CN103744623A (en) Method for realizing intelligent degradation of data cached in SSD (Solid State Disk) of storage system
US11188256B2 (en) Enhanced read-ahead capability for storage devices
US10489296B2 (en) Quality of cache management in a computer
US20190189167A1 (en) Utilizing write stream attributes in storage write commands
US9152599B2 (en) Managing cache memories
US20190050339A1 (en) Invalidating track format information for tracks demoted from cache
US10740029B2 (en) Expandable buffer for memory transactions
CN102521161B (en) Data caching method, device and server
US10733118B2 (en) Computer system, communication device, and storage control method with DMA transfer of data
CN102123318A (en) IO acceleration method of IPTV application
US20120066456A1 (en) Direct memory access cache prefetching
US11449428B2 (en) Enhanced read-ahead capability for storage devices
CN100428200C (en) Method for implementing on-chip command cache
US11687460B2 (en) Network cache injection for coherent GPUs
KR20230055978A (en) System, device for ordered access of data in memory with block modification characteristic, and operation method thereof

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant