CN103744405A - Two-axle planar motion control card oriented to full-automatic surface mount system and two-axle planar motion control method - Google Patents
Two-axle planar motion control card oriented to full-automatic surface mount system and two-axle planar motion control method Download PDFInfo
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- CN103744405A CN103744405A CN201410028594.7A CN201410028594A CN103744405A CN 103744405 A CN103744405 A CN 103744405A CN 201410028594 A CN201410028594 A CN 201410028594A CN 103744405 A CN103744405 A CN 103744405A
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Abstract
The invention discloses a two-axle planar motion control card oriented to a full-automatic surface mount system and a two-axle planar motion control method, relates to the field of industrial motion control and stereometry, and aims to solve the problems of low transmission speed, low reliability and low accuracy in the conventional full-automatic surface mount system as well as the problem that the motion state of a controlled device cannot be reflected in real time by means of the conventional planar motion control method. The two-axle planar motion control card comprises a bus interface circuit, a CPLD (Complex Programmable Logic Device) module, a DSP (Digital Signal Processor) module, an SRAM (Static Random Access Memory) cache module and a lower layer interface circuit, wherein the SRAM cache module is used for supporting high-capacity data storage. In an internal software program of the DSP module, a synchronization algorithm and a speed planning algorithm are adopted. By adopting the synchronization algorithm, high synchronism of two coaxial motors is realized, and errors of the two-axle planar motion control card are up to a micron order. By adopting the speed planning algorithm, the motors run smoothly, act quickly, and are more stable and high in reliability when not running. The two-axle planar motion control card is suitable for surface mount machines, insertion-mount machines and similar products.
Description
Technical field
The present invention relates to industrial motion control and plane survey field.
Background technology
It is the device that the components and parts that adopt surface mounting technology to complete pcb board card mount task that full-automatic surface mounts system, merged the advanced technology in multiple fields such as automatic control, Machine Design manufacture, image recognition, digital signal processing, be the organic whole of various piece, motion algorithm control, signal are processed with the performance index such as the speed of transmission etc., reliability and had higher requirement.Therefore, automatically mount system its nucleus movement control card is especially had to strict requirement.At present, the Design of Motion Control Board that cannot take into account high speed and high reliability is the subject matter that prior art exists, and is also one of important bottleneck of the domestic surface mounting technology development of restriction.And the existing plane motion control method that mounts system towards full-automatic surface, can not reflect in real time the motion state of controlled device, that is to say can not be according to the motion state of controlled device, adjusts in real time the instruction that host computer sends, thereby makes controlled device complete corresponding action.
Summary of the invention
The present invention is the problem that control card transmission speed is slow, reliability is low and precision is low that mounts system in order to solve existing full-automatic surface, is also the problem that can not reflect in real time controlled device motion state in order to solve existing plane motion control method.The two axial plane motion control cards and the two axial plane motion control methods that towards full-automatic surface, mount system are now provided.
The two axial plane motion control cards that mount system towards full-automatic surface, it comprises: bus interface circuit, CPLD module, DSP module, sram cache module and lower floor's interface circuit;
The address signal input end of bus interface circuit connects CPLD module's address output terminal; The data-signal input/output terminal of bus interface circuit connects the data-signal I/O of CPLD module;
The RAM access control signal output part of sram cache module connects the RAM access control signal input part of CPLD module; The RAM data-signal input/output terminal of sram cache module connects the RAM data-signal input/output terminal of CPLD module; The SRAM address signal input end of sram cache module connects the SRAM address signal output terminal of CPLD module; The SRAM data-signal input end of sram cache module connects the SRAM data-signal output terminal of CPLD module;
The peripheral hardware enable signal output terminal of CPLD module connects the peripheral hardware enable signal input end of DSP module; The processor control signal input end of CPLD module connects the processor control signal output terminal of DSP module; The code-disc feedback signal input end of CPLD module connects the code-disc feedback signal output terminal of lower floor's interface circuit; The switch state signal input end of CPLD module connects the switch state signal output terminal of lower floor's interface circuit; The pwm signal input end of CPLD module connects the pwm signal input end of lower floor's interface circuit; The pulse signal input terminal of the pulse signal output end DSP module of CPLD module; The pulse signal output end of DSP module connects the pulse signal input terminal of lower floor's interface circuit.
CPLD module comprises RAM access control module, address decoder, exchanges data latch, pulse command generation module, peripheral access control module, code-disc feed back input module, on off state load module, PWM load module and pulse output module;
RAM access control module is for exporting RAM access control signal to sram cache module;
Described address decoder is for resolving the address signal of bus interface circuit; Described address decoder is also for exporting the address signal of reception respectively to RAM access control module and peripheral access control module;
Described exchanges data latch is for the data-signal of storage bus interfaces circuit, also for storing the dsp control signal of DSP module output, the code-disc feedback signal of code-disc feed back input module output, the switch state signal of on off state load module output, the pwm signal of PWM load module; Also for exporting pulse command to pulse command maker;
Described pulse command maker is used for exporting pulse command to pulse output module;
Peripheral access control module is for exporting the peripheral hardware address signal of address decoder output to DSP module;
Described code-disc feed back input module is for reading the code-disc feedback signal of lower floor's interface circuit output;
Described on off state load module is for reading the switch state signal of lower floor's interface circuit output;
Described PWM load module is for reading the pwm signal of lower floor's interface circuit output;
Described pulse output module is used for exporting pulse command to DSP module, then by DSP module, this pulse signal is sent to lower floor's interface circuit.
The two axial plane motion control methods that mount system towards full-automatic surface, the method concrete steps are as follows:
Step 1, host computer transmit control signal to CPLD module by bus interface circuit, the exchanges data latch of described CPLD module receives this control signal, and this control signal is sent to sram cache module, sram cache module is sent to DSP module by described control signal; DSP module starts timer interrupts or external interrupt, if timer interrupts, performs step two; If external interrupt, performs step three;
The present invention is applicable to surface stick-mounting machine, sticking and inserting machine and similar products thereof.
The two axial plane motion control cards that mount system towards full-automatic surface of the present invention, comprise bus interface circuit, CPLD module, DSP module, sram cache module and lower floor's interface circuit, sram cache module, be used for supporting jumbo data storage, can realize DMA transfer function, greatly improved the speed of large-scale data transmission, compared existing full-automatic surface and mount the control card of system, transmission speed has improved more than 50%.The software embedding in DSP inside modules has adopted synchronized algorithm and speed planning algorithm, and synchronized algorithm can make two coaxial motors reach high level of synchronization, makes error of the present invention reach micron order, and precision has improved more than 30%; Speed planning algorithm can make motor movement smoothly smooth, and motor action speed is fast, and motor is more stable when stopping, and reliability is high, compares existing full-automatic surface and mount the control card of system, and reliability has improved more than 40%.Two axial plane motion control methods of the present invention, have reflected the motion state of controlled device in real time, according to the motion state of controlled device, adjust in real time the instruction that host computer sends.
Accompanying drawing explanation
Fig. 1 is the electrical principle schematic diagram that mounts two axial plane motion control cards of system towards full-automatic surface;
Fig. 2 is the electrical principle schematic diagram that mounts the DSP module of two axial plane motion control cards of system towards full-automatic surface;
Fig. 3 is the course of work process flow diagram of DSP module;
Fig. 4 is the interrupt procedure process flow diagram in the course of work of DSP module.
Embodiment
Embodiment one: illustrate present embodiment with reference to Fig. 1, two axial plane motion control cards of the system that mounts towards full-automatic surface described in present embodiment, it comprises: bus interface circuit 1, CPLD module 2, DSP module 3, sram cache module 4 and lower floor's interface circuit 5;
The address signal input end of bus interface circuit 1 connects CPLD module 2 address output ends; The data-signal input/output terminal of bus interface circuit 1 connects the data-signal I/O of CPLD module 2;
The RAM access control signal output part of sram cache module 4 connects the RAM access control signal input part of CPLD module 2; The RAM data-signal input/output terminal of sram cache module 4 connects the RAM data-signal input/output terminal of CPLD module 2; The SRAM address signal input end of sram cache module 4 connects the SRAM address signal output terminal of CPLD module 2; The SRAM data-signal input end of sram cache module 4 connects the SRAM data-signal output terminal of CPLD module 2;
The peripheral hardware enable signal output terminal of CPLD module 2 connects the peripheral hardware enable signal input end of DSP module 3; The processor control signal input end of CPLD module 2 connects the processor control signal output terminal of DSP module 3; The code-disc feedback signal input end of CPLD module 2 connects the code-disc feedback signal output terminal of lower floor's interface circuit 5; The switch state signal input end of CPLD module 2 connects the switch state signal output terminal of lower floor's interface circuit 5; The pwm signal input end of CPLD module 2 connects the pwm signal input end of lower floor's interface circuit 5; The pulse signal output end of CPLD module 2 connects the pulse signal input terminal of DSP module 3; The pulse signal output end of DSP module 3 connects the pulse signal input terminal of lower floor's interface circuit 5.
Principle explanation: host computer carries out exchanges data by bus interface circuit and CPLD module.
The director data that CPLD module sends host computer is delivered to pulse command maker; Pulse command maker generates the pulse signal for drive motor motion, and by pulse output module, this pulse signal is sent to DSP module 3; DSP module 3 completes the data transmission between motor by lower floor's interface circuit again, makes motor complete corresponding action according to the steering order of host computer.
DSP module is the control core that mounts two axial plane motion control cards of system towards full-automatic surface, its kernel program mounts the duty of System planes motion for controlling full-automatic surface, make mounting head to realize corresponding function according to predetermined flow process, and provide the prompting under various error situations to report to the police and wrong treatment mechanism.
Sram cache module is the important component part that mounts two axial plane motion control cards of system towards full-automatic surface, except completing basic data storage function, also provide the caching function of data transmission, the data transmission between balance host computer and DSP module; In addition, sram cache module also can realize DMA data transmission, greatly improves data transmission efficiency.
Embodiment two: see figures.1.and.2 and illustrate present embodiment, present embodiment is that two axial plane motion control cards of the system that mounts towards full-automatic surface described in embodiment one are described further, in present embodiment,
RAM access control module 2-1 is for exporting RAM access control signal to sram cache module 4;
Described address decoder 2-2 is for resolving the address signal of bus interface circuit 1; Described address decoder 2-2 is also for exporting the address signal of reception respectively to RAM access control module 2-1 and peripheral access control module 2-5;
Described exchanges data latch 2-3 is for the data-signal of storage bus interfaces circuit 1, also for storing the dsp control signal that DSP module 3 exports, the code-disc feedback signal of code-disc feed back input module 2-6 output, the switch state signal of on off state load module 2-7 output, the pwm signal of PWM load module 2-8; Also for exporting pulse command to pulse command maker 2-4;
Described pulse command maker 2-4 is used for exporting pulse command to pulse output module 2-9;
Peripheral access control module 2-5 is for exporting the peripheral hardware address signal of address decoder 2-2 output to DSP module 3;
Described code-disc feed back input module 2-6 is for reading the code-disc feedback signal that lower floor's interface circuit 5 is exported;
Described on off state load module 2-7 is for reading the switch state signal that lower floor's interface circuit 5 is exported;
Described PWM load module 2-8 is for reading the pwm signal that lower floor's interface circuit 5 is exported;
Described pulse output module 2-9 is used for exporting pulse command to DSP module 3, then by DSP module 3, this pulse signal is sent to lower floor's interface circuit 5.
Principle: the address information that address decoder sends host computer is carried out decoding processing, makes the corresponding function module on board and peripheral hardware in selected state.Exchanges data latch has been used for the exchanges data between host computer and DSP, and sends feedback information to host computer.Exchanges data latch module can scheduling control signal direction of transfer, complete the exchanges data between host computer and bus interface circuit DSP module.The time sequential routine of peripheral access control module for having realized peripheral access.RAM access control module has been used for the time sequential routine of RAM chip.Impulse generator, according to the order of host computer, is made speed planning by planning algorithm, generates the pulse signal of controlling motor, outputs to motor driver.Code-disc feedback signal, pwm signal and switch state signal are all read by host computer by exchanges data latch.
Embodiment three: two axial plane motion control methods of the system that mounts towards full-automatic surface described in this enforcement, the method concrete steps are as follows:
Step 1, host computer transmit control signal to CPLD module 2 by bus interface circuit 1, the exchanges data latch 2-3 of described CPLD module 2 receives this control signal, and this control signal is sent to sram cache module 4, sram cache module 4 is sent to DSP module 3 by described control signal; DSP module 3 starts timer interrupts or external interrupt, if timer interrupts, performs step two; If external interrupt, performs step three;
Embodiment four: illustrate present embodiment with reference to Fig. 3, present embodiment is the course of work for DSP module is described, the step of its course of work is as follows;
Step 1, initialization system resource, execution step three;
Step 6, house dog is set;
Step 7, etc. external interrupt to be triggered.
Embodiment five: illustrate present embodiment with reference to Fig. 4, present embodiment is the interrupt procedure in the course of work for DSP module is described, described interrupt procedure step is as follows:
Steps A 1, enter interrupt procedure, judge whether it is that timer interrupts, if so, perform step A2, if not, perform step A10;
Steps A 2, read magnetic railings ruler state;
Steps A 3, the DSP self check information that whether breaks down, and DSP judges whether host computer is finished to the steering order of motor, the information if DSP self check is broken down, and no matter whether host computer is finished to the steering order of motor, all performs step A4;
The information if DSP self check is not broken down, and host computer is finished to the steering order of motor, performs step A5; The information if DSP self check is not broken down, host computer is not finished to the steering order of motor, continues to wait for, until host computer is finished to the steering order of motor, performs step A5;
Steps A 4, malfunction set, then perform step A6;
Steps A 5, motor complete the relevant action of the steering order of host computer to motor;
In steps A 6, DSP, motor mark position malfunction, then performs step A7;
Steps A 7, stop motor, then perform step A8;
Steps A 8, detect and report and then perform step A9 by failure message;
Steps A 9, clear house dog, finish;
Steps A 10, judge whether it is external interrupt, if so, perform step A11, if not, perform step A20;
Steps A 11, reading command;
Steps A 12, judge whether it is position command, if so, executing location instruction, if not, performs step 13;
Steps A 13, judge whether it is position reset instruction, if so, motor is back to initial point, if not, performs step A14;
Steps A 14, judge whether it is register reset instruction, if so, empty and all registers that resets, if not, perform step A15;
Steps A 15, judge whether it is sensor clear command, if so, empty sensor values, if not, perform step A16;
Steps A 16, judge whether it is emergent stopping instruction, if so, stop motor operation, if not, perform step A17;
Steps A 17, judge whether it is RAM read write command, if so, opening RAM is all to enable, if not, perform step A18,
Steps A 18, read-write register parameter instruction while judging whether, if so, read-write register parameter, if not, finishes.
Principle: in the course of work of DSP module, first carry out initialization operation and open system break, then interrupt service routine work.By interrupt service routine, complete the control of host computer to motor.
The interrupt procedure of DSP module comprises that external interrupt and timer interrupt.Enter after interrupt service routine, by interrupt identification, judge that entering timer interrupt service routine still enters external interrupt service routine.
If interrupt identification indicates that what enter is timer interrupt service routine, show that now host computer is not sent into new programmed instruction, DSP module, according to the current command, determines that DSP module continues the action that will carry out.
If interrupt identification indicates that what enter is external interrupt service routine, shows that host computer has issued new programmed instruction.According to different instructions, DSP module arranges corresponding register, and starts corresponding peripheral hardware, carries out operation accordingly.
The two axial plane motion control cards that mount system towards full-automatic surface of the present invention and two axial plane motion control methods can complete RAM buffer memory read-write, generate Electric Machine Control pulse command and obtain the feedback of status of peripheral hardware.All instructions of the plane motion of surface mount system are all to complete on the basis of these elementary instructions.
The read-write of RAM buffer memory.RAM buffer memory is for the relevant control data of interim storage, for the communication between host computer and device port provides at a high speed transmission mode reliably.
Generate Electric Machine Control pulse command.The major function of motion control board is exactly Electric Machine Control, can generate corresponding gating pulse sequence according to host computer instruction, and frequency and the phase place of Negotiation speed planning algorithm paired pulses are controlled, realize the level and smooth control of motor, on the basis of high speed, high-precision motion, reduce the impact to physical construction.
Obtain the feedback of status of peripheral hardware.Motion control card can obtain the feed back input of code-disc signal, pwm signal, switch state signal by peripheral hardware signaling interface, make host computer can obtain in real time the running status of paster apparatus.
Claims (3)
1. the two axial plane motion control cards that mount system towards full-automatic surface, is characterized in that, it comprises: bus interface circuit (1), CPLD module (2), DSP module (3), sram cache module (4) and lower floor's interface circuit (5);
The address signal input end of bus interface circuit (1) connects CPLD module (2) address output end; The data-signal input/output terminal of bus interface circuit (1) connects the data-signal I/O of CPLD module (2);
The RAM access control signal output part of sram cache module (4) connects the RAM access control signal input part of CPLD module (2); The SRAM data-signal input/output terminal of sram cache module (4) connects the SRAM data-signal input/output terminal of CPLD module (2); The SRAM address signal input end of sram cache module (4) connects the SRAM address signal output terminal of CPLD module (2); The SRAM data-signal input end of sram cache module (4) connects the SRAM data-signal output terminal of CPLD module (2);
The peripheral hardware enable signal output terminal of CPLD module (2) connects the peripheral hardware enable signal input end of DSP module (3); The processor control signal input end of CPLD module (2) connects the processor control signal output terminal of DSP module (3); The code-disc feedback signal input end of CPLD module (2) connects the code-disc feedback signal output terminal of lower floor's interface circuit (5); The switch state signal input end of CPLD module (2) connects the switch state signal output terminal of lower floor's interface circuit (5); The pwm signal input end of CPLD module (2) connects the pwm signal input end of lower floor's interface circuit (5); The pulse signal output end of CPLD module (2) connects the pulse signal input terminal of DSP module (3); The pulse signal output end of DSP module (3) connects the pulse signal input terminal of lower floor's interface circuit (5).
2. the two axial plane motion control cards that mount system towards full-automatic surface according to claim 1, it is characterized in that, CPLD module (2) comprises RAM access control module (2-1), address decoder (2-2), exchanges data latch (2-3), pulse command generation module (2-4), peripheral access control module (2-5), code-disc feed back input module (2-6), on off state load module (2-7), PWM load module (2-8) and pulse output module (2-9);
RAM access control module (2-1) is for exporting RAM access control signal to sram cache module (4);
Described address decoder (2-2) is for resolving the address signal of bus interface circuit (1); Described address decoder (2-2) is also for exporting the address signal of reception respectively to RAM access control module (2-1) and peripheral access control module (2-5);
Described exchanges data latch (2-3) is for the data-signal of storage bus interfaces circuit (1), also for storing the dsp control signal of DSP module (3) output, the code-disc feedback signal of code-disc feed back input module (2-6) output, the switch state signal of on off state load module (2-7) output, the pwm signal of PWM load module (2-8); Also for exporting pulse command to pulse command maker (2-4);
Described pulse command maker (2-4) is for exporting pulse command to pulse output module (2-9);
Peripheral access control module (2-5) is for exporting the peripheral hardware address signal of address decoder (2-2) output to DSP module (3);
Described code-disc feed back input module (2-6) is for reading the code-disc feedback signal of lower floor's interface circuit (5) output;
Described on off state load module (2-7) is for reading the switch state signal of lower floor's interface circuit (5) output;
Described PWM load module (2-8) is for reading the pwm signal of lower floor's interface circuit (5) output;
Described pulse output module (2-9) is for pulse command being exported to DSP module (3), then by DSP module (3), this pulse signal is sent to lower floor's interface circuit (5).
3. the two axial plane motion control methods that mount system towards full-automatic surface, is characterized in that, the method concrete steps are as follows:
Step 1, host computer transmit control signal to CPLD module (2) by bus interface circuit (1), the exchanges data latch (2-3) of described CPLD module (2) receives this control signal, and this control signal is sent to sram cache module (4), sram cache module (4) is sent to DSP module (3) by described control signal; DSP module (3) starts timer interrupts or external interrupt, if timer interrupts, performs step two; If external interrupt, performs step three;
Step 2, timer IE, described in sending, DSP module (3) controls signal to the exchanges data latch (2-3) of CPLD module (2), exchanges data latch (2-3) transmitted signal is to pulse command maker (2-4), described pulse command maker (2-4) output pulse signal is to pulse output module (2-9), pulse output module (2-9) output pulse signal is to DSP module (3), by DSP module (3), this pulse signal is sent to lower floor's interface circuit (5) again, lower floor's interface circuit (5) is isolated described output of pulse signal to photoelectricity, then by motor driver drive motor, move,
Step 3, external interrupt starts, show that host computer transmits control signal to CPLD module (2) by bus interface circuit (1) again, the exchanges data latch (2-3) of described CPLD module (2) receives this control signal, and this control signal is sent to sram cache module (4), sram cache module (4) is sent to DSP module (3) by described control signal, the control signal that DSP module (3) resends host computer is sent to the exchanges data latch (2-3) of CPLD module (2), exchanges data latch (2-3) transmitted signal is to pulse command maker (2-4), described pulse command maker (2-4) output pulse signal is to pulse output module (2-9), pulse output module (2-9) output pulse signal is to DSP module (3), by DSP module (3), this pulse signal is sent to lower floor's interface circuit (5) again, lower floor's interface circuit (5) is isolated described output of pulse signal to photoelectricity, then by motor driver drive motor, move,
Step 4, lower floor's interface circuit (5) are sent to CPLD module (2) by the motion state of motor, CPLD module (2) is sent to code-disc feedback signal, switch state signal and pwm signal respectively exchanges data latch (2-3) by code-disc feed back input module (2-6), on off state load module (2-7) and PWM load module (2-8), and exchanges data latch (2-3) deposits described code-disc feedback signal, switch state signal and pwm signal in sram cache module; Exchanges data latch (2-3) is sent to host computer by bus interface circuit by code-disc feedback signal, switch state signal and pwm signal simultaneously, for upper machine-readable getting;
Step 5, host computer judge the motion state of motor, the new power transmission machine steering order of laying equal stress on, repeating step one according to the code-disc feedback signal, switch state signal and the pwm signal that read.
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