CN103744333A - Multi-model high-speed data collecting system and multi-mode high-speed data collecting method applied to high-speed surface mounting device - Google Patents
Multi-model high-speed data collecting system and multi-mode high-speed data collecting method applied to high-speed surface mounting device Download PDFInfo
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Abstract
A multi-model high-speed data collecting system and a multi-mode high-speed data collecting method applied to a high-speed surface mounting device relate to the field of industrial motion control and plane surveying and mapping, aim to solve the problems of high cost and incapability of considering real-time property and large-scale data transmission of a data collecting system of the existing high-speed surface mounting device and also aim to solve the problem of slow collecting speed and single work mode of the existing data collecting method. The method comprises the steps of when an upper computer sends a collecting command, performing address analysis by a CPLD, determining the colleting mode and external equipment to be operated, sending the collecting command to a microcontroller, simultaneously triggering to disconnect the exterior of the microcontroller, starting a disconnection service program by the microcontroller, and determining to start an upper computer main control mode, a lower computer synchronous mode or a large-scale data asynchronous mode according to different control commands, wherein a level conversion chip is used for realizing the connection with the upper computer. The multi-model high-speed data collecting system and the multi-mode high-speed data collecting method applied to the high-speed surface mounting device are suitable for multiple upper computer-controlled motion control systems, two dimension plotters and other high-speed high-precision motion control systems.
Description
Technical field
The present invention relates to industrial motion control and plane survey field.
Background technology
High speed surface mounting device is the complex apparatus that integrates the multinomial technology such as motion control, image acquisition, and the realization of control, collection etc. is needed to higher performance, and the most frequently used system bus is pci bus.The scheme that PCI equipment development adopts is at present pci interface chip, or the IP kernel bank that adopts Quartus II to provide.The former has taken valuable board space resource, and is unfavorable for the single-chip integrated of embedded system; The latter will take the resources such as a large amount of logical blocks, and user logic quantity is restricted, and module is fixing customizable hardly.
The data acquisition system (DAS) mode of operation adopting is at present single, be difficult to multiple collection environment suitable mode of operation is provided, be difficult to take into account real-time and large-scale data transmission, and the Core Feature board cost of current data acquisition system (DAS) is generally higher, and while upgrading upgrading, also need to re-start hardware design, upgrading debugging difficulty is large, and cost is high, has limited the application and development of data acquisition system (DAS).And the existing collecting method picking rate that is applied to high speed surface mounting device is slow, and mode of operation is single, can not meet the requirement of high speed surface mounting device to picking rate and multi-mode working pattern.
Summary of the invention
The present invention is that the data acquisition system (DAS) cost in order to solve existing high speed surface mounting device is high and can not take into account the problem of real-time and large-scale data transmission, is also in order to solve the problem that existing collecting method picking rate is slow and mode of operation is single.The multi-mode high-speed data acquistion system and the multi-mode High Speed Data Collection Method that are applied to high speed surface mounting device are now provided.
Be applied to the multi-mode high-speed data acquistion system of high speed surface mounting device, it comprises CPLD module, microcontroller, SRAM storer and level transferring chip;
The voltage signal input/output terminal of described CPLD module connects the input/output terminal of level transferring chip;
Described SRAM storer is used to CPLD module and microcontroller storage and provides SRAM address and SRAM data;
The microcontroller data-signal input/output terminal of described microcontroller connects the microcontroller data-signal input/output terminal of CPLD module; The microcontroller address signal input end of described microcontroller connects the microcontroller address signal output terminal of CPLD module; The interrupt line signal output part of described microcontroller connects the interrupt line signal input part of CPLD module.
Described CPLD module comprises: PCI protocol analysis module, address decoder, data register and data processing module;
Described PCI protocol analysis module is for depositing address signal in address register, also, for realizing the mutual transmission of data-signal of PCI protocol analysis module and data register, can also be used for receiving the interrupt line signal of microcontroller;
Described address decoder to receive address signal decoding after export SRAM address to SRAM memory stores, export microcontroller address to microcontroller simultaneously;
Described data register is for realizing and the transmission of the data-signal of data processing module, and exports this data-signal to data processing module, waits for that SRAM memory signals is mutual in data processing module;
Described data processing module is used for the mutual transmission of the microcontroller data-signal of realizing data processing module and microcontroller; Can also be used for exporting control line signal to microcontroller.
Described microcontroller adopts DSP or chip microcontroller.
The multi-mode High Speed Data Collection Method that is applied to high speed surface mounting device, the concrete steps of the method are as follows:
Host computer sends acquisition instructions by pci system bus, outputs voltage signal to the PCI protocol analysis module of CPLD module after level transferring chip conversion;
PCI protocol analysis module is resolved described acquisition instructions, and send data-signal to data register, then data register sends acquisition instructions data-signal to data processing module, data processing module is resolved described acquisition instructions data-signal, and the peripheral hardware of definite drainage pattern and operation, then to microprocessor, send microprocessor data signal;
Microprocessor starts interrupt service routine, and determines and enable host computer master mode, slave computer synchronous mode or large-scale data asynchronous mode;
If host computer master mode, the data that microcontroller is collected are sent to CPLD module; The data that CPLD module collects microcontroller by data processing module are deposited to data register, the data in host computer read data register;
If slave computer synchronous mode, microcontroller starts timer to interrupt, and after timer has interrupted, the data that microcontroller is collected are delivered to CPLD module; The data that the data processing module of CPLD module collects microcontroller are deposited to data register, the data in host computer read data register;
If large-scale data asynchronous mode, microcontroller starts timer to interrupt, and after timer has interrupted, the data that microcontroller is collected are delivered to SRAM storer; Microcontroller sends interrupt line signal to CPLD module, and CPLD module is sent to host computer by PCI protocol analysis module by interrupt line signal, and host computer starts interrupt service routine and reads the data in SRAM storer.
The present invention is applicable to other high-speed, high precision kinetic control systems such as the kinetic control system of multiple PC control and two-dimensions plotting apparatus.
Multi-mode high-speed data acquistion system and the multi-mode High Speed Data Collection Method that is applied to high speed surface mounting device of the present invention, comprise CPLD module, microcontroller, SRAM storer and level transferring chip, the protocol analysis of multi-mode high-speed data acquistion system can either be relatively independent, also can be combined with board function logic height, by the Software for Design of microcontroller, the present invention can provide multiple-working mode, met the data acquisition system (DAS) of high speed surface mounting device to hardware real-time, the requirement of software real-time and large-scale data transmitting.CPLD module, microcontroller, SRAM storer and the level transferring chip of employing of the present invention, cost is lower, compare existing high speed surface mounting device data acquisition system (DAS) cost more than 20%.And multi-mode High Speed Data Collection Method of the present invention, picking rate is fast, compares existing collecting method, and picking rate has improved more than 40%, and multiple-working mode is provided.
Accompanying drawing explanation
Fig. 1 is the electrical principle schematic diagram that is applied to the multi-mode high-speed data acquistion system of high speed surface mounting device;
Fig. 2 is the electrical principle schematic diagram that is applied to the CPLD module of the multi-mode high-speed data acquistion system of high speed surface mounting device;
Fig. 3 is the microcontroller course of work process flow diagram described in embodiment five;
Fig. 4 is the external interrupt process flow diagram of register interrupts in the microcontroller course of work described in embodiment six;
Fig. 5 is that the timer of register interrupts in the microcontroller course of work described in embodiment seven interrupts process flow diagram.
Embodiment
Embodiment one: illustrate present embodiment with reference to Fig. 1, the multi-mode high-speed data acquistion system that is applied to high speed surface mounting device described in present embodiment, it comprises CPLD module 1, microcontroller 2, SRAM storer 3 and level transferring chip 4;
The voltage signal input/output terminal of described CPLD module 1 connects the input/output terminal of level transferring chip 4;
Described SRAM storer 3 is used to CPLD module 1 and microcontroller 2 to store and provide SRAM address and SRAM data;
The microcontroller data-signal input/output terminal of described microcontroller 2 connects the microcontroller data-signal input/output terminal of CPLD module 1; The microcontroller address signal input end of described microcontroller 2 connects the microcontroller address signal output terminal of CPLD module 1; The interrupt line signal output part of described microcontroller 2 connects the interrupt line signal input part of CPLD module 1.
Embodiment two: see figures.1.and.2 and illustrate present embodiment, present embodiment is that the multi-mode high-speed data acquistion system that is applied to high speed surface mounting device described in embodiment one is described further, in present embodiment,
Described CPLD module 1 comprises: PCI protocol analysis module 1-1, address decoder 1-2, data register 1-3 and data processing module 1-4;
Described PCI protocol analysis module 1-1 is for depositing address signal in address register 1-2, also, for realizing the mutual transmission of data-signal of PCI protocol analysis module 1-1 and data register 1-3, can also be used for receiving the interrupt line signal of microcontroller 2;
Described address decoder 1-2 exports SRAM address to SRAM storer 3 and stores after to the address signal decoding receiving, and exports microcontroller address to microcontroller 2 simultaneously;
Described data register 1-3 is for realizing and the transmission of the data-signal of data processing module 1-4, and exports this data-signal to data processing module 1-4, waits for that SRAM memory signals is mutual in data processing module 1-4;
Described data processing module 1-4 is used for the mutual transmission of the microcontroller data-signal of realizing data processing module 1-4 and microcontroller 2; Can also be used for exporting control line signal to microcontroller 2.
PCI protocol analysis module is the pci interface module based on verilog HDL, compared with the PCI module providing with the IP kernel bank of quartus II, number of logic cells and pin number have greatly been saved, for the realization of other function logics in sheet provides valuable resource space, and can realize the degree of depth customization for functions of the equipments, according to device requirement, increase or delete corresponding function.
Embodiment three: present embodiment is that the multi-mode high-speed data acquistion system that is applied to high speed surface mounting device described in embodiment one is described further, in present embodiment,
Embodiment four: the multi-mode High Speed Data Collection Method that is applied to high speed surface mounting device described in present embodiment, the concrete steps of the method are as follows:
Host computer sends acquisition instructions by pci system bus, outputs voltage signal to the PCI protocol analysis module 1-1 of CPLD module after level transferring chip conversion;
PCI protocol analysis module 1-1 resolves described acquisition instructions, and send data-signal to data register 1-3, then data register 1-3 sends acquisition instructions data-signal to data processing module 1-4, data processing module 1-4 resolves described acquisition instructions data-signal, and the peripheral hardware of definite drainage pattern and operation, then to microprocessor 2, send microprocessor data signal;
If host computer master mode, the data that microcontroller 2 is collected are sent to CPLD module 1; The data that CPLD module 1 collects microcontroller by data processing module 1-4 are deposited to data register 1-3, the data in host computer read data register;
If slave computer synchronous mode, microcontroller 2 starts timer to interrupt, and after timer has interrupted, the data that microcontroller 2 is collected are delivered to CPLD module; The data that the data processing module of CPLD module collects microcontroller are deposited to data register, the data in host computer read data register;
If large-scale data asynchronous mode, microcontroller 2 starts timer to interrupt, and after timer has interrupted, the data that microcontroller 2 is collected are delivered to SRAM storer; Microcontroller 2 sends interrupt line signal to CPLD module, and CPLD module is sent to host computer by PCI protocol analysis module by interrupt line signal, and host computer starts interrupt service routine and reads the data in SRAM storer.
After host computer reads data, the data of slave computer synchronous mode or the data of large-scale data asynchronous mode of host computer master mode, host computer is deposited described three kinds of data to local data register.
Embodiment five: illustrate present embodiment with reference to Fig. 3, present embodiment is that the course of work step for microcontroller 2 is described is as follows:
Step B1, initialization GPIO, time manager and house dog;
Step B2, initialization RAM module, the register of initialization CPLD inside;
Step B3, microcontroller register interrupts is set, comprises that timer interrupts and external interrupt;
Step B4, house dog is set, then performs step B5;
Step B5, etc. external interrupt to be triggered.
Embodiment six: illustrate present embodiment with reference to Fig. 3 and Fig. 4, present embodiment is the external interrupt process of register interrupts in the course of work for microcontroller 2 is described, this external interrupt process is as follows:
Steps A 1, enter external interrupt;
Steps A 3, parsing master port address;
Steps A 4, open master port and enable;
Steps A 5, read master port data;
Steps A 6, close master port;
Steps A 7, microcontroller is delivered to master port data to the data register of CPLD, trigger interrupt line signal simultaneously, and finish;
Steps A 8, judge whether to enter slave computer Timing Synchronization pattern, if so, perform step A9, if not, perform step 14;
Steps A 9, parsing synchronous port address;
Steps A 10, set model sign;
Steps A 11, open timer interrupt, and start counting;
Steps A 12, judge whether times of collection, if so, performed step A13, if not, continued counting, until complete times of collection, continued execution step A19;
Steps A 13, timeing closing device also finish;
Steps A 14, judge whether to enter large data asynchronous mode, if so, perform step A15, if not, perform step A19;
Steps A 15, parsing asynchronous port address;
Steps A 16, set model sign;
Steps A 17, open timer interrupt, start counting;
Steps A 18, judge whether times of collection, if so, performed step A19, if not, continued counting, until complete times of collection, continued execution step A19;
Steps A 19, timeing closing device also finish.
Embodiment seven: illustrate present embodiment with reference to Fig. 3, Fig. 4 and Fig. 5, present embodiment is the timer interrupt procedure of register interrupts in the course of work for microcontroller 2 is described, this timer interrupt procedure is also the course of work that in the external interrupt process described in embodiment five, the timer in steps A 11 and steps A 17 interrupts.
The course of work that timer described in steps A 11 and steps A 17 interrupts is as follows:
Step 1, enter timer interrupt,
Step 3, synchronous port enable;
Step 5, close synchronous port and enable;
Step 6, triggering PCI interrupt line signal, and finish;
Whether step 7, judgment model sign are large data asynchronous mode, if so, perform step eight, if not, finish;
Step 8, asynchronous port enable;
Step 9, read asynchronous port data;
Step 10, close asynchronous port and enable;
Step 11, triggering PCI interrupt line signal, and finish.
If host computer master mode, microcontroller 2 is sent to CPLD module by the data of host computer master mode; CPLD module is deposited the data of host computer master mode to data register by data processing module, the data of the host computer master mode in host computer read data register;
If slave computer synchronous mode, microcontroller 2 starts timer to interrupt, and after timer has interrupted, microcontroller 2 is delivered to CPLD module by the data of slave computer synchronous mode; The data processing module of CPLD module deposits the data of slave computer synchronous mode to data register, the data of the slave computer synchronous mode in host computer read data register;
If large-scale data asynchronous mode, microcontroller 2 starts timer to interrupt, and after timer has interrupted, microcontroller 2 is delivered to SRAM storer by the data of slave computer synchronous mode; Microcontroller 2 sends interrupt line signal to CPLD module, and CPLD module is sent to host computer by PCI protocol analysis module by interrupt line signal, and host computer starts interrupt service routine and reads the data in SRAM storer.
Be applied to the course of work of the multi-mode high-speed data acquistion system of high speed surface mounting device: when host computer sends acquisition instructions, the function logic of CPLD carries out address resolution, determine drainage pattern and the peripheral hardware that will operate, acquisition instructions is issued to microcontroller, the external interrupt that simultaneously triggers microcontroller, microcontroller is enabled interrupt service routine.According to different steering orders, determine and enable host computer master mode, slave computer synchronous mode or large-scale data asynchronous mode.Under host computer master mode, host computer initiatively requires slave computer once to gather, and slave computer is accessed corresponding peripheral port according to address, and the data that collect are sent into data register, and triggering pci bus interruption, host computer starts interrupt service routine reading out data.In slave computer synchronous mode and large-scale data asynchronous mode, the external interrupt service routine of microcontroller all needs opening timing device, in timer interrupt service routine, according to control code, judgement is slave computer synchronous mode or large-scale data asynchronous mode, slave computer synchronous mode all needs that data are sent into data register at every turn and triggers PCI to interrupt, and large-scale data asynchronous mode only needs to deposit data in buffer at every turn.Data acquisition system (DAS) of the present invention can realize multimode data collection and multi-mode High Speed Data Collection Method, support three kinds of mode of operations, respectively host computer master mode, slave computer Timing Synchronization pattern and large-scale data asynchronous mode, different acquisition conditions can be adapted to, synchronous Timing Data Acquisition and the image data acquiring of single data acquisition, slave computer of host computer master control can be realized respectively.Slave computer refers to microcontroller.
Host computer master mode is applicable to the disposable data acquisition based on software requirement.Under this pattern, by host computer, initiatively initiate data acquisition command, slave computer carries out data sampling one time to the peripheral hardware of choosing, and sampled result is sent to the data register of CPLD module, the content of host computer read data register, deposits the data that collect to local data base.
Slave computer Timing Synchronization pattern is applicable to the more much higher secondary data collection of requirement of real-time.Under this pattern, host computer is assigned after acquisition instructions to slave computer, slave computer enters drainage pattern, start timer, data are carried out sending data to data processing module and the data register of CPLD module after timing sampling, and notify host computer by the interrupt line of pci bus, host computer starts PCI interrupt service routine, by PCI protocol analysis module, the data in read data register, deposit data to local data base.
Large-scale data asynchronous mode is applicable to large-scale data fast transport and host computer procedure does not have the occasion of specific (special) requirements to the real-time of data.As the data transmission of the images such as camera, video equipment.Under this pattern, host computer is assigned after acquisition instructions to slave computer, and process is in suspended state, and slave computer enters drainage pattern, and data are carried out, after timing sampling, data are deposited to the storer to SRAM; After collection finishes, by interrupt line, notify host computer; Host computer starts interrupt service routine, reads the content in SRAM storer, deposits to local data base.Under extensive asynchronous data transfer pattern, transmission speed can reach 132MB/s, and transmission data accuracy reaches more than 99.9%.What the image processing section of surface mount system adopted is exactly large-scale data asynchronous mode.
Claims (4)
1. the multi-mode high-speed data acquistion system that is applied to high speed surface mounting device, is characterized in that, it comprises CPLD module (1), microcontroller (2), SRAM storer (3) and level transferring chip (4);
The voltage signal input/output terminal of described CPLD module (1) connects the input/output terminal of level transferring chip (4);
Described SRAM storer (3) is used to CPLD module (1) and microcontroller (2) to store and provide SRAM address and SRAM data;
The microcontroller data-signal input/output terminal of described microcontroller (2) connects the microcontroller data-signal input/output terminal of CPLD module (1); The microcontroller address signal input end of described microcontroller (2) connects the microcontroller address signal output terminal of CPLD module (1); The interrupt line signal output part of described microcontroller (2) connects the interrupt line signal input part of CPLD module (1).
2. the multi-mode high-speed data acquistion system that is applied to high speed surface mounting device according to claim 1, it is characterized in that, described CPLD module (1) comprising: PCI protocol analysis module (1-1), address decoder (1-2), data register (1-3) and data processing module (1-4);
Described PCI protocol analysis module (1-1) is for depositing address signal in address register (1-2), also, for realizing the mutual transmission of data-signal of PCI protocol analysis module (1-1) and data register (1-3), can also be used for receiving the interrupt line signal of microcontroller (2);
Described address decoder (1-2) is exported SRAM address to SRAM storer (3) storage after to the address signal decoding receiving, and exports microcontroller address to microcontroller (2) simultaneously;
Described data register (1-3) is the transmission with the data-signal of data processing module (1-4) for realization, and exports this data-signal to data processing module (1-4), waits for that SRAM memory signals is mutual in data processing module (1-4);
Described data processing module (1-4) is for realizing the mutual transmission of microcontroller data-signal of data processing module (1-4) and microcontroller (2); Can also be used for exporting control line signal to microcontroller (2).
3. the multi-mode high-speed data acquistion system that is applied to high speed surface mounting device according to claim 1, is characterized in that, described microcontroller (2) adopts DSP or chip microcontroller.
4. the multi-mode High Speed Data Collection Method that is applied to high speed surface mounting device, is characterized in that, the concrete steps of the method are as follows:
Host computer sends acquisition instructions by pci system bus, outputs voltage signal to the PCI protocol analysis module (1-1) of CPLD module after level transferring chip conversion;
PCI protocol analysis module (1-1) is resolved described acquisition instructions, and send data-signal to data register (1-3), then data register (1-3) sends acquisition instructions data-signal to data processing module (1-4), data processing module (1-4) is resolved described acquisition instructions data-signal, and the peripheral hardware of definite drainage pattern and operation, then to microprocessor (2), send microprocessor data signal;
Microprocessor (2) starts interrupt service routine, and determines and enable host computer master mode, slave computer synchronous mode or large-scale data asynchronous mode;
If host computer master mode, the data that microcontroller (2) is collected are sent to CPLD module (1); The data that CPLD module (1) collects microcontroller by data processing module (1-4) are deposited to data register (1-3), the data in host computer read data register;
If slave computer synchronous mode, microcontroller (2) starts timer to interrupt, and after timer has interrupted, the data that microcontroller (2) is collected are delivered to CPLD module; The data that the data processing module of CPLD module collects microcontroller are deposited to data register, the data in host computer read data register;
If large-scale data asynchronous mode, microcontroller (2) starts timer to interrupt, and after timer has interrupted, the data that microcontroller (2) is collected are delivered to SRAM storer; Microcontroller (2) sends interrupt line signal to CPLD module, and CPLD module is sent to host computer by PCI protocol analysis module by interrupt line signal, and host computer starts interrupt service routine and reads the data in SRAM storer.
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