CN103729519A - Method for selecting and processing coverage solution logic function containing items based on minterm - Google Patents
Method for selecting and processing coverage solution logic function containing items based on minterm Download PDFInfo
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- CN103729519A CN103729519A CN201410018856.1A CN201410018856A CN103729519A CN 103729519 A CN103729519 A CN 103729519A CN 201410018856 A CN201410018856 A CN 201410018856A CN 103729519 A CN103729519 A CN 103729519A
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Abstract
The invention discloses a method for selecting and processing coverage solution logic function containing items based on the minterm. The method is suitable for complete listing functions and incomplete listing functions. By searching for truth values 4 in the largest number step by step, a matrix coverage is set up so that the optimal selection algorithm can be set up, all the truth values 4 of the matrix coverage are solved in an output matrix so that the coverage of a conduction set can be found, and therefore the containing items with the coverage property are generated. The method is simple and convenient to implement, and efficiency and accuracy of logic function optimization are improved.
Description
Technical field
The present invention relates to a kind of disposal route of choosing of the covering solution logic function implication based on minterm.
Background technology
Logic optimization is the basis of digital circuit Automated Design, digital circuit computer-aided design (CAD) (Computer Aided Design, CAD) development of system has far-reaching influence to the numerous areas of computer science, more and more urgent to the demand of high-speed, high integration, high complexity and high reliability circuit.In the world, the problem of logic optimization is the study hotspot of computer science and association area.Logic optimization is the comprehensive gordian technique of integrated circuit (IC) logic, asks the problem of the optimum logic optimization based on a certain optimization aim to be proved to be a NP difficult problem.There is at present several different methods can realize logical function optimization, the general method of seeking near-optimal that adopts.The gordian technique of integrated circuit (IC) logic optimization is: 1. make in logic optimization result different term “and”s (AND) expression formula sum minimum, reduce AND gate number; 2. reduce the sum of contained variable in term “and” expression formula, even if AND gate circuit input end number is minimum; 3. seek the formalization representation method of logic optimization.
Summary of the invention
The object of the present invention is to provide a kind of disposal route of choosing of easy, an effective covering solution logic function implication based on minterm.
Technical solution of the present invention is:
A covering solution logic function implication based on minterm choose disposal route, it is characterized in that: comprise the following steps:
(1) cover and solve.Calculating output matrix covers, and solves the implication item of its output covering matrix (or Matrix cover) of matrix occurring with minterm form.The implication item of the conducting collection covering of all true value 4 is found out in requirement.
(1) the implication item selection rule covering
By progressively searching for maximum matrix line numbers that the true value 4 of maximum numbers covers for forming optimum coverage criteria.
(2) the implication item choosing method covering
The first step, chooses in minterm formal matrices and comprises the maximum row of true value 4 numbers, sets it as the major part that produces the implication item covering.Second step, at most it covers covering vector that line numbers the are maximum implication item as the covering of newly choosing to choose on this basis the number that comprises true value 4, and the difference of the number of identical true value 4 contains need be chosen respectively.The 3rd step, covers (covered) mark to the row of its covering of implication item of newly choosing, and carries out false delete flag and change 3, the four steps into covering 4 in row, repeats the first step, until do not comprise 4 in minterm formal matrices.
(2) containing item solves.According to the implication item set of choosing, calculate each minterm superset that item comprises that contains.Minterm (date expression of the input variable) set of the row that minterm superset covers for implication item.(3) expansion: the minterm superset that each implication item is comprised is carried out adjacency merging, is extended to 2, the minimum item that contains of formation by 0 and 1.
The present invention forms Matrix cover with structure optimum optimization Algorithms of Selecting by progressively searching for the true value 4 of maximum numbers, covers all true value 4 to find out the covering of conducting collection, and then produce the implication item that possesses Covering property by solution matrix in output matrix.The inventive method is easy, has improved efficiency and accuracy that logical function is optimized.
Accompanying drawing explanation
Below in conjunction with drawings and Examples, the invention will be further described.
Fig. 1 is the covering schematic diagram of output matrix.
Fig. 2 contains a minterm superset schematic diagram of output covering vector m1.
Fig. 3 contains a minterm superset schematic diagram of output covering vector m2.
Fig. 4 contains a minterm superset schematic diagram of output covering vector m3.
Fig. 5 contains a minterm superset schematic diagram of output covering vector m4.
Fig. 6 is the expansion schematic diagram of m1.
Fig. 7 is a minimum schematic diagram that contains.
Embodiment
A covering solution logic function implication based on minterm choose disposal route, comprise the following steps:
(1) cover and solve.Calculating output matrix covers, and solves the implication item of its output covering matrix (or Matrix cover) of matrix occurring with minterm form.The implication item of the conducting collection covering of all true value 4 is found out in requirement.
(1) the implication item selection rule covering
By progressively searching for maximum matrix line numbers that the true value 4 of maximum numbers covers for forming optimum coverage criteria.
(2) the implication item choosing method covering
The first step, chooses in minterm formal matrices and comprises the maximum row of true value 4 numbers, sets it as the major part that produces the implication item covering.Second step, at most it covers covering vector that line numbers the are maximum implication item as the covering of newly choosing to choose on this basis the number that comprises true value 4, and the difference of the number of identical true value 4 contains need be chosen respectively.The 3rd step, covers (covered) mark to the row of its covering of implication item of newly choosing, and carries out false delete flag and change 3, the four steps into covering 4 in row, repeats the first step, until do not comprise 4 in minterm formal matrices.
(2) containing item solves.According to the implication item set of choosing, calculate each minterm superset that item comprises that contains.Minterm (date expression of the input variable) set of the row that minterm superset covers for implication item.(3) expansion: the minterm superset that each implication item is comprised is carried out adjacency merging, is extended to 2, the minimum item that contains of formation by 0 and 1.
Eample Analysis:
Example 1: provide a Multiinputoutput logical function product term expression matrix as follows.
According to minterm formal matrices, express requirement and can change into following form:
Example 2: provide a Multiinputoutput logical function minterm expression matrix as follows.
First by solution matrix in output matrix, cover all true value 4 to find out the covering of conducting collection, and then produce the implication item that possesses Covering property.The mulching method of output matrix as shown in Figure 1.
Covering implication chooses:
The corresponding output matrix of this function comprises 5 output variables, 7 continuous items.In output matrix, choose m1, m2, m3, m4 for containing for output covers vector, m1-m4 has covered the true value 4 of all outputs.As m1 has covered vector the 4th, the 5th output variable 2., 5. and 7., m2 has covered vector second, third output variable 6. and 7., m3 covered vector 1. and 5. first, the 3rd output variable, m4 covered vector first output variable 2. and 3..
Containing item solves:
When covering, contain an output and cover after vector generation, according to output, cover vector and find out corresponding implication, form minterm superset.
M1 item has covered vector 2., 5., 7. (see Fig. 2).In input matrix, contain a candidate item of exporting covering vector m1 and must comprise minterm superset 2., 5., 7., containing a minterm superset for output covering vector is shown in Fig. 2.
The minterm superset that contains an output covering vector m2, m3, m4 is respectively as shown in Fig. 3, Fig. 4, Fig. 5.
Expansion: each minterm superset of comprising of item that contains is carried out to adjacency merging, and be extended to 2 by non-isomorphic 0 and 1, form minimum contain.
The minterm superset spreading result of output covering vector m1 as shown in Figure 6.
In like manner, we can calculate the spreading result of m2-m4.Merge the spreading result of m1-m4, draw the minimum implication result of logical function optimization as shown in Figure 7.
Remarks explanation:
The explanation of the digital 0-5 occurring in set or matrix
0-input variable is mended (instead) code and is occurred, 1-input variable source code appearance, and this input variable of 2-do not occur,
In 3-output function, product term does not occur, in 4-output function, product term occurs, in 5-output function, product term is outlier.
1, the matrix representation of logical function
If F is a multiple output function, contain n input variable and m output variable, P is given product term set.If p
kthe vector form of ∈ P is
The representation of importation, i.e. the benefit of 0 expression variable, 1 represents former variable, 2 represent that variablees do not occur in product term.Output is defined as follows: if product term p
kdo not belong to function f
t,
be 3, otherwise
be 4.If product term p
kfor outlier,
be 5.Two parts are following formula altogether:
Claims (1)
- Covering solution logic function implication based on minterm choose a disposal route, it is characterized in that: comprise the following steps:(1) cover and solve: calculate output matrix and cover, solve the implication item that covers matrix or Matrix cover with its output of matrix of minterm form appearance, the implication item that requires the conducting collection of finding out all true value 4 to cover;(1) the implication item selection rule coveringBy progressively searching for maximum matrix line numbers that the true value 4 of maximum numbers covers for forming optimum coverage criteria;(2) the implication item choosing method coveringThe first step, chooses in minterm formal matrices and comprises the maximum row of true value 4 numbers, sets it as the major part that produces the implication item covering; Second step, at most it covers covering vector that line numbers the are maximum implication item as the covering of newly choosing to choose on this basis the number that comprises true value 4, and the difference of the number of identical true value 4 contains need be chosen respectively; The 3rd step, carries out overlay marks to the row of its covering of implication item of newly choosing, and carries out false delete flag and change 3 into covering 4 in row; The 4th step, repeats the first step, until do not comprise 4 in minterm formal matrices;(2) containing item solves: according to the implication item set of choosing, calculate each minterm superset that item comprises that contains; The minterm set of the row that minterm superset covers for implication item;(3) expansion: the minterm superset that each implication item is comprised is carried out adjacency merging, is extended to 2, the minimum item that contains of formation by 0 and 1.
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---|---|---|---|---|
CN105447241A (en) * | 2015-11-16 | 2016-03-30 | 浙江万里学院 | ESOP minimization method for logic function |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5748490A (en) * | 1995-10-26 | 1998-05-05 | Motorola, Inc. | Low power logic minimization for electrical circuits |
CN103034758A (en) * | 2012-12-07 | 2013-04-10 | 南通大学 | Logic optimizing and parallel processing method of integrated circuit |
-
2014
- 2014-01-16 CN CN201410018856.1A patent/CN103729519A/en active Pending
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5748490A (en) * | 1995-10-26 | 1998-05-05 | Motorola, Inc. | Low power logic minimization for electrical circuits |
CN103034758A (en) * | 2012-12-07 | 2013-04-10 | 南通大学 | Logic optimizing and parallel processing method of integrated circuit |
Non-Patent Citations (2)
Title |
---|
JIANLIN QIU等: "A New Logic Optimization Algorithm of Multi-valued Logic Function Based on Two-valued Logic", 《APPLIED MECHANICS AND MATERIALS》, 31 October 2011 (2011-10-31) * |
LI FEN等: "Research on Technology of Mini-terms Optimization for Logic Function", 《WORLD CONGRESS ON SOFTWARE ENGINEERING》, vol. 2, 21 May 2009 (2009-05-21) * |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN105447241A (en) * | 2015-11-16 | 2016-03-30 | 浙江万里学院 | ESOP minimization method for logic function |
CN105447241B (en) * | 2015-11-16 | 2018-03-09 | 浙江万里学院 | A kind of ESOP of logical function of Digital Logical Circuits minimizes method |
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