CN103729016A - 61588 time keeping method based on FPGA frequency modulation strategy - Google Patents

Abstract

The invention discloses a 61588 time keeping method based on an FPGA frequency modulation strategy, and belongs to the technical field of communication. The 61588 time keeping method is characterized in that on the premise that a crystal oscillator of a clock source and a crystal oscillator of a synchronized device are not influenced by external conditions, a central processing unit enables time errors calculated in every time of synchronization to serve as compensation values to fine adjust the number of ticks of an FPGA clock counter in real time, and the time keeping aim of the synchronized device under the condition that the 61588 synchronous clock source loses contact can be effectively achieved. Under the condition that the 61588 synchronous clock source loses contact, the reliability, the sensitivity and the stability of an intelligent device with the 61588 time keeping method can completely meet the requirements of an intelligent substation.

Description

A kind of 61588 punctual methods based on FPGA frequency modulation strategy

Technical field

The present invention relates to a kind of 61588 punctual methods of measuring based on FPGA frequency modulation, belong to communication technique field.

Background technology

Present stage, the intelligent substation of employing based on IEC 61850 standards put on account schedule, along with the intelligent substation based on IEC 61850 standard construction puts into operation successively, electronic type voltage, current transformer and intelligent electronic device will be widely used in intelligent substation.Traditional time synchronization protocol, if SNTP is because synchronization accuracy is limited, cannot meet the synchronisation requirement of present stage Electric Power Automation Equipment.For solving intelligent substation Network Synchronization problem, the 1588 accurate timing protocol translation IEC61588 standards that IEC formulates IEEE, this standard is also adopted and is designated as the accurate clock synchronization protocol > > of < < for networking measurement and control system by China.

Electric system is punctual to be of great significance real-time analysis electric network state and guarantee safe operation of electric network tool.Can meet various device and the demand of system to time synchronized in the temporary transient lost contact situation of synchronous device, guarantee the consistance of real-time data acquisition, improve the accuracy of phasor and the dynamic monitoring of merit angle, line fault range finding etc., thereby strengthening power system fault analysis and the stable ability of controlling, is one of key point of 1588 synchro systems.

Summary of the invention

The object of the present invention is to provide a kind of 61588 punctual methods based on frequency modulation strategy.

The present invention is a kind of 61588 punctual methods of measuring based on FPGA frequency modulation, it is characterized in that, the method includes the steps of:

In the intelligent substation of employing IEC61588 standard, the time error that smart machine central processing unit CPU calculates according to clock source, by the each synchronometer of the crystal oscillator of synchronous device is worth by way of compensation, finely tune the tick number (a tick number is once counted in the every vibration of crystal oscillator) of FPGA clock counter, in synchronous clock source lost contact situation, adopt the mode of FPGA frequency modulation to make up this Crystal Oscillator Errors, comprise following steps:

(1) initialization

11) according to smart machine acquiescence, initialization break period is interrupted number N for whole second by synchronous device _s;

12) initialization 10ms offset registers tick counts N ₁₀be 0;

13) initialization 100ms offset registers tick counts N ₁₀₀be 0;

14) initialization 1000ms offset registers tick counts N ₁₀₀₀be 0;

15) initialization need compensate and nanosecond count T _bbe 0;

(2) in the each interruption section of smart machine CPU, carry out successively following link:

21) receive the sync message that adopts IEC 61588 accurate clock synchronization protocols;

22) record one time time error every 30 synchronizing cycles;

23) every 10 time errors are asked for a mean value and are drawn offset;

24) offset is covered to whole second time;

25) according to whole second Time Calculation, go out N _s, N ₁₀, N ₁₀₀, N ₁₀₀₀;

26) by N _s, N ₁₀, N ₁₀₀, N ₁₀₀₀set into corresponding register.

Having under synchronous situation, clock source initiation one in every 2 seconds is subsynchronous, by a synchronous error of 1 minute record of synchronous device.

The beneficial effect that the present invention reaches:

The method is in the situation that considering network delay, think by the mistiming between synchronous device and clock source it is to be caused by the otherness of two table apparatus clock crystal oscillators, by CPU (central processing unit), add up mistiming between the two of per minute and ask multiple averaging value as Crystal Oscillator Errors, in clock source lost contact situation, adopt the mode of FPGA frequency modulation to make up this Crystal Oscillator Errors, thus effectively solve by between synchronous device and clock source owing to there being the inconsistent impact of synchronizeing that oscillator frequency deviation causes.Adopt the smart machine of this punctual method, in 61588 synchronous clock source lost contact situations, its reliability, sensitivity and stability aspect meet the punctual requirement of intelligent substation completely.

Accompanying drawing explanation

The punctual main-process stream that arranges of Fig. 1 FPGA;

The normalization of Fig. 2 error and accumulation flow process;

Fig. 3 FPGA setting procedure of keeping time.

Embodiment

Below in conjunction with accompanying drawing, the invention will be further described.Following examples are only for technical scheme of the present invention is more clearly described, and can not limit the scope of the invention with this.

Based on 61588 punctual methods of FPGA frequency modulation strategy, the method includes the steps of:

1, the punctual main-process stream that arranges of FPGA

Having under 61588 synchronous situation, in clock source 2s, initiate one time 61588 synchronous, by a synchronous error of 1 minute record of synchronous device, flow process is as shown in Figure 1.This flow process completes synchronously when having 61588 synchronizing signal, completes the statistics of the mistiming producing due to intelligent apparatus crystal oscillator and in the inconsistent unit interval causing of main kind of crystal oscillator of main frame simultaneously.

2, error normalization and accumulation, flow process as shown in Figure 2.This flow process is the sub-process of flow process 1, completes the mistiming that every 30 statistical computations once produce due to intelligent apparatus crystal oscillator and in the inconsistent unit interval causing of main kind of crystal oscillator of main frame, and in order to eliminate error, the mistiming is the mean value of 10 errors.

3, FPGA is punctual arranges, and flow process as shown in Figure 3.This flow process is the punctual flow process of FPGA after 61588 synchronizing signals disappear, FPGA according to flow process 1 and flow process 2 at 10ms, 100ms, 1000ms compensation point to compensating tick number according to the offset calculating.

Specific algorithm is as follows:

Whole second:

T: according to clock source, calculate by number of whole second nanosecond of synchronous device;

N _s: by synchronous device, within whole second, interrupted number;

N ₁₀: 10ms offset registers tick number;

N ₁₀₀: 100ms offset registers tick number;

N ₁₀₀₀: 1000ms offset registers tick number;

F: system frequency;

F _s: sample frequency;

T _ns: the nanosecond number of each tick;

T _b: need compensation nanosecond number;

There is formula:

T=(N _s×f×f _s+N ₁₀×100+N ₁₀₀×10+N ₁₀₀₀)×T _ns+T _b；

According to above formula, by reverse derivation, calculate N _s, N ₁₀, N ₁₀₀, N ₁₀₀₀and set into corresponding register.

A kind of 61588 punctual methods based on FPGA frequency modulation strategy that the present invention puts forward, prerequisite is clock source and not affected by external condition by the crystal oscillator of synchronous device.Punctual method major embodiment proposed by the invention is in operating on the DSP of CPU (central processing unit) and the software of FPGA inside, and the FB(flow block) of software as shown in the FIG..Punctual method comprises the following steps:

1, initialization

1) N _s: according to this device acquiescence, number is interrupted in initialization break period for whole second;

2) N ₁₀: initialization 10ms offset registers tick number is 0;

3) N ₁₀₀: initialization 100ms offset registers tick number is 0;

4) N ₁₀₀₀: initialization 1000ms offset registers tick number is 0;

5) T _b: it is 0 that initialization need compensate nanosecond number;

2, in smart machine interrupts section, carry out successively following link:

1) receive 61588 sync messages;

2) record one time time error every 30 synchronizing cycles;

3) every 10 time errors are asked for a mean value and are drawn offset;

4) offset is covered to whole second time;

5) according to whole second Time Calculation, go out N _s, N ₁₀, N ₁₀₀, N ₁₀₀₀;

6) by N _s, N ₁₀, N ₁₀₀, N ₁₀₀₀set into corresponding register;

7) while having synchronizing signal, carry out synchronously, FPGA does not compensate the time;

8) after synchronizing signal disappears, FPGA starts the time to compensate.

Above-mentioned punctual method all can obtain desirable effect in smart machine, and be convenient to realize in the CPU (central processing unit) take DSP as core CPU and FPGA, for keeping time of synchro system 61588 clock source lost contacts, adopt this punctual tactful smart machine when 1588 clock source lost contact, aspect reliability, sensitivity and stability, to meet the punctual requirement of intelligent substation completely.

The above is only the preferred embodiment of the present invention; it should be pointed out that for those skilled in the art, do not departing under the prerequisite of the technology of the present invention principle; can also make some improvement and distortion, these improvement and distortion also should be considered as protection scope of the present invention.

Claims (2)

1. 61588 punctual methods based on FPGA frequency modulation strategy, it is characterized in that: in the intelligent substation of employing IEC 61850 standards, the time error that smart machine central processing unit CPU calculates according to clock source, by the each synchronometer of the crystal oscillator of synchronous device is worth by way of compensation, finely tune the tick number of FPGA clock counter, adopting in the synchronous clock source lost contact situation of IEC 61588 accurate clock synchronization protocols, adopt the mode of FPGA frequency modulation to make up this Crystal Oscillator Errors, comprise following steps:

(1) initialization

11) according to smart machine acquiescence, initialization break period is interrupted number N for whole second by synchronous device _s;

12) initialization 10ms offset registers tick counts N ₁₀be 0;

13) initialization 100ms offset registers tick counts N ₁₀₀be 0;

14) initialization 1000ms offset registers tick counts N ₁₀₀₀be 0;

15) initialization need compensate and nanosecond count T _bbe 0;

(2) in smart machine CPU each break period of section, carry out successively following link:

21) receive the sync message that adopts IEC 61588 accurate clock synchronization protocols;

22) record one time time error every 30 synchronizing cycles;

23) every 10 time errors are asked for a mean value and are drawn offset;

24) offset is covered to whole second time;

25) according to whole second Time Calculation, go out N _s, N ₁₀, N ₁₀₀, N ₁₀₀₀;

26) by N _s, N ₁₀, N ₁₀₀, N ₁₀₀₀set into corresponding register.

2. the 61588 punctual methods based on FPGA frequency modulation strategy according to claim 1, is characterized in that, are having synchronous in the situation that, and it is one subsynchronous that clock source is initiated for every 2 seconds, by a synchronous error of 1 minute record of synchronous device.

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