CN103716150A - MD5 and SHA-1 coprocessor suitable for SOC - Google Patents

Abstract

The invention discloses an MD5 and SHA-1 coprocessor suitable for an SOC. The MD5 and SHA-1 coprocessor suitable for the SOC comprises a DIN register, a SWAP module, an input FIFO module, a position supplementing module, a length supplementing module, an MD5 one-time operation module, an SHA-1 one-time operation module, a CR controller, an STR register, an IMR register and an abstract storage module. The MD5 and SHA-1 coprocessor can be connected to an APB bus, and the reusability of the coprocessor is enhanced to some degree. Due to the fact that the one-time operation modules are reused reasonably and the periodicity of operation is adjusted reasonably, the MD5 and SHA-1 coprocessor has the advantages of being small in area, high in speed, low in power consumption and the like.

Description

Be applicable to MD5 and the SHA-1 coprocessor of SOC

Technical field

The present invention relates to MD5/SHA-1 coprocessor, relate in particular to the MD5/SHA-1 coprocessor of the SOC that is applicable to adopt ARM core.

Background technology

At society, along with the development of the network information technology, the application of information security in every field seems more and more important.The safe transmission of guarantee information how, has become the focus of a trend and research.To cleartext information, encrypt and become cipher-text information reliability and fail safe in transmission and circulation with guarantee information, just like, information encryption has become distorting, losing in prevention cleartext information, ensures effective ways of its safety.Therefore, cryptographic algorithm has become importance and the part in cryptography, is also focus and the trend of society research.

MD5 and SHA-1 hashing algorithm can be realized with software, and still, along with the development of information technology, the shortcoming that software is realized seems obvious all the more.For example, execution speed is slow, is easily subjected to virus attack.Comparatively speaking, realize MD5 and SHA-l just do not have this situation with hardware, institute is so that the hardware implementation structure of research MD5 and SHA-1 algorithm becomes certainty.

Summary of the invention

For the problems referred to above, applicant through Improvement, provides MD5 and the SHA-1 coprocessor of a kind of SOC of being applicable to, has well solved the problem of arithmetic speed, area occupied, power consumption three aspects:.

Technical scheme of the present invention is as follows:

Be applicable to MD5 and a SHA-1 coprocessor of SOC, comprise DIN register, SWAP module, input fifo module, cover module, mend length module, MD5/SHA-1 arithmetic element, CR controller, STR register, IMR register and summary memory module; Wherein MD5/SHA-1 arithmetic element is comprised of MD5 single computing module and SHA-1 single computing module;

Described DIN register is connected with SWAP module with APB bus, and bit wide is 32bit, and it receives the message plaintext transmitting from APB bus, sends into subsequently SWAP module;

Described SWAP module is connected with input fifo module with DIN register, for carrying out the displacement of every bit, every byte, every half-word;

Described input fifo module is connected with cover module with SWAP module, in the mode of first-in first-out, stores the data after SWAP module displacement, when FIFO is filled with or computing during to last data block, the data in FIFO is sent into cover module;

Described cover module is connected with benefit length module with input fifo module, does not carry out cover computing when the number of bits of input data does not meet K*512+448, mends 1, all the other zero paddings for first; Described cover computing is undertaken by data amount check and state machine state in judgement FIFO, and when not needing cover, described cover module does not participate in computing;

Described benefit length module is connected with MD5/SHA-1 arithmetic element with cover module, is carrying out after the message of cover computing, represents the length of origination message with the binary data of 64; The computing of described benefit length is undertaken by data amount check and state machine state in judgement FIFO; Through cover with after mending length, form the data that length is the integral multiple of 512 bits, send into MD5/SHA-1 arithmetic element;

Described MD5 single computing module, for carrying out the computing of MD5 single, to 3 variable B, C, D does a logical operation according to Boolean function, and operation result is added in variables A; 32 place values of gained add a subgroup Mj and a constant ti of message itself, ring shift left s position; Wherein the constant ti of every group calculated in advance draw, with lookup table mode, participate in computing; S draws with the form of tabling look-up equally;

Described SHA-1 single computing module, for carrying out the computing of SHA-1 single, the Kt using in computing obtains with lookup table mode, and W0～W15 is known-plaintext message blocks, and W16～W19 takes turns before computing uses every, according to interative computation, obtains;

Described CR controller is connected with APB bus with MD5/SHA-1 arithmetic element, for by the configuration of APB bus, controls coprocessor and carries out that digest algorithm selection, coprocessor enable, data type is selected;

Described STR register is connected with APB bus with MD5/SHA-1 arithmetic element, is the status register of coprocessor, for reacting the current residing state of coprocessor, the empty full situation of FIFO;

Described IMR register is connected with APB bus with MD5/SHA-1 arithmetic element, for by the configuration of APB bus, enables coprocessor and interrupts;

Described summary memory module is connected with APB bus with MD5/SHA-1 arithmetic element, for the operation result of store M D5/SHA-1 arithmetic element, for APB bus, reads; In described summary memory module, have H0 H1 H2 H3 five 32-bit registers of H4, when using MD5 algorithm, register H0 H1 H2 H3 effective, when using SHA-1 algorithm, register H0 H1 H2 H3 H4 effective.

Useful technique effect of the present invention is:

The present invention, without software intervention, according to the judgement to FIFO and state machine situation, can automatically complete cover, mend size operation, has strengthened speed and the easy operating of computing.

The inventive example MD5 single computing module, every, adopt different Boolean functions, Mj, ti while taking turns computing, with this, reduce chip area, reduce power consumption.

The inventive example SHA-1 single computing module, every, adopt different Boolean functions, Kt, Wt while taking turns computing, with this, reduce chip area, reduce power consumption.

The present invention, by reading the data of STR register, can judge coprocessor status, and the empty full situation of FIFO, is convenient to software operation.

The present invention has more reasonably and controls power consumption.When needs are used MD5/SHA-1 coprocessor, enable MD5/SHA-1 coprocessor special clock; When not using MD5/SHA-1 coprocessor, to close clock and enable, this coprocessor just can not worked, and reduces chip power-consumption.

Accompanying drawing explanation

Fig. 1 is structured flowchart of the present invention.

Embodiment

Below in conjunction with accompanying drawing, the specific embodiment of the present invention is described further.

One, structure explanation:

Fig. 1 is that the present invention is applicable to the MD5 of SOC and the structured flowchart of SHA-1 coprocessor.See Fig. 1, the present invention is comprised of DIN register, SWAP module, input fifo module, cover module, benefit length module, MD5/SHA-1 arithmetic element, CR controller, STR register, IMR register and summary memory module.

DIN register, this register bit wide is 32bit, receives the message plaintext transmitting from APB bus.

SWAP module, this module can realize the displacement of every bit, every byte, every half-word, to meet the different input modes of software.

Input fifo module, this module is stored the data after SWAP module displacement in first-in first-out mode, whenever FIFO is filled with or computing during to last data block, data in FIFO is sent into cover module.

Cover module, when the number of bits of input data does not meet K*512+448, cover module completes cover computing automatically, mends 1, all the other zero paddings for first; This computing is carried out computing by data amount check and state machine state in judgement FIFO, without software intervention; When not needing cover, this module does not participate in computing.

Mend length module, carrying out after the message of cover computing, with the binary data of 64, represent the product degree of origination message; This computing is carried out computing by data amount check and state machine state in judgement FIFO, without software intervention; Through automatic cover with after mending length, the data length of sending into MD5/SHA-1 arithmetic element is the integral multiple of 512 bits.

MD5/SHA-1 arithmetic element is comprised of MD5 single computing module and SHA-1 single computing module.

MD5 single computing module, to 3 variable B, C, D does a logical operation according to Boolean function, and operation result is added in variables A; 32 place values of gained are added a subgroup Mj and a constant ti of message itself, the recirculation s position that moves to left; Wherein every group of ti calculated in advance draw, with lookup table mode, participate in computing, strengthened arithmetic speed; S draws with the form of tabling look-up equally.

SHA-1 single computing module, the Kt using in this computing obtains with lookup table mode, and W0～W15 is known-plaintext message blocks, and W16～W19 takes turns before computing uses every, obtains, to reduce chip area according to interative computation.

CR controller, this register is controlled coprocessor device and is carried out that digest algorithm selection, coprocessor enable, data type is selected.

STR register, the status register of coprocessor, this register has reacted the current residing state of coprocessor, the empty full situation of FIFO etc.

IMR register, can enable coprocessor by this register and interrupt.

Summary memory module, the result of store M D5/SHA-1 computing.

Two, operation principle explanation:

Before operation coprocessor of the present invention, by APB bus, configuration IMR register, the interruption of the computing that enabled once to make a summary;

By APB bus, configuration CR controller, selects the digest algorithm that uses, data type etc., and enable this invention coprocessor;

After completing the configuration of CR controller, IMR register, write the data of need encrypting by APB bus to DIN register, write 32-bit at every turn, the data that write carry out after position changes, depositing in the input fifo module of 16X32 through SWAP module;

When the data in input fifo module expire 512-bit, data are sent into SHA-1 single computing module or MD5 single computing module;

Data in input fifo module are less than 512-bit, and countless according to when input again, data in input fifo module are sent into cover module, mended length module, then the data of carrying out cover, benefit length are sent into SHA-1 single computing module or MD5 single computing module;

Utilize pipelining, repeatedly call SHA-1 single computing module or MD5 single computing module, complete digest algorithm, the summary obtaining is sent into summary memory module;

Summary have in memory module H0 H1 H2 H3 five 32-bit registers of H4, when using MD5 algorithm, only H0 H1 H2 H3 effective; When using SHA-1 algorithm, five registers are all effective;

After completing computing, produce and interrupt, notice CPU, CPU reads the value in summary memory module by APB bus.

Note: in the present invention, the MD5 algorithm that MD5/SHA-1 arithmetic element is in operation related and SHA-1 algorithm are prior art.

Above-described is only the preferred embodiment of the present invention, the invention is not restricted to above embodiment.Be appreciated that the oher improvements and changes that those skilled in the art directly derive or associate without departing from the spirit and concept in the present invention, within all should thinking and being included in protection scope of the present invention.

Claims (1)

1. the MD5 and the SHA-1 coprocessor that are applicable to SOC, is characterized in that: comprise DIN register, SWAP module, input fifo module, cover module, mend length module, MD5/SHA-1 arithmetic element, CR controller, STR register, IMR register and summary memory module; Wherein MD5/SHA-1 arithmetic element is comprised of MD5 single computing module and SHA-1 single computing module;

Described DIN register is connected with SWAP module with APB bus, and bit wide is 32bit, and it receives the message plaintext transmitting from APB bus, sends into subsequently SWAP module;

Described SWAP module is connected with input fifo module with DIN register, for carrying out the displacement of every bit, every byte, every half-word;

Described input fifo module is connected with cover module with SWAP module, in the mode of first-in first-out, stores the data after SWAP module displacement, when FIFO is filled with or computing during to last data block, the data in FIFO is sent into cover module;

Described cover module is connected with benefit length module with input fifo module, does not carry out cover computing when the number of bits of input data does not meet K*512+448, mends 1, all the other zero paddings for first; Described cover computing is undertaken by data amount check and state machine state in judgement FIFO, and when not needing cover, described cover module does not participate in computing;

Described benefit length module is connected with MD5/SHA-1 arithmetic element with cover module, is carrying out after the message of cover computing, represents the length of origination message with the binary data of 64; The computing of described benefit length is undertaken by data amount check and state machine state in judgement FIFO; Through cover with after mending length, form the data that length is the integral multiple of 512 bits, send into MD5/SHA-1 arithmetic element;

Described MD5 single computing module, for carrying out the computing of MD5 single, to 3 variable B, C, D does a logical operation according to Boolean function, and operation result is added in variables A; 32 place values of gained add a subgroup Mj and a constant ti of message itself, ring shift left s position; Wherein the constant ti of every group calculated in advance draw, with lookup table mode, participate in computing; S draws with the form of tabling look-up equally;

Described SHA-1 single computing module, for carrying out the computing of SHA-1 single, the Kt using in computing obtains with lookup table mode, and W0～W15 is known-plaintext message blocks, and W16～W19 takes turns before computing uses every, according to interative computation, obtains;

Described CR controller is connected with APB bus with MD5/SHA-1 arithmetic element, for by the configuration of APB bus, controls coprocessor and carries out that digest algorithm selection, coprocessor enable, data type is selected;

Described STR register is connected with APB bus with MD5/SHA-1 arithmetic element, is the status register of coprocessor, for reacting the current residing state of coprocessor, the empty full situation of FIFO;

Described IMR register is connected with APB bus with MD5/SHA-1 arithmetic element, for by the configuration of APB bus, enables coprocessor and interrupts;

Described summary memory module is connected with APB bus with MD5/SHA-1 arithmetic element, for the operation result of store M D5/SHA-1 arithmetic element, for APB bus, reads; In described summary memory module, have H0 H1 H2 H3 five 32-bit registers of H4, when using MD5 algorithm, register H0 H1 H2 H3 effective, when using SHA-1 algorithm, register H0 H1 H2 H3 H4 effective.

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